commit d73d8011779292788def2cd2520d6f39d9b406de
author Dan Williams <dan.j.williams@intel.com> Tue May 15 01:03:36 2007 +0100
committer Russell King <rmk+kernel@arm.linux.org.uk> Wed May 16 15:35:27 2007 +0100
tree 4a74fca4a1e549091414a0a0cbbc2cf63fcbd64e
parent e702a7155d14a6e11645e17d829217ae98fd45bb

[ARM] 4383/1: iop: fix usage of '__init' and 'inline' in iop files

WARNING: arch/arm/mach-iop13xx/built-in.o - Section mismatch: reference to
.init.text:iop13xx_pcie_map_irq from .text between 'iop13xx_pci_setup' (at
offset 0x7fc) and 'iop13xx_map_pci_memory'

While fixing this warning I also recalled Adrian Bunk's recommendation to
not use inline in .c files, as 'iop13xx_map_pci_memory' is needlessly
inlined.

Removing 'inline' uncovered some dead code so that is cleaned up as well.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

arch/arm/mach-iop33x/iq80331.c

diff --git a/arch/arm/mach-iop33x/iq80331.c b/arch/arm/mach-iop33x/iq80331.c
index 376c932..2b06318 100644
--- a/arch/arm/mach-iop33x/iq80331.c
+++ b/arch/arm/mach-iop33x/iq80331.c
@@ -55,7 +55,7 @@
 /*
  * IQ80331 PCI.
  */
-static inline int __init
+static int __init
 iq80331_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
 	int irq;

arch/arm/mach-iop33x/iq80332.c

diff --git a/arch/arm/mach-iop33x/iq80332.c b/arch/arm/mach-iop33x/iq80332.c
index 58c8149..7889ce3 100644
--- a/arch/arm/mach-iop33x/iq80332.c
+++ b/arch/arm/mach-iop33x/iq80332.c
@@ -55,7 +55,7 @@
 /*
  * IQ80332 PCI.
  */
-static inline int __init
+static int __init
 iq80332_pci_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
 {
 	int irq;

arch/arm/mach-iop33x/irq.c

diff --git a/arch/arm/mach-iop33x/irq.c b/arch/arm/mach-iop33x/irq.c
index c65ea78..f09dd05 100644
--- a/arch/arm/mach-iop33x/irq.c
+++ b/arch/arm/mach-iop33x/irq.c
@@ -22,32 +22,32 @@
 static u32 iop33x_mask0;
 static u32 iop33x_mask1;
 
-static inline void intctl0_write(u32 val)
+static void intctl0_write(u32 val)
 {
 	asm volatile("mcr p6, 0, %0, c0, c0, 0" : : "r" (val));
 }
 
-static inline void intctl1_write(u32 val)
+static void intctl1_write(u32 val)
 {
 	asm volatile("mcr p6, 0, %0, c1, c0, 0" : : "r" (val));
 }
 
-static inline void intstr0_write(u32 val)
+static void intstr0_write(u32 val)
 {
 	asm volatile("mcr p6, 0, %0, c2, c0, 0" : : "r" (val));
 }
 
-static inline void intstr1_write(u32 val)
+static void intstr1_write(u32 val)
 {
 	asm volatile("mcr p6, 0, %0, c3, c0, 0" : : "r" (val));
 }
 
-static inline void intbase_write(u32 val)
+static void intbase_write(u32 val)
 {
 	asm volatile("mcr p6, 0, %0, c12, c0, 0" : : "r" (val));
 }
 
-static inline void intsize_write(u32 val)
+static void intsize_write(u32 val)
 {
 	asm volatile("mcr p6, 0, %0, c13, c0, 0" : : "r" (val));
 }