drm/msm/dsi-staging: add support for non-embedded cmd transfer
Enable non-embedded mode hardware feature to transfer commands of size
greater than present DMA fifo size of 256 bytes.
Change-Id: I9763d364b6997e9efb5610d89b350f72966ea1cd
Signed-off-by: Vara Reddy <varar@codeaurora.org>
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c
index 0ddb47f..f2c2985 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c
@@ -83,6 +83,7 @@
dsi_ctrl_hw_14_reg_dump_to_buffer;
ctrl->ops.schedule_dma_cmd = NULL;
ctrl->ops.get_cont_splash_status = NULL;
+ ctrl->ops.kickoff_command_non_embedded_mode = NULL;
break;
case DSI_CTRL_VERSION_2_0:
ctrl->ops.setup_lane_map = dsi_ctrl_hw_20_setup_lane_map;
@@ -97,6 +98,7 @@
ctrl->ops.clamp_disable = NULL;
ctrl->ops.schedule_dma_cmd = NULL;
ctrl->ops.get_cont_splash_status = NULL;
+ ctrl->ops.kickoff_command_non_embedded_mode = NULL;
break;
case DSI_CTRL_VERSION_2_2:
ctrl->ops.phy_reset_config = dsi_ctrl_hw_22_phy_reset_config;
@@ -113,6 +115,8 @@
ctrl->ops.clamp_enable = NULL;
ctrl->ops.clamp_disable = NULL;
ctrl->ops.schedule_dma_cmd = dsi_ctrl_hw_22_schedule_dma_cmd;
+ ctrl->ops.kickoff_command_non_embedded_mode =
+ dsi_ctrl_hw_kickoff_non_embedded_mode;
break;
default:
break;
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h
index 735f61f..f7756dc 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h
@@ -213,6 +213,9 @@
ssize_t dsi_ctrl_hw_20_reg_dump_to_buffer(struct dsi_ctrl_hw *ctrl,
char *buf,
u32 size);
+void dsi_ctrl_hw_kickoff_non_embedded_mode(struct dsi_ctrl_hw *ctrl,
+ struct dsi_ctrl_cmd_dma_info *cmd,
+ u32 flags);
/* Definitions specific to 2.2 DSI controller hardware */
bool dsi_ctrl_hw_22_get_cont_splash_status(struct dsi_ctrl_hw *ctrl);
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
index 1f10e3c..609ae52 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c
@@ -940,6 +940,62 @@
udelay(sleep_ms * 1000);
}
+void dsi_message_setup_tx_mode(struct dsi_ctrl *dsi_ctrl,
+ u32 cmd_len,
+ u32 *flags)
+{
+ /**
+ * Setup the mode of transmission
+ * override cmd fetch mode during secure session
+ */
+ if (dsi_ctrl->secure_mode) {
+ *flags &= ~DSI_CTRL_CMD_FETCH_MEMORY;
+ *flags |= DSI_CTRL_CMD_FIFO_STORE;
+ pr_debug("[%s] override to TPG during secure session\n",
+ dsi_ctrl->name);
+ return;
+ }
+
+ /* Check to see if cmd len plus header is greater than fifo size */
+ if ((cmd_len + 4) > DSI_EMBEDDED_MODE_DMA_MAX_SIZE_BYTES) {
+ *flags |= DSI_CTRL_CMD_NON_EMBEDDED_MODE;
+ pr_debug("[%s] override to non-embedded mode,cmd len =%d\n",
+ dsi_ctrl->name, cmd_len);
+ return;
+ }
+}
+
+int dsi_message_validate_tx_mode(struct dsi_ctrl *dsi_ctrl,
+ u32 cmd_len,
+ u32 *flags)
+{
+ int rc = 0;
+
+ if (*flags & DSI_CTRL_CMD_FIFO_STORE) {
+ /* if command size plus header is greater than fifo size */
+ if ((cmd_len + 4) > DSI_CTRL_MAX_CMD_FIFO_STORE_SIZE) {
+ pr_err("Cannot transfer Cmd in FIFO config\n");
+ return -ENOTSUPP;
+ }
+ if (!dsi_ctrl->hw.ops.kickoff_fifo_command) {
+ pr_err("Cannot transfer command,ops not defined\n");
+ return -ENOTSUPP;
+ }
+ }
+
+ if (*flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
+ if (*flags & DSI_CTRL_CMD_BROADCAST) {
+ pr_err("Non embedded not supported with broadcast\n");
+ return -ENOTSUPP;
+ }
+ if (!dsi_ctrl->hw.ops.kickoff_command_non_embedded_mode) {
+ pr_err(" Cannot transfer command,ops not defined\n");
+ return -ENOTSUPP;
+ }
+ }
+ return rc;
+}
+
static int dsi_message_tx(struct dsi_ctrl *dsi_ctrl,
const struct mipi_dsi_msg *msg,
u32 flags)
@@ -955,12 +1011,34 @@
u8 *cmdbuf;
struct dsi_mode_info *timing;
- /* override cmd fetch mode during secure session */
- if (dsi_ctrl->secure_mode) {
- flags &= ~DSI_CTRL_CMD_FETCH_MEMORY;
- flags |= DSI_CTRL_CMD_FIFO_STORE;
- pr_debug("[%s] override to TPG during secure session\n",
- dsi_ctrl->name);
+ /* Select the tx mode to transfer the command */
+ dsi_message_setup_tx_mode(dsi_ctrl, msg->tx_len, &flags);
+
+ /* Validate the mode before sending the command */
+ rc = dsi_message_validate_tx_mode(dsi_ctrl, msg->tx_len, &flags);
+ if (rc) {
+ pr_err(" Cmd tx validation failed, cannot transfer cmd\n");
+ rc = -ENOTSUPP;
+ goto error;
+ }
+
+ if (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
+ cmd_mem.offset = dsi_ctrl->cmd_buffer_iova;
+ cmd_mem.en_broadcast = (flags & DSI_CTRL_CMD_BROADCAST) ?
+ true : false;
+ cmd_mem.is_master = (flags & DSI_CTRL_CMD_BROADCAST_MASTER) ?
+ true : false;
+ cmd_mem.use_lpm = (msg->flags & MIPI_DSI_MSG_USE_LPM) ?
+ true : false;
+ cmd_mem.datatype = msg->type;
+ cmd_mem.length = msg->tx_len;
+
+ dsi_ctrl->cmd_len = msg->tx_len;
+ memcpy(dsi_ctrl->vaddr, msg->tx_buf, msg->tx_len);
+ pr_debug(" non-embedded mode , size of command =%zd\n",
+ msg->tx_len);
+
+ goto kickoff;
}
rc = mipi_dsi_create_packet(&packet, msg);
@@ -969,16 +1047,6 @@
goto error;
}
- /* fail cmds more than the supported size in TPG mode */
- if ((flags & DSI_CTRL_CMD_FIFO_STORE) &&
- (msg->tx_len > DSI_CTRL_MAX_CMD_FIFO_STORE_SIZE)) {
- pr_err("[%s] TPG cmd size:%zd not supported, secure:%d\n",
- dsi_ctrl->name, msg->tx_len,
- dsi_ctrl->secure_mode);
- rc = -ENOTSUPP;
- goto error;
- }
-
rc = dsi_ctrl_copy_and_pad_cmd(dsi_ctrl,
&packet,
&buffer,
@@ -993,6 +1061,7 @@
buffer[3] |= BIT(7);//set the last cmd bit in header.
if (flags & DSI_CTRL_CMD_FETCH_MEMORY) {
+ /* Embedded mode config is selected */
cmd_mem.offset = dsi_ctrl->cmd_buffer_iova;
cmd_mem.en_broadcast = (flags & DSI_CTRL_CMD_BROADCAST) ?
true : false;
@@ -1026,6 +1095,7 @@
true : false;
}
+kickoff:
timing = &(dsi_ctrl->host_config.video_timing);
if (timing)
line_no += timing->v_back_porch + timing->v_sync_width +
@@ -1045,9 +1115,18 @@
if (flags & DSI_CTRL_CMD_DEFER_TRIGGER) {
if (flags & DSI_CTRL_CMD_FETCH_MEMORY) {
- dsi_ctrl->hw.ops.kickoff_command(&dsi_ctrl->hw,
+ if (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
+ dsi_ctrl->hw.ops.
+ kickoff_command_non_embedded_mode(
+ &dsi_ctrl->hw,
&cmd_mem,
hw_flags);
+ } else {
+ dsi_ctrl->hw.ops.kickoff_command(
+ &dsi_ctrl->hw,
+ &cmd_mem,
+ hw_flags);
+ }
} else if (flags & DSI_CTRL_CMD_FIFO_STORE) {
dsi_ctrl->hw.ops.kickoff_fifo_command(&dsi_ctrl->hw,
&cmd,
@@ -1065,9 +1144,18 @@
reinit_completion(&dsi_ctrl->irq_info.cmd_dma_done);
if (flags & DSI_CTRL_CMD_FETCH_MEMORY) {
- dsi_ctrl->hw.ops.kickoff_command(&dsi_ctrl->hw,
- &cmd_mem,
- hw_flags);
+ if (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
+ dsi_ctrl->hw.ops.
+ kickoff_command_non_embedded_mode(
+ &dsi_ctrl->hw,
+ &cmd_mem,
+ hw_flags);
+ } else {
+ dsi_ctrl->hw.ops.kickoff_command(
+ &dsi_ctrl->hw,
+ &cmd_mem,
+ hw_flags);
+ }
} else if (flags & DSI_CTRL_CMD_FIFO_STORE) {
dsi_ctrl->hw.ops.kickoff_fifo_command(&dsi_ctrl->hw,
&cmd,
@@ -1106,6 +1194,16 @@
dsi_ctrl->hw.ops.mask_error_intr(&dsi_ctrl->hw,
BIT(DSI_FIFO_OVERFLOW), false);
dsi_ctrl->hw.ops.reset_cmd_fifo(&dsi_ctrl->hw);
+
+ /*
+ * DSI 2.2 needs a soft reset whenever we send non-embedded
+ * mode command followed by embedded mode. Otherwise it will
+ * result in smmu write faults with DSI as client.
+ */
+ if (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
+ dsi_ctrl->hw.ops.soft_reset(&dsi_ctrl->hw);
+ dsi_ctrl->cmd_len = 0;
+ }
}
error:
if (buffer)
@@ -2682,6 +2780,11 @@
if (dsi_ctrl->hw.ops.mask_error_intr)
dsi_ctrl->hw.ops.mask_error_intr(&dsi_ctrl->hw,
BIT(DSI_FIFO_OVERFLOW), false);
+
+ if (flags & DSI_CTRL_CMD_NON_EMBEDDED_MODE) {
+ dsi_ctrl->hw.ops.soft_reset(&dsi_ctrl->hw);
+ dsi_ctrl->cmd_len = 0;
+ }
}
mutex_unlock(&dsi_ctrl->ctrl_lock);
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h
index f5b08a0..80b91ca 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h
@@ -37,6 +37,7 @@
* and transfer it.
* @DSI_CTRL_CMD_LAST_COMMAND: Trigger the DMA cmd transfer if this is last
* command in the batch.
+ * @DSI_CTRL_CMD_NON_EMBEDDED_MODE:Trasfer cmd packets in non embedded mode.
*/
#define DSI_CTRL_CMD_READ 0x1
#define DSI_CTRL_CMD_BROADCAST 0x2
@@ -45,6 +46,12 @@
#define DSI_CTRL_CMD_FIFO_STORE 0x10
#define DSI_CTRL_CMD_FETCH_MEMORY 0x20
#define DSI_CTRL_CMD_LAST_COMMAND 0x40
+#define DSI_CTRL_CMD_NON_EMBEDDED_MODE 0x80
+
+/* DSI embedded mode fifo size
+ * If the command is greater than 256 bytes it is sent in non-embedded mode.
+ */
+#define DSI_EMBEDDED_MODE_DMA_MAX_SIZE_BYTES 256
/* max size supported for dsi cmd transfer using TPG */
#define DSI_CTRL_MAX_CMD_FIFO_STORE_SIZE 64
@@ -680,4 +687,20 @@
*/
int dsi_ctrl_vid_engine_en(struct dsi_ctrl *dsi_ctrl, bool on);
+/**
+ * @dsi_ctrl: DSI controller handle.
+ * cmd_len: Length of command.
+ * flags: Config mode flags.
+ */
+void dsi_message_setup_tx_mode(struct dsi_ctrl *dsi_ctrl, u32 cmd_len,
+ u32 *flags);
+
+/**
+ * @dsi_ctrl: DSI controller handle.
+ * cmd_len: Length of command.
+ * flags: Config mode flags.
+ */
+int dsi_message_validate_tx_mode(struct dsi_ctrl *dsi_ctrl, u32 cmd_len,
+ u32 *flags);
+
#endif /* _DSI_CTRL_H_ */
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h
index c77065c..567f289 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h
@@ -296,6 +296,7 @@
* struct dsi_ctrl_cmd_dma_info - command buffer information
* @offset: IOMMU VA for command buffer address.
* @length: Length of the command buffer.
+ * @datatype: Datatype of cmd.
* @en_broadcast: Enable broadcast mode if set to true.
* @is_master: Is master in broadcast mode.
* @use_lpm: Use low power mode for command transmission.
@@ -303,6 +304,7 @@
struct dsi_ctrl_cmd_dma_info {
u32 offset;
u32 length;
+ u8 datatype;
bool en_broadcast;
bool is_master;
bool use_lpm;
@@ -497,6 +499,25 @@
u32 flags);
/**
+ * kickoff_command_non_embedded_mode() - cmd in non embedded mode
+ * @ctrl: Pointer to the controller host hardware.
+ * @cmd: Command information.
+ * @flags: Modifiers for command transmission.
+ *
+ * If command length is greater than DMA FIFO size of 256 bytes we use
+ * this non- embedded mode.
+ * The controller hardware is programmed with address and size of the
+ * command buffer. The transmission is kicked off if
+ * DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER flag is not set. If this flag is
+ * set, caller should make a separate call to trigger_command_dma() to
+ * transmit the command.
+ */
+
+ void (*kickoff_command_non_embedded_mode)(struct dsi_ctrl_hw *ctrl,
+ struct dsi_ctrl_cmd_dma_info *cmd,
+ u32 flags);
+
+ /**
* kickoff_fifo_command() - transmits a command using FIFO in dsi
* hardware.
* @ctrl: Pointer to the controller host hardware.
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_2.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_2.c
index 650c2e0..d94d6f7b 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_2.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_2.c
@@ -79,3 +79,48 @@
reg = DSI_R32(ctrl, DSI_SCRATCH_REGISTER_1);
return reg == 0x1 ? true : false;
}
+
+/*
+ * dsi_ctrl_hw_kickoff_non_embedded_mode()-Kickoff cmd in non-embedded mode
+ * @ctrl: - Pointer to the controller host hardware.
+ * @dsi_ctrl_cmd_dma_info: - command buffer information.
+ * @flags: - DSI CTRL Flags.
+ */
+void dsi_ctrl_hw_kickoff_non_embedded_mode(struct dsi_ctrl_hw *ctrl,
+ struct dsi_ctrl_cmd_dma_info *cmd,
+ u32 flags)
+{
+ u32 reg = 0;
+
+ reg = DSI_R32(ctrl, DSI_COMMAND_MODE_DMA_CTRL);
+
+ reg &= ~BIT(31);/* disable broadcast */
+ reg &= ~BIT(30);
+
+ if (cmd->use_lpm)
+ reg |= BIT(26);
+ else
+ reg &= ~BIT(26);
+
+ /* Select non EMBEDDED_MODE, pick the packet header from register */
+ reg &= ~BIT(28);
+ reg |= BIT(24);/* long packet */
+ reg |= BIT(29);/* wc_sel = 1 */
+ reg |= (((cmd->datatype) & 0x03f) << 16);/* data type */
+ DSI_W32(ctrl, DSI_COMMAND_MODE_DMA_CTRL, reg);
+
+ /* Enable WRITE_WATERMARK_DISABLE and READ_WATERMARK_DISABLE bits */
+ reg = DSI_R32(ctrl, DSI_DMA_FIFO_CTRL);
+ reg |= BIT(20);
+ reg |= BIT(16);
+ DSI_W32(ctrl, DSI_DMA_FIFO_CTRL, reg);
+
+ DSI_W32(ctrl, DSI_DMA_CMD_OFFSET, cmd->offset);
+ DSI_W32(ctrl, DSI_DMA_CMD_LENGTH, ((cmd->length) & 0xFFFFFF));
+
+ /* wait for writes to complete before kick off */
+ wmb();
+
+ if (!(flags & DSI_CTRL_HW_CMD_WAIT_FOR_TRIGGER))
+ DSI_W32(ctrl, DSI_CMD_MODE_DMA_SW_TRIGGER, 0x1);
+}
diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c
index c2c8f57..c753c80 100644
--- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c
+++ b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c
@@ -612,9 +612,17 @@
else
reg &= ~BIT(26);
- reg |= BIT(28);
+ reg |= BIT(28);/* Select embedded mode */
+ reg &= ~BIT(24);/* packet type */
+ reg &= ~BIT(29);/* WC_SEL to 0 */
DSI_W32(ctrl, DSI_COMMAND_MODE_DMA_CTRL, reg);
+ reg = DSI_R32(ctrl, DSI_DMA_FIFO_CTRL);
+ reg &= ~BIT(20);/* Enable write watermark*/
+ reg &= ~BIT(16);/* Enable read watermark */
+
+
+ DSI_W32(ctrl, DSI_DMA_FIFO_CTRL, reg);
DSI_W32(ctrl, DSI_DMA_CMD_OFFSET, cmd->offset);
DSI_W32(ctrl, DSI_DMA_CMD_LENGTH, (cmd->length & 0xFFFFFF));