arch/arm64/boot/dts/qcom/sdm670-coresight.dtsi

/* Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 and
 * only version 2 as published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
&soc {

	csr: csr@6001000 {
		compatible = "qcom,coresight-csr";
		reg = <0x6001000 0x1000>;
		reg-names = "csr-base";

		coresight-name = "coresight-csr";

		qcom,usb-bam-support;
		qcom,hwctrl-set-support;
		qcom,set-byte-cntr-support;
		qcom,blk-size = <1>;
	};

	replicator_qdss: replicator@6046000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b909>;

		reg = <0x6046000 0x1000>;
		reg-names = "replicator-base";

		coresight-name = "coresight-replicator";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				replicator_out_tmc_etr: endpoint {
					remote-endpoint =
						<&tmc_etr_in_replicator>;
				};
			};

			port@1 {
				reg = <0>;
				replicator_in_tmc_etf: endpoint {
					slave-mode;
					remote-endpoint =
						<&tmc_etf_out_replicator>;
				};
			};
		};
	};

	tmc_etr: tmc@6048000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b961>;

		reg = <0x6048000 0x1000>,
		      <0x6064000 0x15000>;
		reg-names = "tmc-base", "bam-base";

		arm,buffer-size = <0x400000>;
		arm,sg-enable;

		coresight-name = "coresight-tmc-etr";
		coresight-ctis = <&cti0 &cti8>;
		coresight-csr = <&csr>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		interrupts = <GIC_SPI 270 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "byte-cntr-irq";

		port {
			tmc_etr_in_replicator: endpoint {
				slave-mode;
				remote-endpoint = <&replicator_out_tmc_etr>;
			};
		};
	};

	replicator_swao: replicator@6b0a000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b909>;

		reg = <0x6b0a000 0x1000>;
		reg-names = "replicator-base";

		coresight-name = "coresight-replicator-swao";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				replicator_swao_in_tmc_etf_swao: endpoint {
					slave-mode;
					remote-endpoint =
						<&tmc_etf_swao_out_replicator>;
				};
			};

			port@1 {
				reg = <0>;
				replicator_swao_out_funnel_in2: endpoint {
					remote-endpoint =
					      <&funnel_in2_in_replicator_swao>;
				};
			};
		};
	};

	tmc_etf_swao: tmc@6b09000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b961>;

		reg = <0x6b09000 0x1000>;
		reg-names = "tmc-base";

		coresight-name = "coresight-tmc-etf-swao";
		coresight-csr = <&csr>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				tmc_etf_swao_out_replicator: endpoint {
					remote-endpoint=
					  <&replicator_swao_in_tmc_etf_swao>;
				};
			};

			port@1 {
				reg = <0>;
				tmc_etf_swao_in_funnel_swao: endpoint {
					slave-mode;
					remote-endpoint=
					  <&funnel_swao_out_tmc_etf_swao>;
				};
			};
		};
	};

	funnel_swao:funnel@0x6b08000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6b08000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-swao";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_swao_out_tmc_etf_swao: endpoint {
					remote-endpoint =
						<&tmc_etf_swao_in_funnel_swao>;
				};
			};

			port@1 {
				reg = <6>;
				funnel_swao_in_sensor_etm0: endpoint {
					slave-mode;
					remote-endpoint=
						<&sensor_etm0_out_funnel_swao>;
				};
			};

			port@2 {
				reg = <7>;
				funnel_swao_in_tpda_swao: endpoint {
					slave-mode;
					remote-endpoint=
						<&tpda_swao_out_funnel_swao>;
				};
			};
		};
	};

	tpda_swao: tpda@6b01000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x6b01000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-swao";

		qcom,tpda-atid = <71>;
		qcom,dsb-elem-size = <1 32>;
		qcom,cmb-elem-size = <0 64>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				tpda_swao_out_funnel_swao: endpoint {
					remote-endpoint =
						<&funnel_swao_in_tpda_swao>;
				};
			};

			port@1 {
				reg = <0>;
				tpda_swao_in_tpdm_swao0: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_swao0_out_tpda_swao>;
				};
			};

			port@2 {
				reg = <1>;
				tpda_swao_in_tpdm_swao1: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_swao1_out_tpda_swao>;
				};
			};
		};
	};

	tpdm_swao0: tpdm@6b02000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;

		reg = <0x6b02000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-swao-0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_swao0_out_tpda_swao: endpoint {
			remote-endpoint = <&tpda_swao_in_tpdm_swao0>;
			 };
		};
	};

	tpdm_swao1: tpdm@6b03000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x6b03000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name="coresight-tpdm-swao-1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,msr-fix-req;

		port {
			tpdm_swao1_out_tpda_swao: endpoint {
				remote-endpoint = <&tpda_swao_in_tpdm_swao1>;
			};
		};
	};

	tmc_etf: tmc@6047000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b961>;

		reg = <0x6047000 0x1000>;
		reg-names = "tmc-base";

		coresight-name = "coresight-tmc-etf";
		coresight-ctis = <&cti0 &cti8>;
		arm,default-sink;
		coresight-csr = <&csr>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				tmc_etf_out_replicator: endpoint {
					remote-endpoint =
						<&replicator_in_tmc_etf>;
				};
			};

			port@1 {
				reg = <1>;
				tmc_etf_in_funnel_merg: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_merg_out_tmc_etf>;
				};
			};
		};

	};

	funnel_merg: funnel@6045000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6045000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-merg";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_merg_out_tmc_etf: endpoint {
					remote-endpoint =
						<&tmc_etf_in_funnel_merg>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_merg_in_funnel_in0: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_in0_out_funnel_merg>;
				};
			};

			port@2 {
				reg = <1>;
				funnel_merg_in_funnel_in1: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_in1_out_funnel_merg>;
				};
			};

			port@3 {
				reg = <2>;
				funnel_merg_in_funnel_in2: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_in2_out_funnel_merg>;
				};
			};
		};
	};

	stm: stm@6002000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b962>;

		reg = <0x6002000 0x1000>,
		      <0x16280000 0x180000>;
		reg-names = "stm-base", "stm-stimulus-base";

		coresight-name = "coresight-stm";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			stm_out_funnel_in0: endpoint {
				remote-endpoint = <&funnel_in0_in_stm>;
			};
		};

	};

	hwevent: hwevent@0x014066f0 {
		compatible = "qcom,coresight-hwevent";
		reg = <0x14066f0 0x4>,
		      <0x14166f0 0x4>,
		      <0x1406038 0x4>,
		      <0x1416038 0x4>;
		reg-names = "ddr-ch0-cfg", "ddr-ch23-cfg", "ddr-ch0-ctrl",
			    "ddr-ch23-ctrl";

		coresight-csr = <&csr>;
		coresight-name = "coresight-hwevent";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	funnel_in0: funnel@0x6041000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6041000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-in0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_in0_out_funnel_merg: endpoint {
					remote-endpoint =
						<&funnel_merg_in_funnel_in0>;
				};
			};

			port@1 {
				reg = <6>;
				funnel_in0_in_funnel_qatb: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_qatb_out_funnel_in0>;
				};
			};

			port@2 {
				reg = <7>;
				funnel_in0_in_stm: endpoint {
					slave-mode;
					remote-endpoint = <&stm_out_funnel_in0>;
				};
			};
		};
	};

	funnel_in1: funnel@0x6042000 {
		 compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6042000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-in1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";


		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_in1_out_funnel_merg: endpoint {
					remote-endpoint =
					  <&funnel_merg_in_funnel_in1>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_in1_in_audio_etm0: endpoint {
					slave-mode;
					remote-endpoint =
						<&audio_etm0_out_funnel_in1>;
				};
			};

			port@2 {
				reg = <0>;
				funnel_in1_in_tpdm_lpass: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpdm_lpass_out_funnel_in1>;
				};
			};
		};
	};

	funnel_in2: funnel@0x6043000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6043000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-in2";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_in2_out_funnel_merg: endpoint {
					remote-endpoint =
					  <&funnel_merg_in_funnel_in2>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_in2_in_modem_etm0: endpoint {
					slave-mode;
					remote-endpoint =
					  <&modem_etm0_out_funnel_in2>;
				};

			};

			port@2 {
				reg = <1>;
				funnel_in2_in_replicator_swao: endpoint {
					slave-mode;
					remote-endpoint =
					  <&replicator_swao_out_funnel_in2>;
				};
			};
			port@3 {
				reg = <2>;
				funnel_in2_in_funnel_modem: endpoint {
					slave-mode;
					remote-endpoint =
					  <&funnel_modem_out_funnel_in2>;
				};
			};
			port@4 {
				reg = <5>;
				funnel_in2_in_funnel_apss_merg: endpoint {
					slave-mode;
					remote-endpoint =
					  <&funnel_apss_merg_out_funnel_in2>;
				};
			};
			port@5 {
				reg = <6>;
				funnel_in2_in_funnel_gfx: endpoint {
					slave-mode;
					remote-endpoint =
					  <&funnel_gfx_out_funnel_in2>;
				};
			};
		};
	};

	funnel_gfx: funnel@0x6943000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6943000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-gfx";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		status = "disabled";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_gfx_out_funnel_in2: endpoint {
					remote-endpoint =
					  <&funnel_in2_in_funnel_gfx>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_in2_in_gfx: endpoint {
					slave-mode;
					remote-endpoint =
					  <&gfx_out_funnel_in2>;
				};
			};

			port@2 {
				reg = <1>;
				funnel_in2_in_gfx_cx: endpoint {
					slave-mode;
					remote-endpoint =
					  <&gfx_cx_out_funnel_in2>;
				};
			};
		};
	};

	tpda: tpda@6004000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x6004000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda";

		qcom,tpda-atid = <65>;
		qcom,bc-elem-size = <10 32>,
				    <13 32>;
		qcom,tc-elem-size = <13 32>;
		qcom,dsb-elem-size = <0 32>,
				     <2 32>,
				     <3 32>,
				     <5 32>,
				     <6 32>,
				     <10 32>,
				     <11 32>,
				     <13 32>;
		qcom,cmb-elem-size = <3 64>,
				     <7 64>,
				     <9 64>,
				     <13 64>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				tpda_out_funnel_qatb: endpoint {
					remote-endpoint =
						<&funnel_qatb_in_tpda>;
				};

			};

			port@1 {
				reg = <0>;
				tpda_in_tpdm_center: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_center_out_tpda>;
				};
			};

			port@2 {
				reg = <2>;
				tpda_in_funnel_dl_mm: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_dl_mm_out_tpda>;
				};
			};

			port@3 {
				reg = <3>;
				tpda_in_funnel_ddr_0: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_ddr_0_out_tpda>;
				};
			};

			port@4 {
				reg = <6>;
				tpda_in_funnel_turing: endpoint {
					slave-mode;
					remote-endpoint =
						<&funnel_turing_out_tpda>;
				};
			};

			port@5 {
				reg = <7>;
				tpda_in_tpdm_vsense: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_vsense_out_tpda>;
				};
			};

			port@6 {
				reg = <9>;
				tpda_in_tpdm_prng: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_prng_out_tpda>;
				};
			};

			port@7 {
				reg = <11>;
					tpda_in_tpdm_north: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_north_out_tpda>;
				};
			};

			port@8 {
				reg = <12>;
				tpda_in_tpdm_qm: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_qm_out_tpda>;
				};
			};

			port@9 {
				reg = <13>;
				tpda_in_tpdm_pimem: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_pimem_out_tpda>;
				};
			};
		};
	};

	funnel_modem: funnel@6832000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6832000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-modem";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_modem_out_funnel_in2: endpoint {
					remote-endpoint =
					    <&funnel_in2_in_funnel_modem>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_modem_in_tpda_modem: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpda_modem_out_funnel_modem>;
				};
			};
		};
	};

	tpda_modem: tpda@6831000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x6831000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-modem";

		qcom,tpda-atid = <67>;
		qcom,dsb-elem-size = <0 32>;
		qcom,cmb-elem-size = <0 64>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				tpda_modem_out_funnel_modem: endpoint {
					remote-endpoint =
						<&funnel_modem_in_tpda_modem>;
				};
			};

			port@1 {
				reg = <0>;
				tpda_modem_in_tpdm_modem: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_modem_out_tpda_modem>;
				};
			};
		};
	};

	tpdm_modem: tpdm@6830000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x6830000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-modem";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_modem_out_tpda_modem: endpoint {
				remote-endpoint = <&tpda_modem_in_tpdm_modem>;
			};
		};
	};

	tpdm_prng: tpdm@684c000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x684c000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-prng";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_prng_out_tpda: endpoint {
				remote-endpoint = <&tpda_in_tpdm_prng>;
			};
		};
	};

	tpdm_center: tpdm@6c28000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x6c28000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-center";

		qcom,msr-fix-req;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_center_out_tpda: endpoint {
				remote-endpoint = <&tpda_in_tpdm_center>;
			};
		};
	};

	tpdm_north: tpdm@6a24000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x6a24000 0x1000>;
		reg-names = "tpdm-base";

		qcom,msr-fix-req;

		coresight-name = "coresight-tpdm-north";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_north_out_tpda: endpoint {
				remote-endpoint = <&tpda_in_tpdm_north>;
			};
		};
	};

	tpdm_qm: tpdm@69d0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x69d0000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-qm";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_qm_out_tpda: endpoint {
				remote-endpoint = <&tpda_in_tpdm_qm>;
			};
		};
	};

	tpda_apss: tpda@7862000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x7862000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-apss";

		qcom,tpda-atid = <66>;
		qcom,dsb-elem-size = <0 32>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				tpda_apss_out_funnel_apss_merg: endpoint {
					remote-endpoint =
					       <&funnel_apss_merg_in_tpda_apss>;
				};
			};

			port@1 {
				reg = <0>;
				tpda_apss_in_tpdm_apss: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_apss_out_tpda_apss>;
				};
			};
		};
	};

	tpdm_apss: tpdm@7860000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x7860000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-apss";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_apss_out_tpda_apss: endpoint {
				remote-endpoint = <&tpda_apss_in_tpdm_apss>;
			};
		};
	};

	tpda_llm_silver: tpda@78c0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x78c0000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-llm-silver";

		qcom,tpda-atid = <72>;
		qcom,cmb-elem-size = <0 32>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				tpda_llm_silver_out_funnel_apss_merg: endpoint {
				remote-endpoint =
					<&funnel_apss_merg_in_tpda_llm_silver>;
				};
			};

			port@1 {
				reg = <0>;
				tpda_llm_silver_in_tpdm_llm_silver: endpoint {
				slave-mode;
				remote-endpoint =
					<&tpdm_llm_silver_out_tpda_llm_silver>;
				};
			};
		};
	};

	tpdm_llm_silver: tpdm@78a0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x78a0000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-llm-silver";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_llm_silver_out_tpda_llm_silver: endpoint {
				remote-endpoint =
					<&tpda_llm_silver_in_tpdm_llm_silver>;
			};
		};
	};

	tpda_llm_gold: tpda@78d0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x78d0000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-llm-gold";

		qcom,tpda-atid = <73>;
		qcom,cmb-elem-size = <0 32>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				tpda_llm_gold_out_funnel_apss_merg: endpoint {
					remote-endpoint =
					  <&funnel_apss_merg_in_tpda_llm_gold>;
				};
			};

			port@1 {
				reg = <0>;
				tpda_llm_gold_in_tpdm_llm_gold: endpoint {
					slave-mode;
					remote-endpoint =
					  <&tpdm_llm_gold_out_tpda_llm_gold>;
				};
			};
		};
	};

	tpdm_llm_gold: tpdm@78b0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x78b0000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-llm-gold";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_llm_gold_out_tpda_llm_gold: endpoint {
				remote-endpoint =
				    <&tpda_llm_gold_in_tpdm_llm_gold>;
			};
		};
	};

	funnel_dl_mm: funnel@6c0b000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6c0b000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-dl-mm";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_dl_mm_out_tpda: endpoint {
					remote-endpoint =
					    <&tpda_in_funnel_dl_mm>;
				};
			};

			port@1 {
				reg = <1>;
				funnel_dl_mm_in_tpdm_mm: endpoint {
					slave-mode;
					remote-endpoint =
					    <&tpdm_mm_out_funnel_dl_mm>;
				};
			};
		};
	};

	tpdm_mm: tpdm@6c08000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x6c08000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-mm";

		qcom,msr-fix-req;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_mm_out_funnel_dl_mm: endpoint {
				remote-endpoint = <&funnel_dl_mm_in_tpdm_mm>;
			};
		};
	};

	funnel_turing: funnel@6861000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6861000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-turing";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_turing_out_tpda: endpoint {
					remote-endpoint =
					    <&tpda_in_funnel_turing>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_turing_in_tpdm_turing: endpoint {
					slave-mode;
					remote-endpoint =
					    <&tpdm_turing_out_funnel_turing>;
				};
			};
		};
	};

	funnel_turing_1: funnel_1@6861000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6867000 0x10>,
		      <0x6861000 0x1000>;
		reg-names = "funnel-base-dummy", "funnel-base-real";

		coresight-name = "coresight-funnel-turing-1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		qcom,duplicate-funnel;

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_turing_1_out_funnel_qatb: endpoint {
					remote-endpoint =
					    <&funnel_qatb_in_funnel_turing_1>;
				};
			};

			port@1 {
				reg = <1>;
				funnel_turing_1_in_turing_etm0: endpoint {
					slave-mode;
					remote-endpoint =
					    <&turing_etm0_out_funnel_turing_1>;
				};
			};
		};
	};

	tpdm_turing: tpdm@6860000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x6860000 0x1000>;
		reg-names = "tpdm-base";

		qcom,msr-fix-req;

		coresight-name = "coresight-tpdm-turing";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_turing_out_funnel_turing: endpoint {
				remote-endpoint =
				    <&funnel_turing_in_tpdm_turing>;
			};
		};
	};

	funnel_ddr_0: funnel@69e2000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x69e2000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-ddr-0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_ddr_0_out_tpda: endpoint {
					remote-endpoint =
					    <&tpda_in_funnel_ddr_0>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_ddr_0_in_tpdm_ddr: endpoint {
					slave-mode;
					remote-endpoint =
					    <&tpdm_ddr_out_funnel_ddr_0>;
				};
			};
		};
	};

	tpdm_ddr: tpdm@69e0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x69e0000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-ddr";

		qcom,msr-fix-req;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_ddr_out_funnel_ddr_0: endpoint {
				remote-endpoint = <&funnel_ddr_0_in_tpdm_ddr>;
			};
		};
	};

	tpdm_pimem: tpdm@6850000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x6850000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-pimem";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			tpdm_pimem_out_tpda: endpoint {
				remote-endpoint = <&tpda_in_tpdm_pimem>;
			};
		};
	};

	tpdm_vsense: tpdm@6840000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x6840000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-vsense";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port{
			tpdm_vsense_out_tpda: endpoint {
				remote-endpoint = <&tpda_in_tpdm_vsense>;
			};
		};
	};

	tpda_olc: tpda@7832000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b969>;
		reg = <0x7832000 0x1000>;
		reg-names = "tpda-base";

		coresight-name = "coresight-tpda-olc";

		qcom,tpda-atid = <69>;
		qcom,cmb-elem-size = <0 64>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
				tpda_olc_out_funnel_apss_merg: endpoint {
					remote-endpoint =
						<&funnel_apss_merg_in_tpda_olc>;
				};
			};
			port@1 {
				reg = <0>;
				tpda_olc_in_tpdm_olc: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpdm_olc_out_tpda_olc>;
				};
			};
		};
	};

	tpdm_olc: tpdm@7830000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b968>;
		reg = <0x7830000 0x1000>;
		reg-names = "tpdm-base";

		coresight-name = "coresight-tpdm-olc";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port{
			tpdm_olc_out_tpda_olc: endpoint {
				remote-endpoint = <&tpda_olc_in_tpdm_olc>;
			};
		};
	};

	funnel_qatb: funnel@6005000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x6005000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-qatb";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_qatb_out_funnel_in0: endpoint {
					remote-endpoint =
						<&funnel_in0_in_funnel_qatb>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_qatb_in_tpda: endpoint {
					slave-mode;
					remote-endpoint =
						<&tpda_out_funnel_qatb>;
				};
			};

			port@2 {
				reg = <7>;
				funnel_qatb_in_funnel_turing_1: endpoint {
					slave-mode;
					remote-endpoint =
					    <&funnel_turing_1_out_funnel_qatb>;
				};
			};
		};
	};

	cti0_ddr0: cti@69e1000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x69e1000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-ddr_dl_0_cti0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti0_ddr1: cti@69e4000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x69e4000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-ddr_dl_1_cti0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti1_ddr1: cti@69e5000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x69e5000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-ddr_dl_1_cti1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti0_dlmm: cti@6c09000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6c09000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-dlmm_cti0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti1_dlmm: cti@6c0a000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6c0a000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-dlmm_cti1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti0_dlct: cti@6c29000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6c29000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-dlct_cti0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti1_dlct: cti@6c2a000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6c2a000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-dlct_cti1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti0_wcss: cti@69a4000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x69a4000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-wcss_cti0";
		status = "disabled";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti1_wcss: cti@69a5000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x69a5000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-wcss_cti1";
		status = "disabled";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti2_wcss: cti@69a6000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x69a6000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-wcss_cti2";
		status = "disabled";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_mss_q6: cti@683b000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x683b000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-mss-q6";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_turing: cti@6867000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6867000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-turing";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti2_ssc_sdc: cti@6b10000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6b10000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-ssc_sdc_cti2";
		status = "disabled";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti1_ssc: cti@6b11000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6b11000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-ssc_cti1";
		status = "disabled";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti0_ssc_q6: cti@6b1b000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6b1b000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-ssc_q6_cti0";
		status = "disabled";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_ssc_noc: cti@6b1e000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6b1e000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-ssc_noc";
		status = "disabled";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti6_ssc_noc: cti@6b1f000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6b1f000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-ssc_noc_cti6";
		status = "disabled";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti0_swao: cti@6b04000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6b04000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-swao_cti0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti1_swao: cti@6b05000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6b05000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-swao_cti1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti2_swao: cti@6b06000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6b06000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-swao_cti2";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti3_swao: cti@6b07000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6b07000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-swao_cti3";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_aop_m3: cti@6b21000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6b21000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-aop-m3";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_titan: cti@6c13000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6c13000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-titan";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_venus_arm9: cti@6c20000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6c20000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-venus-arm9";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti0_apss: cti@78e0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x78e0000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-apss_cti0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti1_apss: cti@78f0000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x78f0000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-apss_cti1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti2_apss: cti@7900000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7900000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-apss_cti2";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti0: cti@6010000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6010000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti1: cti@6011000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6011000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti2: cti@6012000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6012000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti2";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti3: cti@6013000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6013000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti3";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti4: cti@6014000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6014000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti4";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti5: cti@6015000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6015000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti5";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti6: cti@6016000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6016000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti6";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti7: cti@6017000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6017000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti7";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti8: cti@6018000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6018000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti8";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti9: cti@6019000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x6019000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti9";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti10: cti@601a000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601a000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti10";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti11: cti@601b000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601b000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti11";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti12: cti@601c000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601c000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti12";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti13: cti@601d000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601d000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti13";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti14: cti@601e000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601e000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti14";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti15: cti@601f000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x601f000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti15";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti_cpu0: cti@7020000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7020000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu0";
		cpu = <&CPU0>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

	};

	cti_cpu1: cti@7120000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7120000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu1";
		cpu = <&CPU1>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_cpu2: cti@7220000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7220000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu2";
		cpu = <&CPU2>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_cpu3: cti@7320000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7320000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu3";
		cpu = <&CPU3>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_cpu4: cti@7420000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7420000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu4";
		cpu = <&CPU4>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_cpu5: cti@7520000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7520000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu5";
		cpu = <&CPU5>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_cpu6: cti@7620000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7620000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu6";
		cpu = <&CPU6>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	cti_cpu7: cti@7720000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b966>;
		reg = <0x7720000 0x1000>;
		reg-names = "cti-base";

		coresight-name = "coresight-cti-cpu7";
		cpu = <&CPU7>;

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	turing_etm0 {
		compatible = "qcom,coresight-remote-etm";

		coresight-name = "coresight-turing-etm0";
		qcom,inst-id = <13>;

		port{
			turing_etm0_out_funnel_turing_1: endpoint {
				remote-endpoint =
					<&funnel_turing_1_in_turing_etm0>;
			};
		};
	};

	modem_etm0 {
		compatible = "qcom,coresight-remote-etm";

		coresight-name = "coresight-modem-etm0";
		qcom,inst-id = <2>;

		port {
			modem_etm0_out_funnel_in2: endpoint {
				remote-endpoint =
					<&funnel_in2_in_modem_etm0>;
			};
		};
	};

	sensor_etm0 {
		compatible = "qcom,coresight-remote-etm";

		coresight-name = "coresight-sensor-etm0";
		qcom,inst-id = <8>;

		port {
			sensor_etm0_out_funnel_swao: endpoint {
				remote-endpoint =
					<&funnel_swao_in_sensor_etm0>;
			};
		};
	};

	tpdm_lpass: tpdm@6b16000 {
		compatible = "qcom,coresight-dummy";
		coresight-name = "coresight-tpdm-lpass";

		qcom,dummy-source;
		port {
			tpdm_lpass_out_funnel_in1: endpoint {
				remote-endpoint = <&funnel_in1_in_tpdm_lpass>;
			};
		};
	};

	audio_etm0 {
		compatible = "qcom,coresight-remote-etm";

		coresight-name = "coresight-audio-etm0";
		qcom,inst-id = <5>;

		port {
			audio_etm0_out_funnel_in1: endpoint {
				remote-endpoint =
					<&funnel_in1_in_audio_etm0>;
			};
		};
	};

	funnel_apss_merg: funnel@7810000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x7810000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-apss-merg";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_apss_merg_out_funnel_in2: endpoint {
					remote-endpoint =
					    <&funnel_in2_in_funnel_apss_merg>;
				};
			};

			port@1 {
				reg = <0>;
				funnel_apss_merg_in_funnel_apss: endpoint {
					slave-mode;
					remote-endpoint =
					    <&funnel_apss_out_funnel_apss_merg>;
				};
			};

			port@2 {
				reg = <2>;
				funnel_apss_merg_in_tpda_olc: endpoint {
					slave-mode;
					remote-endpoint =
					    <&tpda_olc_out_funnel_apss_merg>;
				};
			};

			port@3 {
				reg = <4>;
				funnel_apss_merg_in_tpda_apss: endpoint {
					slave-mode;
					remote-endpoint =
					    <&tpda_apss_out_funnel_apss_merg>;
				};
			};
			port@4 {
				reg = <5>;
				funnel_apss_merg_in_tpda_llm_silver: endpoint {
					slave-mode;
					remote-endpoint =
					<&tpda_llm_silver_out_funnel_apss_merg>;
				};
			};
			port@5 {
				reg = <6>;
				funnel_apss_merg_in_tpda_llm_gold: endpoint {
					slave-mode;
					remote-endpoint =
					  <&tpda_llm_gold_out_funnel_apss_merg>;
				};
			};
		};
	};

	etm0: etm@7040000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x7040000 0x1000>;
		cpu = <&CPU0>;

		coresight-name = "coresight-etm0";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			etm0_out_funnel_apss: endpoint {
				remote-endpoint = <&funnel_apss_in_etm0>;
			};
		};
	};

	etm1: etm@7140000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x7140000 0x1000>;
		cpu = <&CPU1>;

		coresight-name = "coresight-etm1";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			etm1_out_funnel_apss: endpoint {
				remote-endpoint = <&funnel_apss_in_etm1>;
			};
		};
	};

	etm2: etm@7240000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x7240000 0x1000>;
		cpu = <&CPU2>;

		coresight-name = "coresight-etm2";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			etm2_out_funnel_apss: endpoint {
				remote-endpoint = <&funnel_apss_in_etm2>;
			};
		};
	};

	etm3: etm@7340000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x7340000 0x1000>;
		cpu = <&CPU3>;

		coresight-name = "coresight-etm3";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			etm3_out_funnel_apss: endpoint {
				remote-endpoint = <&funnel_apss_in_etm3>;
			};
		};
	};

	etm4: etm@7440000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x7440000 0x1000>;
		cpu = <&CPU4>;

		coresight-name = "coresight-etm4";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			etm4_out_funnel_apss: endpoint {
				remote-endpoint = <&funnel_apss_in_etm4>;
			};
		};
	};

	etm5: etm@7540000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x7540000 0x1000>;
		cpu = <&CPU5>;

		coresight-name = "coresight-etm5";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			etm5_out_funnel_apss: endpoint {
				remote-endpoint = <&funnel_apss_in_etm5>;
			};
		};
	};

	etm6: etm@7640000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x7640000 0x1000>;
		cpu = <&CPU6>;

		coresight-name = "coresight-etm6";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			etm6_out_funnel_apss: endpoint {
				remote-endpoint = <&funnel_apss_in_etm6>;
			};
		};
	};

	etm7: etm@7740000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x000bb95d>;

		reg = <0x7740000 0x1000>;
		cpu = <&CPU7>;

		coresight-name = "coresight-etm7";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		port {
			etm7_out_funnel_apss: endpoint {
				remote-endpoint = <&funnel_apss_in_etm7>;
			};
		};
	};

	ipcb_tgu: tgu@6b0c000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b999>;
		reg = <0x6b0c000 0x1000>;
		reg-names = "tgu-base";
		tgu-steps = <3>;
		tgu-conditions = <4>;
		tgu-regs = <4>;
		tgu-timer-counters = <8>;

		coresight-name = "coresight-tgu-ipcb";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";
	};

	funnel_apss: funnel@7800000 {
		compatible = "arm,primecell";
		arm,primecell-periphid = <0x0003b908>;

		reg = <0x7800000 0x1000>;
		reg-names = "funnel-base";

		coresight-name = "coresight-funnel-apss";

		clocks = <&clock_aop QDSS_CLK>;
		clock-names = "apb_pclk";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				funnel_apss_out_funnel_apss_merg: endpoint {
					remote-endpoint =
					    <&funnel_apss_merg_in_funnel_apss>;
				};
			};
			port@1 {
				reg = <0>;
				funnel_apss_in_etm0: endpoint {
					slave-mode;
					remote-endpoint =
						<&etm0_out_funnel_apss>;
				};
			};

			port@2 {
				reg = <1>;
				funnel_apss_in_etm1: endpoint {
					slave-mode;
					remote-endpoint =
						<&etm1_out_funnel_apss>;
				};
			};

			port@3 {
				reg = <2>;
				funnel_apss_in_etm2: endpoint {
					slave-mode;
					remote-endpoint =
						<&etm2_out_funnel_apss>;
				};
			};

			port@4 {
				reg = <3>;
				funnel_apss_in_etm3: endpoint {
					slave-mode;
					remote-endpoint =
						<&etm3_out_funnel_apss>;
				};
			};

			port@5 {
				reg = <4>;
				funnel_apss_in_etm4: endpoint {
					slave-mode;
					remote-endpoint =
						<&etm4_out_funnel_apss>;
				};
			};

			port@6 {
				reg = <5>;
				funnel_apss_in_etm5: endpoint {
					slave-mode;
					remote-endpoint =
						<&etm5_out_funnel_apss>;
				};
			};

			port@7 {
				reg = <6>;
				funnel_apss_in_etm6: endpoint {
					slave-mode;
					remote-endpoint =
						<&etm6_out_funnel_apss>;
				};
			};

			port@8 {
				reg = <7>;
				funnel_apss_in_etm7: endpoint {
					slave-mode;
					remote-endpoint =
						<&etm7_out_funnel_apss>;
				};
			};
		};
	};
};