Merge "Revert "usb: phy: Pet EUD based on LDO24 status""
diff --git a/Documentation/devicetree/bindings/usb/msm-phy.txt b/Documentation/devicetree/bindings/usb/msm-phy.txt
index d23cb46..6109fad 100644
--- a/Documentation/devicetree/bindings/usb/msm-phy.txt
+++ b/Documentation/devicetree/bindings/usb/msm-phy.txt
@@ -159,7 +159,6 @@
"efuse_addr": EFUSE address to read and update analog tune parameter.
"emu_phy_base" : phy base address used for programming emulation target phy.
"ref_clk_addr" : ref_clk bcr address used for on/off ref_clk before reset.
- "eud_base" : EUD device register address space to use EUD pet functionality.
- clocks: a list of phandles to the PHY clocks. Use as per
Documentation/devicetree/bindings/clock/clock-bindings.txt
- clock-names: Names of the clocks in 1-1 correspondence with the "clocks"
diff --git a/drivers/usb/phy/phy-msm-qusb-v2.c b/drivers/usb/phy/phy-msm-qusb-v2.c
index b9b604a..6d97dec 100644
--- a/drivers/usb/phy/phy-msm-qusb-v2.c
+++ b/drivers/usb/phy/phy-msm-qusb-v2.c
@@ -63,17 +63,6 @@
#define LINESTATE_DP BIT(0)
#define LINESTATE_DM BIT(1)
-/* eud related registers */
-#define EUD_SW_ATTACH_DET 0x1018
-#define EUD_INT1_EN_MASK 0x0024
-
-/* EUD interrupt mask bits */
-#define EUD_INT_RX BIT(0)
-#define EUD_INT_TX BIT(1)
-#define EUD_INT_VBUS BIT(2)
-#define EUD_INT_CHGR BIT(3)
-#define EUD_INT_SAFE_MODE BIT(4)
-
unsigned int phy_tune1;
module_param(phy_tune1, uint, 0644);
MODULE_PARM_DESC(phy_tune1, "QUSB PHY v2 TUNE1");
@@ -92,7 +81,6 @@
struct usb_phy phy;
struct mutex lock;
void __iomem *base;
- void __iomem *eud_base;
void __iomem *efuse_reg;
struct clk *ref_clk_src;
@@ -667,22 +655,6 @@
return ret;
}
qphy->dpdm_enable = true;
-
- if (qphy->eud_base) {
- if (qphy->cfg_ahb_clk)
- clk_prepare_enable(qphy->cfg_ahb_clk);
- writel_relaxed(BIT(0),
- qphy->eud_base + EUD_SW_ATTACH_DET);
- /* to flush above write before next write */
- wmb();
-
- writel_relaxed(EUD_INT_VBUS | EUD_INT_CHGR,
- qphy->eud_base + EUD_INT1_EN_MASK);
- /* to flush above write before turning off clk */
- wmb();
- if (qphy->cfg_ahb_clk)
- clk_disable_unprepare(qphy->cfg_ahb_clk);
- }
}
return ret;
@@ -697,16 +669,6 @@
__func__, qphy->dpdm_enable);
if (qphy->dpdm_enable) {
- if (qphy->eud_base) {
- if (qphy->cfg_ahb_clk)
- clk_prepare_enable(qphy->cfg_ahb_clk);
- writel_relaxed(0, qphy->eud_base + EUD_SW_ATTACH_DET);
- /* to flush above write before turning off clk */
- wmb();
- if (qphy->cfg_ahb_clk)
- clk_disable_unprepare(qphy->cfg_ahb_clk);
- }
-
ret = qusb_phy_enable_power(qphy, false);
if (ret < 0) {
dev_dbg(qphy->phy.dev,
@@ -813,17 +775,6 @@
}
}
- res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
- "eud_base");
- if (res) {
- qphy->eud_base = devm_ioremap(dev, res->start,
- resource_size(res));
- if (IS_ERR(qphy->eud_base)) {
- dev_dbg(dev, "couldn't ioremap eud_base\n");
- qphy->eud_base = NULL;
- }
- }
-
/* ref_clk_src is needed irrespective of SE_CLK or DIFF_CLK usage */
qphy->ref_clk_src = devm_clk_get(dev, "ref_clk_src");
if (IS_ERR(qphy->ref_clk_src)) {