| Qualcomm Technologies Inc GPI DMA controller |
| |
| QCOM GPI DMA controller provides DMA capabilities for |
| peripheral buses such as I2C, UART, and SPI. |
| |
| ============== |
| Node Structure |
| ============== |
| |
| Main node properties: |
| |
| - #dma-cells |
| Usage: required |
| Value type: <u32> |
| Definition: Number of parameters client will provide. Must be set to 5. |
| 1st parameter: channel index, 0 for TX, 1 for RX |
| 2nd parameter: serial engine index |
| 3rd parameter: bus protocol, 1 for SPI, 2 for UART, 3 for I2C |
| 4th parameter: channel ring length in transfer ring elements |
| 5th parameter: event processing priority, set to 0 for lowest latency |
| |
| - compatible |
| Usage: required |
| Value type: <string> |
| Definition: "qcom,gpi-dma" |
| |
| - reg |
| Usage: required |
| Value type: Array of <u32> |
| Definition: register address space location and size |
| |
| - reg-name |
| Usage: required |
| Value type: <string> |
| Definition: register space name, must be "gpi-top" |
| |
| - interrupts |
| Usage: required |
| Value type: Array of <u32> |
| Definition: Array of tuples which describe interrupt line for each GPII |
| instance. |
| |
| - qcom,max-num-gpii |
| Usage: required |
| Value type: <u32> |
| Definition: Total number of GPII instances available for this controller. |
| |
| - qcom,gpii-mask |
| Usage: required |
| Value type: <u32> |
| Definition: Bitmap of supported GPII instances in hlos. |
| |
| - qcom,ev-factor |
| Usage: required |
| Value type: <u32> |
| Definition: Event ring transfer size compare to channel transfer ring. Event |
| ring length = ev-factor * transfer ring size |
| |
| - iommus |
| Usage: required |
| Value type: <phandle u32 u32> |
| Definition: phandle for apps smmu controller and SID, and mask |
| for the controller. For more detail please check binding |
| documentation arm,smmu.txt |
| |
| - qcom,smmu-cfg |
| Usage: required |
| Value type: <u32> |
| Definition: Determine whether GPI driver require to configure SMMU that |
| sits behind GPI controller. |
| Bit mask: |
| BIT(0) : Attach address mapping to endpoint device |
| BIT(1) : Set SMMU attribute S1_BYPASS |
| BIT(2) : Set SMMU attribute FAST |
| BIT(3) : Set SMMU attribute ATOMIC |
| |
| - qcom,iova-range |
| Usage: required if SMMU S1 translation is enabled |
| Value type: Array of <u64> |
| Definition: Pair of values describing iova base and size to allocate. |
| |
| ======== |
| Example: |
| ======== |
| gpi_dma0: qcom,gpi-dma@0x800000 { |
| #dma-cells = <5>; |
| compatible = "qcom,gpi-dma"; |
| reg = <0x800000 0x60000>; |
| reg-names = "gpi-top"; |
| interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>, |
| <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>, |
| <0 252 0>, <0 253 0>, <0 254 0>, <0 255 0>, |
| <0 256 0>; |
| qcom,max-num-gpii = <13>; |
| qcom,gpii-mask = <0xfa>; |
| qcom,ev-factor = <2>; |
| iommus = <&apps_smmu 0x0016 0x0>; |
| qcom,smmu-cfg = <0x1> |
| qcom,iova-range = <0x0 0x100000 0x0 0x100000>; |
| status = "ok"; |
| }; |