| /* |
| * Copyright (c) 2014-2016,2018, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| &soc { |
| mdss_mdp: qcom,mdss_mdp@1a00000 { |
| compatible = "qcom,mdss_mdp3"; |
| reg = <0x1a00000 0x100000>, |
| <0x1ab0000 0x3000>; |
| reg-names = "mdp_phys", "vbif_phys"; |
| interrupts = <0 72 0>; |
| |
| vdd-supply = <&gdsc_mdss>; |
| clocks = <&clock_gcc clk_gcc_mdss_ahb_clk>, |
| <&clock_gcc clk_gcc_mdss_axi_clk>, |
| <&clock_gcc clk_mdp_clk_src>, |
| <&clock_gcc clk_gcc_mdss_mdp_clk>, |
| <&clock_gcc clk_gcc_mdss_vsync_clk>; |
| clock-names = "iface_clk", "bus_clk", "core_clk_src", |
| "core_clk", "vsync_clk"; |
| |
| qcom,regs-dump-mdp = <0x0300 0x0358>, |
| <0x10000 0x101E0>, |
| <0x20004 0x0020044>, |
| <0x90000 0x90074>; |
| qcom,regs-dump-names-mdp = "MDP_SYNC", |
| "PPP","PPP_FETCH", |
| "DMA_P"; |
| |
| qcom,regs-dump-vbif = <0x0004 0x0010>, |
| <0x0194 0x01b0>, |
| <0x0200 0x020c>; |
| |
| qcom,regs-dump-names-vbif = "VBIF_CLK", |
| "VBIF_ERR","VBIF_XIN_HALT"; |
| |
| mdss_fb0: qcom,mdss_fb_primary { |
| cell-index = <0>; |
| compatible = "qcom,mdss-fb"; |
| qcom,cont-splash-memory { |
| linux,contiguous-region = <&cont_splash_mem>; |
| }; |
| }; |
| |
| smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb { |
| compatible = "qcom,smmu_mdp_unsec"; |
| iommus = <&apps_iommu 0xC00 0>; /* For NS ctx bank */ |
| }; |
| smmu_mdp_sec: qcom,smmu_mdp_sec_cb { |
| compatible = "qcom,smmu_mdp_sec"; |
| iommus = <&apps_iommu 0xC01 0>; /* For SEC Ctx Bank */ |
| }; |
| }; |
| |
| mdss_dsi: qcom,mdss_dsi@0 { |
| compatible = "qcom,mdss-dsi"; |
| hw-config = "single_dsi"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| qcom,mdss-fb-map-prim = <&mdss_fb0>; |
| gdsc-supply = <&gdsc_mdss>; |
| vdda-supply = <&pm660_l2>; |
| vddio-supply = <&pm660_l6>; |
| |
| /* Bus Scale Settings */ |
| qcom,msm-bus,name = "mdss_dsi"; |
| qcom,msm-bus,num-cases = <2>; |
| qcom,msm-bus,num-paths = <1>; |
| qcom,msm-bus,vectors-KBps = |
| <22 512 0 0>, |
| <22 512 0 1000>; |
| |
| ranges = <0x1ac8000 0x1ac8000 0x25c |
| 0x1ac8500 0x1ac8500 0x280 |
| 0x1ac8780 0x1ac8780 0x30 |
| 0x193e000 0x193e000 0x30>; |
| |
| clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>, |
| <&clock_gcc clk_gcc_mdss_ahb_clk>, |
| <&clock_gcc clk_gcc_mdss_axi_clk>; |
| clock-names = "mdp_core_clk", "iface_clk", "bus_clk"; |
| |
| qcom,mmss-ulp-clamp-ctrl-offset = <0x20>; |
| qcom,mmss-phyreset-ctrl-offset = <0x24>; |
| |
| qcom,core-supply-entries { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,core-supply-entry@0 { |
| reg = <0>; |
| qcom,supply-name = "gdsc"; |
| qcom,supply-min-voltage = <0>; |
| qcom,supply-max-voltage = <0>; |
| qcom,supply-enable-load = <0>; |
| qcom,supply-disable-load = <0>; |
| }; |
| }; |
| |
| qcom,ctrl-supply-entries { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,ctrl-supply-entry@0 { |
| reg = <0>; |
| qcom,supply-name = "vdda"; |
| qcom,supply-min-voltage = <1200000>; |
| qcom,supply-max-voltage = <1200000>; |
| qcom,supply-enable-load = <100000>; |
| qcom,supply-disable-load = <100>; |
| qcom,supply-post-on-sleep = <5>; |
| }; |
| }; |
| |
| qcom,phy-supply-entries { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,phy-supply-entry@0 { |
| reg = <0>; |
| qcom,supply-name = "vddio"; |
| qcom,supply-min-voltage = <1800000>; |
| qcom,supply-max-voltage = <1800000>; |
| qcom,supply-enable-load = <100000>; |
| qcom,supply-disable-load = <100>; |
| }; |
| }; |
| |
| mdss_dsi0: qcom,mdss_dsi_ctrl0@1ac8000 { |
| compatible = "qcom,mdss-dsi-ctrl"; |
| label = "MDSS DSI CTRL->0"; |
| cell-index = <0>; |
| reg = <0x1ac8000 0x25c>, |
| <0x1ac8500 0x280>, |
| <0x1ac8780 0x30>, |
| <0x193e000 0x30>; |
| reg-names = "dsi_ctrl", "dsi_phy", |
| "dsi_phy_regulator", "mmss_misc_phys"; |
| |
| qcom,dsi-irq-line; |
| interrupts = <0 80 0>; |
| |
| qcom,mdss-mdp = <&mdss_mdp>; |
| vdd-supply = <&pm660_l17>; |
| vddio-supply = <&pm660_l6>; |
| |
| clocks = <&clock_gcc_mdss clk_gcc_mdss_byte0_clk>, |
| <&clock_gcc_mdss clk_gcc_mdss_pclk0_clk>, |
| <&clock_gcc clk_gcc_mdss_esc0_clk>; |
| clock-names = "byte_clk", "pixel_clk", "core_clk"; |
| |
| qcom,regulator-ldo-mode; |
| |
| qcom,platform-strength-ctrl = [ff 06]; |
| qcom,platform-bist-ctrl = [00 00 b1 ff 00 00]; |
| qcom,platform-regulator-settings = |
| [00 01 01 00 20 07 00]; |
| qcom,platform-lane-config = |
| [00 00 00 00 00 00 00 01 97 |
| 00 00 00 00 05 00 00 01 97 |
| 00 00 00 00 0a 00 00 01 97 |
| 00 00 00 00 0f 00 00 01 97 |
| 00 c0 00 00 00 00 00 01 bb]; |
| }; |
| }; |
| }; |
| |
| #include "msm8909-mdss-panels.dtsi" |