| commit | e7ada8dfd564d9fa518432a513994cc53e358fad | [log] [tgz] |
|---|---|---|
| author | Arnd Bergmann <arnd@arndb.de> | Fri Feb 26 22:54:53 2016 +0100 |
| committer | Arnd Bergmann <arnd@arndb.de> | Fri Feb 26 22:54:53 2016 +0100 |
| tree | d287940ed960d538f76f51432f53da7e4b9dc36f | |
| parent | 8bba98a8c1527f1cc121776cf5fac97ac2d3089c [diff] | |
| parent | 8fff2f752f2c9d31414f83170157701b59aec4c1 [diff] |
Merge tag 'zynq-soc-for-4.6' of https://github.com/Xilinx/linux-xlnx into next/soc Merge "ARM: Xilinx Zynq patches for v4.6" from Michal Simek: - SLCR early init - Fix L2 cache data corruption - Fix early printk uart setting * tag 'zynq-soc-for-4.6' of https://github.com/Xilinx/linux-xlnx: ARM: zynq: Move early printk virtual address to vmalloc area ARM: zynq: address L2 cache data corruption ARM: zynq: initialize slcr mapping earlier