| /* |
| * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 and |
| * only version 2 as published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include "sda670.dtsi" |
| |
| / { |
| model = "Qualcomm Technologies, Inc. QCS605"; |
| qcom,msm-id = <347 0x0>; |
| }; |
| |
| &pil_modem_mem { |
| reg = <0 0x8b000000 0 0x3100000>; |
| }; |
| |
| &pil_video_mem { |
| reg = <0 0x8e100000 0 0x500000>; |
| }; |
| |
| &wlan_msa_mem { |
| reg = <0 0x8e600000 0 0x100000>; |
| }; |
| |
| &pil_cdsp_mem { |
| reg = <0 0x8e700000 0 0x800000>; |
| }; |
| |
| &pil_mba_mem { |
| reg = <0 0x8ef00000 0 0x200000>; |
| }; |
| |
| &pil_adsp_mem { |
| reg = <0 0x8f100000 0 0x1e00000>; |
| }; |
| |
| &pil_ipa_fw_mem { |
| reg = <0 0x90f00000 0 0x10000>; |
| }; |
| |
| &pil_ipa_gsi_mem { |
| reg = <0 0x90f10000 0 0x5000>; |
| }; |
| |
| &pil_gpu_mem { |
| reg = <0 0x90f15000 0 0x2000>; |
| }; |
| |
| &adsp_mem { |
| size = <0 0x800000>; |
| }; |
| |
| &secure_display_memory { |
| status = "disabled"; |
| }; |
| |
| &qcom_seecom { |
| reg = <0x86d00000 0x800000>; |
| }; |
| |
| &sp_mem { |
| status = "disabled"; |
| }; |
| |
| &dump_mem { |
| size = <0 0x800000>; |
| }; |
| |
| &soc { |
| qcom,rmnet-ipa { |
| status = "disabled"; |
| }; |
| }; |
| |
| &llcc { |
| compatible = "qcom,qcs605-llcc"; |
| }; |
| |
| &ipa_hw { |
| status = "disabled"; |
| }; |
| |
| &mem_dump { |
| rpmh { |
| qcom,dump-size = <0x400000>; |
| }; |
| }; |
| |
| &thermal_zones { |
| lmh-dcvs-00 { |
| trips { |
| active-config { |
| temperature = <100000>; |
| hysteresis = <35000>; |
| }; |
| }; |
| }; |
| |
| lmh-dcvs-01 { |
| trips { |
| active-config { |
| temperature = <100000>; |
| hysteresis = <35000>; |
| }; |
| }; |
| }; |
| |
| gpu-virt-max-step { |
| trips { |
| gpu-trip0 { |
| temperature = <100000>; |
| }; |
| }; |
| }; |
| }; |
| |
| &msm_gpu { |
| /delete-node/qcom,gpu-mempools; |
| /delete-node/qcom,gpu-pwrlevel-bins; |
| |
| qcom,gpu-pwrlevel-bins { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| compatible="qcom,gpu-pwrlevel-bins"; |
| |
| qcom,gpu-pwrlevels-0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <0>; |
| |
| qcom,initial-pwrlevel = <4>; |
| qcom,ca-target-pwrlevel = <5>; |
| |
| /* TURBO_L1 */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <780000000>; |
| qcom,bus-freq = <11>; |
| qcom,bus-min = <10>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* TURBO */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <750000000>; |
| qcom,bus-freq = <11>; |
| qcom,bus-min = <9>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* NOM_L1 */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <650000000>; |
| qcom,bus-freq = <10>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* NOM */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <565000000>; |
| qcom,bus-freq = <9>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <10>; |
| }; |
| |
| /* SVS_L1 */ |
| qcom,gpu-pwrlevel@4 { |
| reg = <4>; |
| qcom,gpu-freq = <430000000>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <7>; |
| qcom,bus-max = <10>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@5 { |
| reg = <5>; |
| qcom,gpu-freq = <355000000>; |
| qcom,bus-freq = <7>; |
| qcom,bus-min = <5>; |
| qcom,bus-max = <8>; |
| }; |
| |
| /* LOW SVS */ |
| qcom,gpu-pwrlevel@6 { |
| reg = <6>; |
| qcom,gpu-freq = <267000000>; |
| qcom,bus-freq = <6>; |
| qcom,bus-min = <4>; |
| qcom,bus-max = <7>; |
| }; |
| |
| /* MIN SVS */ |
| qcom,gpu-pwrlevel@7 { |
| reg = <7>; |
| qcom,gpu-freq = <180000000>; |
| qcom,bus-freq = <4>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <4>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@8 { |
| reg = <8>; |
| qcom,gpu-freq = <0>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <146>; |
| |
| qcom,initial-pwrlevel = <3>; |
| qcom,ca-target-pwrlevel = <4>; |
| |
| /* TURBO */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <700000000>; |
| qcom,bus-freq = <11>; |
| qcom,bus-min = <9>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* NOM_L1 */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <650000000>; |
| qcom,bus-freq = <10>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* NOM */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <565000000>; |
| qcom,bus-freq = <9>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <10>; |
| }; |
| |
| /* SVS_L1 */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <430000000>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <7>; |
| qcom,bus-max = <10>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@4 { |
| reg = <4>; |
| qcom,gpu-freq = <355000000>; |
| qcom,bus-freq = <7>; |
| qcom,bus-min = <5>; |
| qcom,bus-max = <8>; |
| }; |
| |
| /* LOW SVS */ |
| qcom,gpu-pwrlevel@5 { |
| reg = <5>; |
| qcom,gpu-freq = <267000000>; |
| qcom,bus-freq = <6>; |
| qcom,bus-min = <4>; |
| qcom,bus-max = <7>; |
| }; |
| |
| /* MIN SVS */ |
| qcom,gpu-pwrlevel@6 { |
| reg = <6>; |
| qcom,gpu-freq = <180000000>; |
| qcom,bus-freq = <4>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <4>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@7 { |
| reg = <7>; |
| qcom,gpu-freq = <0>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| |
| qcom,gpu-pwrlevels-2 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| qcom,speed-bin = <163>; |
| |
| qcom,initial-pwrlevel = <4>; |
| qcom,ca-target-pwrlevel = <5>; |
| |
| /* TURBO_L1 */ |
| qcom,gpu-pwrlevel@0 { |
| reg = <0>; |
| qcom,gpu-freq = <780000000>; |
| qcom,bus-freq = <11>; |
| qcom,bus-min = <10>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* TURBO */ |
| qcom,gpu-pwrlevel@1 { |
| reg = <1>; |
| qcom,gpu-freq = <750000000>; |
| qcom,bus-freq = <11>; |
| qcom,bus-min = <9>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* NOM_L1 */ |
| qcom,gpu-pwrlevel@2 { |
| reg = <2>; |
| qcom,gpu-freq = <650000000>; |
| qcom,bus-freq = <10>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <11>; |
| }; |
| |
| /* NOM */ |
| qcom,gpu-pwrlevel@3 { |
| reg = <3>; |
| qcom,gpu-freq = <565000000>; |
| qcom,bus-freq = <9>; |
| qcom,bus-min = <8>; |
| qcom,bus-max = <10>; |
| }; |
| |
| /* SVS_L1 */ |
| qcom,gpu-pwrlevel@4 { |
| reg = <4>; |
| qcom,gpu-freq = <430000000>; |
| qcom,bus-freq = <8>; |
| qcom,bus-min = <7>; |
| qcom,bus-max = <10>; |
| }; |
| |
| /* SVS */ |
| qcom,gpu-pwrlevel@5 { |
| reg = <5>; |
| qcom,gpu-freq = <355000000>; |
| qcom,bus-freq = <7>; |
| qcom,bus-min = <5>; |
| qcom,bus-max = <8>; |
| }; |
| |
| /* LOW SVS */ |
| qcom,gpu-pwrlevel@6 { |
| reg = <6>; |
| qcom,gpu-freq = <267000000>; |
| qcom,bus-freq = <6>; |
| qcom,bus-min = <4>; |
| qcom,bus-max = <7>; |
| }; |
| |
| /* MIN SVS */ |
| qcom,gpu-pwrlevel@7 { |
| reg = <7>; |
| qcom,gpu-freq = <180000000>; |
| qcom,bus-freq = <4>; |
| qcom,bus-min = <3>; |
| qcom,bus-max = <4>; |
| }; |
| |
| /* XO */ |
| qcom,gpu-pwrlevel@8 { |
| reg = <8>; |
| qcom,gpu-freq = <0>; |
| qcom,bus-freq = <0>; |
| qcom,bus-min = <0>; |
| qcom,bus-max = <0>; |
| }; |
| }; |
| }; |
| }; |