blob: 7d968c2e79f1b23f1d958b31d05441a3fbd6e471 [file] [log] [blame]
/* Copyright (c) 2014-2020, The Linux Foundation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 and
* only version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include "skeleton64.dtsi"
#include <dt-bindings/clock/msm-clocks-8909.h>
#include <dt-bindings/clock/msm-clocks-a7.h>
/ {
model = "Qualcomm Technologies, Inc. MSM8909";
compatible = "qcom,msm8909";
qcom,msm-id = <245 0>,
<258 0>,
<265 0>,
<275 0>;
interrupt-parent = <&wakegic>;
aliases {
/* smdtty devices */
smd1 = &smdtty_apps_fm;
smd2 = &smdtty_apps_riva_bt_acl;
smd3 = &smdtty_apps_riva_bt_cmd;
smd5 = &smdtty_apps_riva_ant_cmd;
smd6 = &smdtty_apps_riva_ant_data;
smd7 = &smdtty_data1;
smd8 = &smdtty_data4;
smd11 = &smdtty_data11;
smd21 = &smdtty_data21;
smd36 = &smdtty_loopback;
sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
sdhc2 = &sdhc_2; /* SDC2 SD card slot */
spi0 = &spi_0; /* SPI0 controller device */
spi2 = &spi_2;
spi4 = &spi_4;
spi5 = &spi_5;
i2c5 = &i2c_5; /* I2c5 cntroller device */
i2c3 = &i2c_3; /* I2C3 controller */
i2c1 = &i2c_1; /* I2C1 controller */
i2c2 = &i2c_2; /* I2C2 NFC qup2 device */
i2c4 = &i2c_4; /* I2C4 controller device */
qpic_nand1 = &qnand_1; /* qpic nand controller */
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
};
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x0>;
efficiency = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
qcom,sleep-status = <&cpu0_slp_sts>;
#cooling-cells = <2>;
};
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x1>;
efficiency = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
qcom,sleep-status = <&cpu1_slp_sts>;
#cooling-cells = <2>;
};
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x2>;
efficiency = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
qcom,sleep-status = <&cpu2_slp_sts>;
#cooling-cells = <2>;
};
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x3>;
efficiency = <1024>;
sched-energy-costs = <&CPU_COST_0 &CLUSTER_COST_0>;
qcom,sleep-status = <&cpu3_slp_sts>;
#cooling-cells = <2>;
};
};
energy_costs: energy-costs {
compatible = "sched-energy";
CPU_COST_0: core-cost0 {
busy-cost-data = <
400000 82
800000 164
1094400 290
>;
idle-cost-data = <
40 20 12 8
>;
};
CLUSTER_COST_0: cluster-cost0 {
busy-cost-data = <
400000 23
800000 48
1094400 87
>;
idle-cost-data = <
4 3 2 1
>;
};
};
firmware: firmware {
android {
compatible = "android,firmware";
fstab {
compatible = "android,fstab";
vendor_fstab: vendor {
compatible = "android,vendor";
dev =
"/dev/block/platform/soc/7824900.sdhci/by-name/vendor";
type = "ext4";
mnt_flags = "ro,barrier=1,discard";
fsmgr_flags = "wait";
status = "ok";
};
system_fstab: system {
compatible = "android,system";
dev =
"/dev/block/platform/soc/7824900.sdhci/by-name/system";
type = "ext4";
mnt_flags = "ro,barrier=1,discard";
fsmgr_flags = "wait,verify";
status = "ok";
};
};
};
};
reserved_mem: reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
external_image_mem: external_image__region@0 {
reg = <0x0 0x87a00000 0x0 0x0600000>;
compatible = "removed-dma-pool";
no-map;
};
modem_adsp_mem: modem_adsp_region@0 {
reg = <0x0 0x88000000 0x0 0x05500000>;
compatible = "removed-dma-pool";
no-map;
};
peripheral_mem: pheripheral_region@0 {
reg = <0x0 0x8d500000 0x0 0x0700000>;
compatible = "removed-dma-pool";
no-map;
};
venus_qseecom_mem: venus_qseecom_region@0 {
compatible = "shared-dma-pool";
reusable;
alloc-ranges = <0x0 0x80000000 0x0 0x10000000>;
alignment = <0 0x400000>;
size = <0 0x0800000>;
};
qseecom_ta_mem: qseecom_ta_region {
compatible = "shared-dma-pool";
alloc-ranges = <0 0x00000000 0 0xffffffff>;
reusable;
alignment = <0 0x400000>;
size = <0 0x400000>;
};
audio_mem: audio_region@0 {
compatible = "shared-dma-pool";
reusable;
alignment = <0 0x400000>;
size = <0 0x400000>;
};
adsp_mem: adsp_region@0 {
compatible = "shared-dma-pool";
reusable;
alignment = <0 0x400000>;
size = <0 0x400000>;
};
cont_splash_mem: splash_region@83000000 {
reg = <0x0 0x83000000 0x0 0xc00000>;
};
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
reusable;
size = <0 0x100000>;
};
};
soc: soc { };
};
#include "msm8909-ion.dtsi"
#include "msm8909-smp2p.dtsi"
#include "msm8909-ipcrouter.dtsi"
#include "msm-gdsc-8916.dtsi"
#include "msm-arm-smmu-8909.dtsi"
#include "msm8909-gpu.dtsi"
#include "msm8909-coresight.dtsi"
#include "msm8909-bus.dtsi"
#include "msm8909-vidc.dtsi"
#include "msm8909-mdss.dtsi"
#include "msm8909-mdss-pll.dtsi"
#include "msm8909-camera.dtsi"
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
intc: interrupt-controller@b000000 {
compatible = "qcom,msm-qgic2";
interrupt-controller;
interrupt-parent = <&intc>;
#interrupt-cells = <3>;
reg = <0x0b000000 0x1000>,
<0x0b002000 0x1000>;
};
wakegic: wake-gic@601d0 {
compatible = "qcom,mpm-gic-msm8909", "qcom,mpm-gic";
interrupts = <GIC_SPI 171 IRQ_TYPE_EDGE_RISING>;
reg = <0x601d0 0x1000>,
<0xb011008 0x4>; /* MSM_APCS_GCC_BASE 4K */
reg-names = "vmpm", "ipc";
interrupt-controller;
interrupt-parent = <&intc>;
#interrupt-cells = <3>;
};
wakegpio: wake-gpio {
compatible = "qcom,mpm-gpio-msm8909", "qcom,mpm-gpio";
interrupt-controller;
interrupt-parent = <&intc>;
#interrupt-cells = <2>;
};
restart@4ab000 {
compatible = "qcom,pshold";
reg = <0x4ab000 0x4>,
<0x193d100 0x4>;
reg-names = "pshold-base", "tcsr-boot-misc-detect";
};
timer {
compatible = "arm,armv7-timer";
interrupts = <1 2 0xf08>,
<1 3 0xf08>,
<1 4 0xf08>,
<1 1 0xf08>;
clock-frequency = <19200000>;
};
timer@b020000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0xb020000 0x1000>;
clock-frequency = <19200000>;
frame@b021000 {
frame-number = <0>;
interrupts = <0 8 0x4>,
<0 7 0x4>;
reg = <0xb021000 0x1000>,
<0xb022000 0x1000>;
};
frame@b023000 {
frame-number = <1>;
interrupts = <0 9 0x4>;
reg = <0xb023000 0x1000>;
status = "disabled";
};
frame@b024000 {
frame-number = <2>;
interrupts = <0 10 0x4>;
reg = <0xb024000 0x1000>;
status = "disabled";
};
frame@b025000 {
frame-number = <3>;
interrupts = <0 11 0x4>;
reg = <0xb025000 0x1000>;
status = "disabled";
};
frame@b026000 {
frame-number = <4>;
interrupts = <0 12 0x4>;
reg = <0xb026000 0x1000>;
status = "disabled";
};
frame@b027000 {
frame-number = <5>;
interrupts = <0 13 0x4>;
reg = <0xb027000 0x1000>;
status = "disabled";
};
frame@b028000 {
frame-number = <6>;
interrupts = <0 14 0x4>;
reg = <0xb028000 0x1000>;
status = "disabled";
};
};
clock_rpm: qcom,rpmcc@1800000 {
compatible = "qcom,rpmcc-8909";
reg = <0x1800000 0x80000>;
reg-names = "cc_base";
#clock-cells = <1>;
};
clock_gcc: qcom,gcc@1800000 {
compatible = "qcom,gcc-8909";
reg = <0x1800000 0x80000>,
<0xb016000 0x00040>;
reg-names = "cc_base", "apcs_base";
qcom,gfx3d_clk_src-opp-store-vcorner = <&msm_gpu>;
vdd_dig-supply = <&pm8909_s1_corner>;
vdd_sr2_dig-supply = <&pm8909_s1_corner_ao>;
vdd_sr2_pll-supply = <&pm8909_l7_ao>;
clocks = <&clock_rpm clk_xo_clk_src>,
<&clock_rpm clk_xo_a_clk_src>;
clock-names = "xo", "xo_a";
#clock-cells = <1>;
#reset-cells = <1>;
};
clock_gcc_mdss: qcom,gcc-mdss@1ac8300 {
compatible = "qcom,gcc-mdss-8909";
clocks = <&mdss_dsi0_pll clk_dsi_pll0_pixel_clk_src>,
<&mdss_dsi0_pll clk_dsi_pll0_byte_clk_src>;
clock-names = "pclk0_src", "byte0_src";
#clock-cells = <1>;
};
clock_debug: qcom,cc-debug@1874000 {
compatible = "qcom,cc-debug-8909";
reg = <0x1874000 0x4>,
<0xb01101c 0x8>;
reg-names = "cc_base", "meas";
clocks = <&clock_rpm clk_rpm_debug_mux>;
clock-names = "rpm_debug_mux";
#clock-cells = <1>;
};
clock_cpu: qcom,clock-a7@0b011050 {
compatible = "qcom,clock-a53-8916";
reg = <0x0b011050 0x8>,
<0x0005c00c 0x8>;
reg-names = "rcg-base", "efuse";
qcom,safe-freq = < 400000000 >;
cpu-vdd-supply = <&pm8909_s1_corner_ao>;
qcom,enable-opp;
clocks = <&clock_gcc clk_gpll0_ao_clk_src>,
<&clock_gcc clk_a7sspll>;
clock-names = "clk-4", "clk-5";
qcom,speed0-bin-v0 =
< 0 0>,
< 400000000 4>,
< 800000000 5>,
< 1267200000 7>;
qcom,speed2-bin-v0 =
< 0 0>,
< 400000000 4>,
< 800000000 5>,
< 1094400000 7>;
#clock-cells = <1>;
};
cpubw: qcom,cpubw {
compatible = "qcom,devbw";
governor = "cpufreq";
qcom,src-dst-ports = <1 512>;
qcom,active-only;
qcom,bw-tbl =
< 762 /* 100 MHz */>,
< 1525 /* 200 MHz */>,
< 3051 /* 400 MHz */>,
< 4066 /* 533 MHz */>;
};
devfreq-cpufreq {
cpubw-cpufreq {
target-dev = <&cpubw>;
cpu-to-dev-map =
< 400000 762>,
< 800000 1525>,
< 998400 3051>,
< 1094400 4066>;
};
};
qcom,cpu-bwmon {
compatible = "qcom,bimc-bwmon2";
reg = <0x408000 0x300>, <0x401000 0x200>;
reg-names = "base", "global_base";
interrupts = <0 183 4>;
qcom,mport = <0>;
qcom,target-dev = <&cpubw>;
};
qcom,msm-cpufreq {
reg = <0 4>;
compatible = "qcom,msm-cpufreq";
clocks = <&clock_cpu clk_a7ssmux>,
<&clock_cpu clk_a7ssmux>,
<&clock_cpu clk_a7ssmux>,
<&clock_cpu clk_a7ssmux>;
clock-names = "cpu0_clk", "cpu1_clk",
"cpu2_clk", "cpu3_clk";
qcom,cpufreq-table =
< 200000 >,
< 400000 >,
< 533330 >,
< 800000 >,
< 998400 >,
< 1094400 >,
< 1190400 >,
< 1248000 >,
< 1267200 >;
};
blsp1_uart1: serial@78af000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uart";
reg = <0x78af000 0x200>;
interrupts = <0 107 0>;
status = "disabled";
clocks = <&clock_gcc clk_gcc_blsp1_uart1_apps_clk>,
<&clock_gcc clk_gcc_blsp1_ahb_clk>;
clock-names = "core", "iface";
};
blsp1_uart2: serial@78b0000 {
compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uart";
reg = <0x78b0000 0x200>;
interrupts = <0 108 0>;
status = "disabled";
clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
<&clock_gcc clk_gcc_blsp1_ahb_clk>;
clock-names = "core", "iface";
};
blsp1_uart2_hs: uart@78b0000 { /*BLSP1 UART2*/
compatible = "qcom,msm-hsuart-v14";
reg = <0x78b0000 0x200>,
<0x7884000 0x1f000>;
reg-names = "core_mem", "bam_mem";
interrupt-names = "core_irq", "bam_irq", "wakeup_irq";
#address-cells = <0>;
interrupt-parent = <&blsp1_uart2_hs>;
interrupts = <0 1 2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xffffffff>;
interrupt-map = <0 &intc 0 108 0
1 &intc 0 238 0
2 &msm_gpio 21 0>;
qcom,inject-rx-on-wakeup;
qcom,rx-char-to-inject = <0xfd>;
qcom,master-id = <86>;
clock-names = "core_clk", "iface_clk";
clocks = <&clock_gcc clk_gcc_blsp1_uart2_apps_clk>,
<&clock_gcc clk_gcc_blsp1_ahb_clk>;
pinctrl-names = "sleep", "default";
pinctrl-0 = <&blsp1_uart2_tx_sleep>, <&blsp1_uart2_rxcts_sleep>,
<&blsp1_uart2_rfr_sleep>;
pinctrl-1 = <&blsp1_uart2_tx_active>,
<&blsp1_uart2_rxcts_active>, <&blsp1_uart2_rfr_active>;
qcom,bam-tx-ep-pipe-index = <2>;
qcom,bam-rx-ep-pipe-index = <3>;
qcom,msm-bus,name = "blsp1_uart2_hs";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<86 512 0 0>,
<86 512 500 800>;
status = "disabled";
};
qcom,sps {
compatible = "qcom,msm_sps_4k";
qcom,device-type = <3>;
qcom,pipe-attr-ee;
};
thermal_zones: thermal-zones {};
mem_dump {
compatible = "qcom,mem-dump";
memory-region = <&dump_mem>;
rpm_sw_dump {
qcom,dump-size = <0x28000>;
qcom,dump-id = <0xea>;
};
pmic_dump {
qcom,dump-size = <0x10000>;
qcom,dump-id = <0xe4>;
};
vsense_dump {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0xe9>;
};
tmc_etf_dump {
qcom,dump-size = <0x10000>;
qcom,dump-id = <0xf0>;
};
tmc_etr_reg_dump {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x100>;
};
tmc_etf_reg_dump {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0x101>;
};
misc_data_dump {
qcom,dump-size = <0x1000>;
qcom,dump-id = <0xe8>;
};
};
tsens0: tsens@4a8000 {
compatible = "qcom,msm8909-tsens";
reg = <0x4a8000 0x1000>,
<0x4a9000 0x1000>,
<0x5c000 0x1000>;
reg-names = "tsens_srot_physical",
"tsens_tm_physical", "tsens_eeprom_physical";
interrupts = <0 184 0>;
interrupt-names = "tsens-upper-lower";
#thermal-sensor-cells = <1>;
};
qcom,ipc-spinlock@1905000 {
compatible = "qcom,ipc-spinlock-sfpb";
reg = <0x1905000 0x8000>;
qcom,num-locks = <8>;
};
qcom,smem@87d00000 {
compatible = "qcom,smem";
reg = <0x87d00000 0x100000>,
<0x0b011008 0x4>,
<0x60000 0x8000>,
<0x193D000 0x8>;
reg-names = "smem", "irq-reg-base",
"aux-mem1", "smem_targ_info_reg";
qcom,mpu-enabled;
qcom,smd-modem {
compatible = "qcom,smd";
qcom,smd-edge = <0>;
qcom,smd-irq-offset = <0x0>;
qcom,smd-irq-bitmask = <0x1000>;
interrupts = <0 25 1>;
label = "modem";
qcom,not-loadable;
};
qcom,smsm-modem {
compatible = "qcom,smsm";
qcom,smsm-edge = <0>;
qcom,smsm-irq-offset = <0x0>;
qcom,smsm-irq-bitmask = <0x2000>;
interrupts = <0 26 1>;
};
qcom,smd-wcnss {
compatible = "qcom,smd";
qcom,smd-edge = <6>;
qcom,smd-irq-offset = <0x0>;
qcom,smd-irq-bitmask = <0x20000>;
interrupts = <0 142 1>;
label = "wcnss";
};
qcom,smsm-wcnss {
compatible = "qcom,smsm";
qcom,smsm-edge = <6>;
qcom,smsm-irq-offset = <0x0>;
qcom,smsm-irq-bitmask = <0x80000>;
interrupts = <0 144 1>;
};
qcom,smd-rpm {
compatible = "qcom,smd";
qcom,smd-edge = <15>;
qcom,smd-irq-offset = <0x0>;
qcom,smd-irq-bitmask = <0x1>;
interrupts = <0 168 1>;
label = "rpm";
qcom,irq-no-suspend;
qcom,not-loadable;
};
};
rpm_bus: qcom,rpm-smd {
compatible = "qcom,rpm-smd";
rpm-channel-name = "rpm_requests";
rpm-channel-type = <15>; /* SMD_APPS_RPM */
};
qcom,bam_dmux@4044000 {
compatible = "qcom,bam_dmux";
reg = <0x4044000 0x19000>;
interrupts = <0 29 1>;
qcom,rx-ring-size = <32>;
qcom,max-rx-mtu = <4096>;
qcom,fast-shutdown;
qcom,no-cpu-affinity;
};
qcom,smdtty {
compatible = "qcom,smdtty";
smdtty_apps_fm: qcom,smdtty-apps-fm {
qcom,smdtty-remote = "wcnss";
qcom,smdtty-port-name = "APPS_FM";
};
smdtty_apps_riva_bt_acl: smdtty-apps-riva-bt-acl {
qcom,smdtty-remote = "wcnss";
qcom,smdtty-port-name = "APPS_RIVA_BT_ACL";
};
smdtty_apps_riva_bt_cmd: qcom,smdtty-apps-riva-bt-cmd {
qcom,smdtty-remote = "wcnss";
qcom,smdtty-port-name = "APPS_RIVA_BT_CMD";
};
smdtty_apps_riva_ant_cmd: smdtty-apps-riva-ant-cmd {
qcom,smdtty-remote = "wcnss";
qcom,smdtty-port-name = "APPS_RIVA_ANT_CMD";
};
smdtty_apps_riva_ant_data: smdtty-apps-riva-ant-data {
qcom,smdtty-remote = "wcnss";
qcom,smdtty-port-name = "APPS_RIVA_ANT_DATA";
};
smdtty_data1: qcom,smdtty-data1 {
qcom,smdtty-remote = "modem";
qcom,smdtty-port-name = "DATA1";
};
smdtty_data4: qcom,smdtty-data4 {
qcom,smdtty-remote = "modem";
qcom,smdtty-port-name = "DATA4";
};
smdtty_data11: qcom,smdtty-data11 {
qcom,smdtty-remote = "modem";
qcom,smdtty-port-name = "DATA11";
};
smdtty_data21: qcom,smdtty-data21 {
qcom,smdtty-remote = "modem";
qcom,smdtty-port-name = "DATA21";
};
smdtty_loopback: smdtty-loopback {
qcom,smdtty-remote = "modem";
qcom,smdtty-port-name = "LOOPBACK";
qcom,smdtty-dev-name = "LOOPBACK_TTY";
};
};
qcom,smdpkt {
compatible = "qcom,smdpkt";
qcom,smdpkt-data5-cntl {
qcom,smdpkt-remote = "modem";
qcom,smdpkt-port-name = "DATA5_CNTL";
qcom,smdpkt-dev-name = "smdcntl0";
};
qcom,smdpkt-data22 {
qcom,smdpkt-remote = "modem";
qcom,smdpkt-port-name = "DATA22";
qcom,smdpkt-dev-name = "smd22";
};
qcom,smdpkt-data40-cntl {
qcom,smdpkt-remote = "modem";
qcom,smdpkt-port-name = "DATA40_CNTL";
qcom,smdpkt-dev-name = "smdcntl8";
};
qcom,smdpkt-data2 {
qcom,smdpkt-remote = "modem";
qcom,smdpkt-port-name = "DATA2";
qcom,smdpkt-dev-name = "at_mdm0";
};
qcom,smdpkt-apr-apps2 {
qcom,smdpkt-remote = "modem";
qcom,smdpkt-port-name = "apr_apps2";
qcom,smdpkt-dev-name = "apr_apps2";
};
qcom,smdpkt-loopback {
qcom,smdpkt-remote = "modem";
qcom,smdpkt-port-name = "LOOPBACK";
qcom,smdpkt-dev-name = "smd_pkt_loopback";
};
};
qcom,iris-fm {
compatible = "qcom,iris_fm";
};
wcnss: qcom,wcnss-wlan@a000000 {
compatible = "qcom,wcnss_wlan";
reg = <0x0a000000 0x280000>,
<0xb011008 0x04>,
<0x0a21b000 0x3000>,
<0x03204000 0x00000100>,
<0x03200800 0x00000200>,
<0x0A100400 0x00000200>,
<0x0A205050 0x00000200>,
<0x0A219000 0x00000020>,
<0x0A080488 0x00000008>,
<0x0A080fb0 0x00000008>,
<0x0A08040c 0x00000008>,
<0x0A0120a8 0x00000008>,
<0x0A012448 0x00000008>,
<0x0A080c00 0x00000001>,
<0x0005E000 0x00000064>;
reg-names = "wcnss_mmio", "wcnss_fiq",
"pronto_phy_base", "riva_phy_base",
"riva_ccu_base", "pronto_a2xb_base",
"pronto_ccpu_base", "pronto_saw2_base",
"wlan_tx_phy_aborts","wlan_brdg_err_source",
"wlan_tx_status", "alarms_txctl",
"alarms_tactl", "pronto_mcu_base",
"pronto_qfuse";
interrupts = <0 145 0 0 146 0>;
interrupt-names = "wcnss_wlantx_irq", "wcnss_wlanrx_irq";
qcom,pronto-vddmx-supply = <&pm8909_l3_corner_ao>;
qcom,pronto-vddcx-supply = <&pm8909_s1_corner>;
qcom,pronto-vddpx-supply = <&pm8909_l7>;
qcom,iris-vddxo-supply = <&pm8909_l7>;
qcom,iris-vddrfa-supply = <&pm8909_l10>;
qcom,iris-vddpa-supply = <&pm8909_l9>;
qcom,iris-vdddig-supply = <&pm8909_l5>;
qcom,iris-vddxo-voltage-level = <1800000 0 1800000>;
qcom,iris-vddrfa-voltage-level = <1300000 0 1300000>;
qcom,iris-vddpa-voltage-level = <3300000 0 3300000>;
qcom,iris-vdddig-voltage-level = <1800000 0 1800000>;
qcom,vddmx-voltage-level = <5 1 7>;
qcom,vddcx-voltage-level = <5 1 7>;
qcom,vddpx-voltage-level = <1800000 0 1800000>;
qcom,iris-vddxo-current = <10000>;
qcom,iris-vddrfa-current = <100000>;
qcom,iris-vddpa-current = <515000>;
qcom,iris-vdddig-current = <10000>;
qcom,pronto-vddmx-current = <0>;
qcom,pronto-vddcx-current = <0>;
qcom,pronto-vddpx-current = <0>;
pinctrl-names = "wcnss_default", "wcnss_sleep",
"wcnss_gpio_default";
pinctrl-0 = <&wcnss_default>;
pinctrl-1 = <&wcnss_sleep>;
pinctrl-2 = <&wcnss_gpio_default>;
gpios = <&msm_gpio 40 0>, <&msm_gpio 41 0>, <&msm_gpio 42 0>,
<&msm_gpio 43 0>, <&msm_gpio 44 0>;
clocks = <&clock_rpm clk_xo_wlan_clk>,
<&clock_rpm clk_rf_clk2>,
<&clock_debug clk_gcc_debug_mux>,
<&clock_gcc clk_wcnss_m_clk>;
clock-names = "xo", "rf_clk", "measure", "wcnss_debug";
qcom,wlan-rx-buff-count = <512>;
qcom,has-autodetect-xo;
qcom,is-pronto-v3;
qcom,is-dual-band-disabled;
qcom,is-pronto-vadc;
qcom,has-pronto-hw;
qcom,wcnss-adc_tm = <&pm8909_adc_tm>;
};
usb_otg: usb@78d9000 {
compatible = "qcom,hsusb-otg";
reg = <0x78d9000 0x400>, <0x6c000 0x200>;
reg-names = "core", "phy_csr";
interrupts = <0 134 0>,<0 140 0>;
interrupt-names = "core_irq", "async_irq";
hsusb_vdd_dig-supply = <&pm8909_l2>;
HSUSB_1p8-supply = <&pm8909_l7>;
HSUSB_3p3-supply = <&pm8909_l13>;
qcom,vdd-voltage-level = <0 1200000 1200000>;
qcom,hsusb-otg-phy-init-seq = <0x73 0x80 0xffffffff>;
qcom,hsusb-otg-phy-type = <3>; /* SNPS Femto PHY */
qcom,hsusb-otg-mode = <1>; /* DEVICE only */
qcom,hsusb-otg-otg-control = <2>; /* PMIC */
qcom,dp-manual-pullup;
qcom,phy-dvdd-always-on;
qcom,hsusb-otg-delay-lpm;
qcom,hsusb-otg-mpm-dpsehv-int = <49>;
qcom,hsusb-otg-mpm-dmsehv-int = <58>;
qcom,msm-bus,name = "usb2";
qcom,msm-bus,num-cases = <3>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<87 512 0 0>,
<87 512 80000 0>,
<87 512 6000 6000>;
clocks = <&clock_gcc clk_gcc_usb_hs_ahb_clk>,
<&clock_gcc clk_gcc_usb_hs_system_clk>,
<&clock_gcc clk_gcc_usb2a_phy_sleep_clk>,
<&clock_rpm clk_bimc_usb_a_clk>,
<&clock_rpm clk_snoc_usb_a_clk>,
<&clock_rpm clk_pcnoc_usb_a_clk>,
<&clock_gcc clk_gcc_qusb2_phy_clk>,
<&clock_gcc clk_gcc_usb2_hs_phy_only_clk>,
<&clock_gcc clk_gcc_usb_hs_phy_cfg_ahb_clk>,
<&clock_rpm clk_xo_otg_clk>;
clock-names = "iface_clk", "core_clk", "sleep_clk",
"bimc_clk", "snoc_clk", "pcnoc_clk",
"phy_reset_clk", "phy_por_clk", "phy_csr_clk",
"xo";
qcom,bus-clk-rate = <400000000 200000000 100000000>;
qcom,max-nominal-sysclk-rate = <100000000>;
qcom,boost-sysclk-with-streaming;
resets = <&clock_gcc GCC_USB_HS_BCR>,
<&clock_gcc GCC_QUSB2_PHY_BCR>,
<&clock_gcc GCC_USB2_HS_PHY_ONLY_BCR>;
reset-names = "core_reset", "phy_reset", "phy_por_reset";
};
android_usb: android_usb@086000c8 {
compatible = "qcom,android-usb";
reg = <0x086000c8 0xc8>;
qcom,pm-qos-latency = <2 1001 12701>;
};
qcom,usbbam@78c4000 {
compatible = "qcom,usb-bam-msm";
reg = <0x78c4000 0x15000>;
reg-names = "hsusb";
interrupts = <0 135 0>;
interrupt-names = "hsusb";
qcom,bam-type = <1>;
qcom,usb-bam-num-pipes = <2>;
qcom,usb-bam-fifo-baseaddr = <0x08603800>;
qcom,ignore-core-reset-ack;
qcom,disable-clk-gating;
qcom,reset-bam-on-disconnect;
qcom,pipe0 {
label = "hsusb-qdss-in-0";
qcom,usb-bam-mem-type = <2>;
qcom,dir = <1>;
qcom,pipe-num = <0>;
qcom,peer-bam = <0>;
qcom,peer-bam-physical-address = <0x884000>;
qcom,src-bam-pipe-index = <0>;
qcom,dst-bam-pipe-index = <0>;
qcom,data-fifo-offset = <0x0>;
qcom,data-fifo-size = <0x600>;
qcom,descriptor-fifo-offset = <0x600>;
qcom,descriptor-fifo-size = <0x200>;
};
};
spmi_bus: qcom,spmi@200f000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0x200f000 0x1000>,
<0x2400000 0x400000>,
<0x2c00000 0x400000>,
<0x3800000 0x200000>,
<0x200a000 0x2100>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupt-names = "periph_irq";
interrupts = <0 190 0>;
qcom,ee = <0>;
qcom,channel = <0>;
#address-cells = <1>;
#size-cells = <1>;
#interrupt-cells = <4>;
interrupt-controller;
cell-index = <0>;
};
qcom,rmtfs_sharedmem@87c00000 {
compatible = "qcom,sharedmem-uio";
reg = <0x87c00000 0xe0000>;
reg-names = "rmtfs";
qcom,client-id = <0x00000001>;
};
qcom,dsp_sharedmem@87ce0000 {
compatible = "qcom,sharedmem-uio";
reg = <0x87ce0000 0x10000>;
reg-names = "rfsa_dsp";
qcom,client-id = <0x011013ec>;
};
qcom,mdm_sharedmem@87cf0000 {
compatible = "qcom,sharedmem-uio";
reg = <0x87cf0000 0x10000>;
reg-names = "rfsa_mdm";
qcom,client-id = <0x011013ed>;
};
cpu-pmu {
compatible = "arm,cortex-a7-pmu";
qcom,irq-is-percpu;
interrupts = <1 7 0xf00>;
};
jtag_fuse: jtagfuse@5e01c {
compatible = "qcom,jtag-fuse-v2";
reg = <0x5e01c 0x8>;
reg-names = "fuse-base";
};
jtag_mm0: jtagmm@84c000 {
compatible = "qcom,jtag-mm";
reg = <0x84c000 0x1000>,
<0x840000 0x1000>;
reg-names = "etm-base","debug-base";
clocks = <&clock_rpm clk_qdss_clk>,
<&clock_rpm clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU0>;
};
jtag_mm1: jtagmm@84d000 {
compatible = "qcom,jtag-mm";
reg = <0x84d000 0x1000>,
<0x842000 0x1000>;
reg-names = "etm-base","debug-base";
clocks = <&clock_rpm clk_qdss_clk>,
<&clock_rpm clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU1>;
};
jtag_mm2: jtagmm@84e000 {
compatible = "qcom,jtag-mm";
reg = <0x84e000 0x1000>,
<0x844000 0x1000>;
reg-names = "etm-base","debug-base";
clocks = <&clock_rpm clk_qdss_clk>,
<&clock_rpm clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU2>;
};
jtag_mm3: jtagmm@84f000 {
compatible = "qcom,jtag-mm";
reg = <0x84f000 0x1000>,
<0x846000 0x1000>;
reg-names = "etm-base","debug-base";
clocks = <&clock_rpm clk_qdss_clk>,
<&clock_rpm clk_qdss_a_clk>;
clock-names = "core_clk", "core_a_clk";
qcom,coresight-jtagmm-cpu = <&CPU3>;
};
qnand_1: nand@7980000 {
compatible = "qcom,msm-nand";
reg = <0x7980000 0x1000>,
<0x7984000 0x1a000>,
<0x5e02c 0x4>;
reg-names = "nand_phys",
"bam_phys", "boot_cfg";
qcom,reg-adjustment-offset = <0>;
interrupts = <0 132 0>;
interrupt-names = "bam_irq";
qcom,msm-bus,name = "qpic_nand";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<91 512 0 0>,
/* Voting for max b/w on PNOC bus for now */
<91 512 400000 800000>;
clock-names = "core_clk";
clocks = <&clock_rpm clk_qpic_clk>;
status = "disabled";
};
sdhc_1: sdhci@7824000 {
compatible = "qcom,sdhci-msm";
reg = <0x07824900 0x11c>, <0x07824000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <0 123 0>, <0 138 0>;
interrupt-names = "hc_irq", "pwr_irq";
qcom,bus-width = <8>;
qcom,pm-qos-irq-type = "affine_irq";
qcom,pm-qos-irq-latency = <2 250>;
qcom,msm-bus,name = "sdhc1";
qcom,msm-bus,num-cases = <8>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps = <78 512 0 0>, /* No vote */
<78 512 1046 3200>, /* 400 KB/s*/
<78 512 52286 160000>, /* 20 MB/s */
<78 512 65360 200000>, /* 25 MB/s */
<78 512 130718 400000>, /* 50 MB/s */
<78 512 261438 800000>, /* 100 MB/s */
<78 512 261438 800000>, /* 200 MB/s */
<78 512 1338562 4096000>; /* Max. bandwidth */
qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
100000000 200000000 4294967295>;
clocks = <&clock_gcc clk_gcc_sdcc1_ahb_clk>,
<&clock_gcc clk_gcc_sdcc1_apps_clk>;
clock-names = "iface_clk", "core_clk";
qcom,clk-rates = <400000 25000000 50000000 100000000 177770000>;
qcom,devfreq,freq-table = <50000000 177770000>;
status = "disabled";
};
sdhc_2: sdhci@07864000 {
compatible = "qcom,sdhci-msm";
reg = <0x07864900 0x11c>, <0x07864000 0x800>;
reg-names = "hc_mem", "core_mem";
interrupts = <0 125 0>, <0 221 0>;
interrupt-names = "hc_irq", "pwr_irq";
qcom,bus-width = <4>;
qcom,pm-qos-irq-type = "affine_irq";
qcom,pm-qos-irq-latency = <2 250>;
qcom,msm-bus,name = "sdhc2";
qcom,msm-bus,num-cases = <8>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps = <81 512 0 0>, /* No vote */
<81 512 1046 3200>, /* 400 KB/s*/
<81 512 52286 160000>, /* 20 MB/s */
<81 512 65360 200000>, /* 25 MB/s */
<81 512 130718 400000>, /* 50 MB/s */
<81 512 261438 800000>, /* 100 MB/s */
<81 512 261438 800000>, /* 200 MB/s */
<81 512 1338562 4096000>; /* Max. bandwidth */
qcom,bus-bw-vectors-bps = <0 400000 20000000 25000000 50000000
100000000 200000000 4294967295>;
clocks = <&clock_gcc clk_gcc_sdcc2_ahb_clk>,
<&clock_gcc clk_gcc_sdcc2_apps_clk>;
clock-names = "iface_clk", "core_clk";
qcom,clk-rates = <400000 25000000 50000000 100000000 200000000>;
qcom,devfreq,freq-table = <50000000 200000000>;
status = "disabled";
};
qcom,wdt@b017000 {
compatible = "qcom,msm-watchdog";
reg = <0xb017000 0x1000>;
reg-names = "wdt-base";
interrupts = <0 3 0>, <0 4 0>;
qcom,bark-time = <11000>;
qcom,pet-time = <10000>;
qcom,ipi-ping;
};
qcom,msm-rtb {
compatible = "qcom,msm-rtb";
qcom,rtb-size = <0x100000>; /* 1M EBI1 buffer */
};
qcom,msm-imem@8600000 {
compatible = "qcom,msm-imem";
reg = <0x08600000 0x1000>; /* Address and size of IMEM */
ranges = <0x0 0x08600000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 8>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 32>;
};
pil@94c {
compatible = "qcom,msm-imem-pil";
reg = <0x94c 200>;
};
restart_reason@65c {
compatible = "qcom,msm-imem-restart_reason";
reg = <0x65c 4>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 200>;
};
};
qcom,mpm2-sleep-counter@4a3000 {
compatible = "qcom,mpm2-sleep-counter";
reg = <0x4a3000 0x1000>;
clock-frequency = <32768>;
};
spi_0: spi@78ba000 { /* BLSP1 QUP6 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0x78ba000 0x600>,
<0x7884000 0x23000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 100 0>, <0 238 0>;
spi-max-frequency = <19200000>;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi0_default &spi0_cs0_active>;
pinctrl-1 = <&spi0_sleep &spi0_cs0_sleep>;
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup6_spi_apps_clk>;
clock-names = "iface_clk", "core_clk";
qcom,infinite-mode = <0>;
qcom,use-bam;
qcom,use-pinctrl;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <14>;
qcom,bam-producer-pipe-index = <15>;
qcom,master-id = <86>;
};
spi_2: spi@78b6000 { /* BLSP1 QUP2 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0x78b6000 0x600>,
<0x7884000 0x23000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 96 0>, <0 238 0>;
spi-max-frequency = <50000000>;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi2_default &spi2_cs0_active>;
pinctrl-1 = <&spi2_sleep &spi2_cs0_sleep>;
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup2_spi_apps_clk>;
clock-names = "iface_clk", "core_clk";
qcom,infinite-mode = <0>;
qcom,use-bam;
qcom,use-pinctrl;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <6>;
qcom,bam-producer-pipe-index = <7>;
qcom,master-id = <86>;
status = "disabled";
};
spi_4: spi@78B8000{ /* BLSP1 QUP4 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0x78b8000 0x600>,
<0x7884000 0x23000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 98 0>, <0 238 0>;
spi-max-frequency = <50000000>;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi4_default &spi4_cs0_active>;
pinctrl-1 = <&spi4_sleep &spi4_cs0_sleep>;
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup4_spi_apps_clk>;
clock-names = "iface_clk", "core_clk";
qcom,infinite-mode = <0>;
qcom,use-bam;
qcom,use-pinctrl;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <10>;
qcom,bam-producer-pipe-index = <11>;
qcom,master-id = <86>;
status = "disabled";
};
spi_5: spi@78b9000 { /* BLSP1 QUP5 */
compatible = "qcom,spi-qup-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "spi_physical", "spi_bam_physical";
reg = <0x78b9000 0x600>,
<0x7884000 0x23000>;
interrupt-names = "spi_irq", "spi_bam_irq";
interrupts = <0 99 0>, <0 238 0>;
spi-max-frequency = <50000000>;
pinctrl-names = "spi_default", "spi_sleep";
pinctrl-0 = <&spi5_default &spi5_cs0_active>;
pinctrl-1 = <&spi5_sleep &spi5_cs0_sleep>;
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup5_spi_apps_clk>;
clock-names = "iface_clk", "core_clk";
qcom,infinite-mode = <0>;
qcom,use-bam;
qcom,use-pinctrl;
qcom,ver-reg-exists;
qcom,bam-consumer-pipe-index = <12>;
qcom,bam-producer-pipe-index = <13>;
qcom,master-id = <86>;
status = "disabled";
};
dma_blsp1: qcom,sps-dma@7884000 { /* BLSP1 */
#dma-cells = <4>;
compatible = "qcom,sps-dma";
reg = <0x7884000 0x23000>;
interrupts = <0 238 0>;
qcom,summing-threshold = <10>;
};
i2c_2: i2c@78b6000 { /* BLSP1 QUP2 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0x78b6000 0x1000>;
interrupt-names = "qup_irq";
interrupts = <0 96 0>;
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
clock-names = "iface_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup2_i2c_apps_clk>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_2_active>;
pinctrl-1 = <&i2c_2_sleep>;
qcom,noise-rjct-scl = <0>;
qcom,noise-rjct-sda = <0>;
dmas = <&dma_blsp1 6 64 0x20000020 0x20>,
<&dma_blsp1 7 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <86>;
};
i2c_4: i2c@78b8000 { /* BLSP1 QUP4 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0x78b8000 0x1000>;
interrupt-names = "qup_irq";
interrupts = <0 98 0>;
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup4_i2c_apps_clk>;
clock-names = "iface_clk", "core_clk";
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_4_active>;
pinctrl-1 = <&i2c_4_sleep>;
qcom,noise-rjct-scl = <0>;
qcom,noise-rjct-sda = <0>;
dmas = <&dma_blsp1 10 64 0x20000020 0x20>,
<&dma_blsp1 11 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <86>;
};
i2c_5: i2c@78b9000 { /* BLSP1 QUP5 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0x78b9000 0x1000>;
interrupt-names = "qup_irq";
interrupts = <0 99 0>;
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup5_i2c_apps_clk>;
clock-names = "iface_clk", "core_clk";
qcom,clk-freq-out = <100000>;
qcom,clk-freq-in = <19200000>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_5_active>;
pinctrl-1 = <&i2c_5_sleep>;
qcom,noise-rjct-scl = <0>;
qcom,noise-rjct-sda = <0>;
dmas = <&dma_blsp1 12 64 0x20000020 0x20>,
<&dma_blsp1 13 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <86>;
};
i2c_3: i2c@78b7000 { /* BLSP1 QUP3 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0x78b7000 0x1000>;
interrupt-names = "qup_irq";
interrupts = <0 97 0>;
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup3_i2c_apps_clk>;
clock-names = "iface_clk", "core_clk";
qcom,clk-freq-out = <100000>;
qcom,clk-freq-in = <19200000>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_3_active>;
pinctrl-1 = <&i2c_3_sleep>;
qcom,noise-rjct-scl = <0>;
qcom,noise-rjct-sda = <0>;
dmas = <&dma_blsp1 8 64 0x20000020 0x20>,
<&dma_blsp1 9 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <86>;
};
i2c_1: i2c@78b5000 { /* BLSP1 QUP1 */
compatible = "qcom,i2c-msm-v2";
#address-cells = <1>;
#size-cells = <0>;
reg-names = "qup_phys_addr";
reg = <0x78b5000 0x1000>;
interrupt-names = "qup_irq";
interrupts = <0 95 0>;
clocks = <&clock_gcc clk_gcc_blsp1_ahb_clk>,
<&clock_gcc clk_gcc_blsp1_qup1_i2c_apps_clk>;
clock-names = "iface_clk", "core_clk";
qcom,clk-freq-out = <400000>;
qcom,clk-freq-in = <19200000>;
pinctrl-names = "i2c_active", "i2c_sleep";
pinctrl-0 = <&i2c_1_active>;
pinctrl-1 = <&i2c_1_sleep>;
qcom,noise-rjct-scl = <0>;
qcom,noise-rjct-sda = <0>;
dmas = <&dma_blsp1 4 64 0x20000020 0x20>,
<&dma_blsp1 5 32 0x20000020 0x20>;
dma-names = "tx", "rx";
qcom,master-id = <86>;
};
qcom,venus@1de0000 {
compatible = "qcom,pil-tz-generic";
reg = <0x1de0000 0x4000>;
vdd-supply = <&gdsc_venus>;
qcom,proxy-reg-names = "vdd";
clocks = <&clock_gcc clk_gcc_venus0_vcodec0_clk>,
<&clock_gcc clk_gcc_venus0_ahb_clk>,
<&clock_gcc clk_gcc_venus0_axi_clk>,
<&clock_gcc clk_gcc_crypto_clk>,
<&clock_gcc clk_gcc_crypto_ahb_clk>,
<&clock_gcc clk_gcc_crypto_axi_clk>,
<&clock_gcc clk_crypto_clk_src>;
clock-names = "core_clk", "iface_clk", "bus_clk",
"scm_core_clk", "scm_iface_clk",
"scm_bus_clk", "scm_core_clk_src";
qcom,proxy-clock-names = "core_clk", "iface_clk",
"bus_clk", "scm_core_clk",
"scm_iface_clk", "scm_bus_clk",
"scm_core_clk_src";
qcom,scm_core_clk_src-freq = <80000000>;
qcom,pas-id = <9>;
qcom,mas-crypto = <&mas_crypto>;
qcom,proxy-timeout-ms = <100>;
qcom,firmware-name = "venus";
memory-region = <&venus_qseecom_mem>;
};
pcm0: qcom,msm-pcm {
compatible = "qcom,msm-pcm-dsp";
qcom,msm-pcm-dsp-id = <0>;
};
routing: qcom,msm-pcm-routing {
compatible = "qcom,msm-pcm-routing";
};
pcm1: qcom,msm-pcm-low-latency {
compatible = "qcom,msm-pcm-dsp";
qcom,msm-pcm-dsp-id = <1>;
qcom,msm-pcm-low-latency;
qcom,latency-level = "regular";
};
pcm2: qcom,msm-ultra-low-latency {
compatible = "qcom,msm-pcm-dsp";
qcom,msm-pcm-dsp-id = <2>;
qcom,msm-pcm-low-latency;
qcom,latency-level = "ultra";
};
pcm_noirq: qcom,msm-pcm-dsp-noirq {
compatible = "qcom,msm-pcm-dsp-noirq";
qcom,msm-pcm-low-latency;
qcom,latency-level = "ultra";
};
lpa: qcom,msm-pcm-lpa {
compatible = "qcom,msm-pcm-lpa";
};
compress: qcom,msm-compress-dsp {
compatible = "qcom,msm-compress-dsp";
};
voip: qcom,msm-voip-dsp {
compatible = "qcom,msm-voip-dsp";
};
voice: qcom,msm-pcm-voice {
compatible = "qcom,msm-pcm-voice";
qcom,destroy-cvd;
qcom,vote-bms;
};
stub_codec: qcom,msm-stub-codec {
compatible = "qcom,msm-stub-codec";
};
qcom,msm-dai-fe {
compatible = "qcom,msm-dai-fe";
};
afe: qcom,msm-pcm-afe {
compatible = "qcom,msm-pcm-afe";
};
voice_svc: qcom,msm-voice-svc {
compatible = "qcom,msm-voice-svc";
};
loopback: qcom,msm-pcm-loopback {
compatible = "qcom,msm-pcm-loopback";
};
pcm_noirq: qcom,msm-pcm-dsp-noirq {
compatible = "qcom,msm-pcm-dsp-noirq";
qcom,msm-pcm-low-latency;
qcom,latency-level = "ultra";
};
qcom,msm-dai-mi2s {
compatible = "qcom,msm-dai-mi2s";
dai_mi2s0: qcom,msm-dai-q6-mi2s-prim {
compatible = "qcom,msm-dai-q6-mi2s";
qcom,msm-dai-q6-mi2s-dev-id = <0>;
qcom,msm-mi2s-rx-lines = <3>;
qcom,msm-mi2s-tx-lines = <0>;
};
dai_mi2s1: qcom,msm-dai-q6-mi2s-sec {
compatible = "qcom,msm-dai-q6-mi2s";
qcom,msm-dai-q6-mi2s-dev-id = <1>;
qcom,msm-mi2s-rx-lines = <1>;
qcom,msm-mi2s-tx-lines = <0>;
};
dai_mi2s2: qcom,msm-dai-q6-mi2s-tert {
compatible = "qcom,msm-dai-q6-mi2s";
qcom,msm-dai-q6-mi2s-dev-id = <2>;
qcom,msm-mi2s-rx-lines = <0>;
qcom,msm-mi2s-tx-lines = <3>;
};
dai_mi2s3: qcom,msm-dai-q6-mi2s-quat {
compatible = "qcom,msm-dai-q6-mi2s";
qcom,msm-dai-q6-mi2s-dev-id = <3>;
qcom,msm-mi2s-rx-lines = <0>;
qcom,msm-mi2s-tx-lines = <3>;
};
dai_mi2s4: qcom,msm-dai-q6-mi2s-quin {
compatible = "qcom,msm-dai-q6-mi2s";
qcom,msm-dai-q6-mi2s-dev-id = <4>;
qcom,msm-mi2s-rx-lines = <1>;
qcom,msm-mi2s-tx-lines = <2>;
};
dai_mi2s5: qcom,msm-dai-q6-mi2s-senary {
compatible = "qcom,msm-dai-q6-mi2s";
qcom,msm-dai-q6-mi2s-dev-id = <6>;
qcom,msm-mi2s-rx-lines = <0>;
qcom,msm-mi2s-tx-lines = <3>;
};
};
dai_hdmi: qcom,msm-dai-q6-hdmi {
compatible = "qcom,msm-dai-q6-hdmi";
qcom,msm-dai-q6-dev-id = <8>;
};
lsm: qcom,msm-lsm-client {
compatible = "qcom,msm-lsm-client";
};
qcom,msm-dai-q6 {
compatible = "qcom,msm-dai-q6";
sb_0_rx: qcom,msm-dai-q6-sb-0-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <16384>;
};
sb_0_tx: qcom,msm-dai-q6-sb-0-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <16385>;
};
sb_1_rx: qcom,msm-dai-q6-sb-1-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <16386>;
};
sb_1_tx: qcom,msm-dai-q6-sb-1-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <16387>;
};
sb_3_rx: qcom,msm-dai-q6-sb-3-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <16390>;
};
sb_3_tx: qcom,msm-dai-q6-sb-3-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <16391>;
};
sb_4_rx: qcom,msm-dai-q6-sb-4-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <16392>;
};
sb_4_tx: qcom,msm-dai-q6-sb-4-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <16393>;
};
bt_sco_rx: qcom,msm-dai-q6-bt-sco-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <12288>;
};
bt_sco_tx: qcom,msm-dai-q6-bt-sco-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <12289>;
};
bt_a2dp_rx: qcom,msm-dai-q6-bt-a2dp-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <12290>;
};
int_fm_rx: qcom,msm-dai-q6-int-fm-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <12292>;
};
int_fm_tx: qcom,msm-dai-q6-int-fm-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <12293>;
};
afe_pcm_rx: qcom,msm-dai-q6-be-afe-pcm-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <224>;
};
afe_pcm_tx: qcom,msm-dai-q6-be-afe-pcm-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <225>;
};
afe_proxy_rx: qcom,msm-dai-q6-afe-proxy-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <241>;
};
afe_proxy_tx: qcom,msm-dai-q6-afe-proxy-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <240>;
};
afe_loopback_tx: qcom,msm-dai-q6-afe-loopback-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <24577>;
};
incall_record_rx: qcom,msm-dai-q6-incall-record-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <32771>;
};
incall_record_tx: qcom,msm-dai-q6-incall-record-tx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <32772>;
};
incall_music_rx: qcom,msm-dai-q6-incall-music-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <32773>;
};
incall_music_2_rx: qcom,msm-dai-q6-incall-music-2-rx {
compatible = "qcom,msm-dai-q6-dev";
qcom,msm-dai-q6-dev-id = <32770>;
};
};
hostless: qcom,msm-pcm-hostless {
compatible = "qcom,msm-pcm-hostless";
};
dai_pri_auxpcm: qcom,msm-pri-auxpcm {
compatible = "qcom,msm-auxpcm-dev";
qcom,msm-cpudai-auxpcm-mode = <0>, <0>;
qcom,msm-cpudai-auxpcm-sync = <1>, <1>;
qcom,msm-cpudai-auxpcm-frame = <5>, <4>;
qcom,msm-cpudai-auxpcm-quant = <2>, <2>;
qcom,msm-cpudai-auxpcm-num-slots = <1>, <1>;
qcom,msm-cpudai-auxpcm-slot-mapping = <1>, <1>;
qcom,msm-cpudai-auxpcm-data = <0>, <0>;
qcom,msm-cpudai-auxpcm-pcm-clk-rate = <2048000>, <2048000>;
qcom,msm-auxpcm-interface = "primary";
};
qcom,msm-audio-ion {
compatible = "qcom,msm-audio-ion";
};
qcom,msm-audio-apr {
compatible = "qcom,msm-audio-apr";
msm_audio_apr_dummy {
compatible = "qcom,msm-audio-apr-dummy";
};
};
qcom,mdsprpc-mem {
compatible = "qcom,msm-mdsprpc-mem-region";
memory-region = <&adsp_mem>;
};
qcom,msm-adsprpc-mem {
compatible = "qcom,msm-adsprpc-mem-region";
memory-region = <&adsp_mem>;
restrict-access;
};
qcom,msm_fastrpc {
compatible = "qcom,msm-fastrpc-legacy-compute";
};
qcom,msm-adsp-loader {
compatible = "qcom,adsp-loader";
qcom,adsp-state = <0>;
qcom,proc-img-to-load = "modem";
};
qcom,avtimer@770600c {
compatible = "qcom,avtimer";
reg = <0x0770600C 0x4>,
<0x07706010 0x4>;
reg-names = "avtimer_lsb_addr", "avtimer_msb_addr";
qcom,clk-div = <27>;
};
qcom,memshare {
compatible = "qcom,memshare";
qcom,client_1 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x200000>;
qcom,client-id = <0>;
qcom,allocate-boot-time;
label = "modem";
};
qcom,client_2 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0x300000>;
qcom,client-id = <2>;
label = "modem";
};
qcom,client_3 {
compatible = "qcom,memshare-peripheral";
qcom,peripheral-size = <0>;
qcom,client-id = <1>;
label = "modem";
};
};
qcom_tzlog: tz-log@8600720 {
compatible = "qcom,tz-log";
reg = <0x08600720 0x1000>;
status = "disabled";
};
qcom_rng: qrng@22000 {
compatible = "qcom,msm-rng";
reg = <0x22000 0x200>;
qcom,msm-rng-iface-clk;
qcom,msm-bus,name = "msm-rng-noc";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<1 618 0 0>, /* No vote */
<1 618 0 800>; /* 100 MB/s */
clocks = <&clock_gcc clk_gcc_prng_ahb_clk>;
clock-names = "iface_clk";
status = "disabled";
};
qcom_crypto: qcrypto@720000 {
compatible = "qcom,qcrypto";
reg = <0x720000 0x20000>,
<0x704000 0x20000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <0 207 0>;
qcom,bam-pipe-pair = <2>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,clk-mgmt-sus-res;
qcom,msm-bus,name = "qcrypto-noc";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<55 512 0 0>,
<55 512 393600 800000>; /* 49.2MHz & 100MHz */
clocks = <&clock_gcc clk_crypto_clk_src>,
<&clock_gcc clk_gcc_crypto_clk>,
<&clock_gcc clk_gcc_crypto_ahb_clk>,
<&clock_gcc clk_gcc_crypto_axi_clk>;
clock-names = "core_clk_src", "core_clk",
"iface_clk", "bus_clk";
qcom,use-sw-aes-cbc-ecb-ctr-algo;
qcom,use-sw-aes-xts-algo;
qcom,use-sw-ahash-algo;
status = "disabled";
qcom,ce-opp-freq = <100000000>;
};
qcom_cedev: qcedev@720000 {
compatible = "qcom,qcedev";
reg = <0x720000 0x20000>,
<0x704000 0x20000>;
reg-names = "crypto-base","crypto-bam-base";
interrupts = <0 207 0>;
qcom,bam-pipe-pair = <1>;
qcom,ce-hw-instance = <0>;
qcom,ce-device = <0>;
qcom,ce-hw-shared;
qcom,msm-bus,name = "qcedev-noc";
qcom,msm-bus,num-cases = <2>;
qcom,msm-bus,num-paths = <1>;
qcom,msm-bus,vectors-KBps =
<55 512 0 0>,
<55 512 3936000 393600>;
clocks = <&clock_gcc clk_crypto_clk_src>,
<&clock_gcc clk_gcc_crypto_clk>,
<&clock_gcc clk_gcc_crypto_ahb_clk>,
<&clock_gcc clk_gcc_crypto_axi_clk>;
clock-names = "core_clk_src", "core_clk",
"iface_clk", "bus_clk";
status = "disabled";
qcom,ce-opp-freq = <100000000>;
};
qcom_seecom: qseecom@87a00000 {
compatible = "qcom,qseecom";
reg = <0x87a00000 0x200000>;
reg-names = "secapp-region";
qcom,disk-encrypt-pipe-pair = <2>;
qcom,hlos-ce-hw-instance = <0>;
qcom,qsee-ce-hw-instance = <0>;
qcom,msm-bus,name = "qseecom-noc";
qcom,msm-bus,num-cases = <4>;
qcom,msm-bus,num-paths = <1>;
qcom,support-bus-scaling;
qcom,support-fde;
qcom,msm-bus,vectors-KBps =
<55 512 0 0>,
<55 512 0 0>,
<55 512 120000 1200000>,
<55 512 393600 3936000>;
clocks = <&clock_gcc clk_crypto_clk_src>,
<&clock_gcc clk_gcc_crypto_clk>,
<&clock_gcc clk_gcc_crypto_ahb_clk>,
<&clock_gcc clk_gcc_crypto_axi_clk>;
clock-names = "core_clk_src", "core_clk",
"iface_clk", "bus_clk";
status = "disabled";
qcom,ce-opp-freq = <100000000>;
};
qcom,pronto@a21b000 {
compatible = "qcom,pil-tz-generic";
reg = <0x0a21b000 0x3000>;
interrupts = <0 149 1>;
vdd_pronto_pll-supply = <&pm8909_l7>;
proxy-reg-names = "vdd_pronto_pll";
vdd_pronto_pll-uV-uA = <1800000 18000>;
clocks = <&clock_rpm clk_xo_pil_pronto_clk>,
<&clock_gcc clk_gcc_crypto_clk>,
<&clock_gcc clk_gcc_crypto_ahb_clk>,
<&clock_gcc clk_gcc_crypto_axi_clk>,
<&clock_gcc clk_crypto_clk_src>;
clock-names = "xo", "scm_core_clk", "scm_iface_clk",
"scm_bus_clk", "scm_core_clk_src";
qcom,proxy-clock-names = "xo", "scm_core_clk", "scm_iface_clk",
"scm_bus_clk", "scm_core_clk_src";
qcom,scm_core_clk_src = <80000000>;
qcom,pas-id = <6>;
qcom,proxy-timeout-ms = <10000>;
qcom,smem-id = <422>;
qcom,sysmon-id = <6>;
qcom,ssctl-instance-id = <0x13>;
qcom,firmware-name = "wcnss";
qcom,mas-crypto = <&mas_crypto>;
/* GPIO inputs from wcnss */
qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_4_in 0 0>;
qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_4_in 1 0>;
qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_4_in 2 0>;
qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_4_in 3 0>;
/* GPIO output to wcnss */
qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_4_out 0 0>;
memory-region = <&peripheral_mem>;
};
qcom,mss@4080000 {
compatible = "qcom,pil-q6v55-mss";
reg = <0x04080000 0x100>,
<0x0194f000 0x010>,
<0x01950000 0x008>,
<0x01951000 0x008>,
<0x04020000 0x040>,
<0x0183e000 0x004>;
reg-names = "qdsp6_base", "halt_q6", "halt_modem", "halt_nc",
"rmb_base", "restart_reg";
interrupts = <0 24 1>;
vdd_cx-supply = <&pm8909_s1_corner>;
vdd_cx-voltage = <7>;
vdd_mx-supply = <&pm8909_l3_corner_ao>;
vdd_mx-uV = <3>;
vdd_pll-supply = <&pm8909_l7>;
qcom,vdd_pll = <1800000>;
clocks = <&clock_rpm clk_xo_pil_mss_clk>,
<&clock_gcc clk_gcc_mss_cfg_ahb_clk>,
<&clock_gcc clk_gcc_mss_q6_bimc_axi_clk>,
<&clock_gcc clk_gcc_boot_rom_ahb_clk>;
clock-names = "xo", "iface_clk", "bus_clk", "mem_clk";
qcom,proxy-clock-names = "xo";
qcom,active-clock-names = "iface_clk", "bus_clk", "mem_clk";
qcom,firmware-name = "modem";
qcom,pil-self-auth;
qcom,sequential-fw-load;
qcom,sysmon-id = <0>;
qcom,ssctl-instance-id = <0x12>;
qcom,reset-clk;
/* GPIO inputs from mss */
qcom,gpio-err-fatal = <&smp2pgpio_ssr_smp2p_1_in 0 0>;
qcom,gpio-err-ready = <&smp2pgpio_ssr_smp2p_1_in 1 0>;
qcom,gpio-proxy-unvote = <&smp2pgpio_ssr_smp2p_1_in 2 0>;
qcom,gpio-stop-ack = <&smp2pgpio_ssr_smp2p_1_in 3 0>;
/* GPIO output to mss */
qcom,gpio-force-stop = <&smp2pgpio_ssr_smp2p_1_out 0 0>;
memory-region = <&modem_adsp_mem>;
};
cpu0_slp_sts: cpu-sleep-status@b088008 {
reg = <0xb088008 0x100>;
qcom,sleep-status-mask= <0x80000>;
};
cpu1_slp_sts: cpu-sleep-status@b098008 {
reg = <0xb098008 0x100>;
qcom,sleep-status-mask= <0x80000>;
};
cpu2_slp_sts: cpu-sleep-status@b0a8008 {
reg = <0xb0a8008 0x100>;
qcom,sleep-status-mask= <0x80000>;
};
cpu3_slp_sts: cpu-sleep-status@b0b8008 {
reg = <0xb0b8008 0x100>;
qcom,sleep-status-mask= <0x80000>;
};
};
&gdsc_venus {
clock-names = "bus_clk", "core_clk";
clocks = <&clock_gcc clk_gcc_venus0_axi_clk>,
<&clock_gcc clk_gcc_venus0_vcodec0_clk>;
status = "okay";
};
&gdsc_venus_core0 {
qcom,support-hw-trigger;
clock-names = "core0_clk";
clocks = <&clock_gcc clk_gcc_venus0_core0_vcodec0_clk>;
status = "okay";
};
&gdsc_mdss {
clock-names = "core_clk", "bus_clk";
clocks = <&clock_gcc clk_gcc_mdss_mdp_clk>,
<&clock_gcc clk_gcc_mdss_axi_clk>;
status = "okay";
};
&gdsc_vfe {
clock-names = "core_clk", "bus_clk", "csi_clk";
clocks = <&clock_gcc clk_gcc_camss_vfe0_clk>,
<&clock_gcc clk_gcc_camss_vfe_axi_clk>,
<&clock_gcc clk_gcc_camss_csi_vfe0_clk>;
status = "okay";
};
&gdsc_oxili_gx {
clock-names = "core_clk";
clocks = <&clock_gcc clk_gcc_oxili_gfx3d_clk>;
status = "okay";
};
#include "msm8909-thermal.dtsi"
#include "msm8909-pinctrl.dtsi"