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Thierry Redingdec72732013-09-03 08:45:46 +02001/*
2 * Copyright (C) 2013 NVIDIA Corporation
3 *
Thierry Reding9a2ac2d2014-02-11 15:52:01 +01004 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
Thierry Redingdec72732013-09-03 08:45:46 +02007 */
8
9#ifndef DRM_TEGRA_DSI_H
10#define DRM_TEGRA_DSI_H
11
12#define DSI_INCR_SYNCPT 0x00
13#define DSI_INCR_SYNCPT_CONTROL 0x01
14#define DSI_INCR_SYNCPT_ERROR 0x02
15#define DSI_CTXSW 0x08
16#define DSI_RD_DATA 0x09
17#define DSI_WR_DATA 0x0a
18#define DSI_POWER_CONTROL 0x0b
19#define DSI_POWER_CONTROL_ENABLE (1 << 0)
20#define DSI_INT_ENABLE 0x0c
21#define DSI_INT_STATUS 0x0d
22#define DSI_INT_MASK 0x0e
23#define DSI_HOST_CONTROL 0x0f
Thierry Reding0fffdf62014-11-07 17:25:26 +010024#define DSI_HOST_CONTROL_FIFO_RESET (1 << 21)
25#define DSI_HOST_CONTROL_CRC_RESET (1 << 20)
26#define DSI_HOST_CONTROL_TX_TRIG_SOL (0 << 12)
27#define DSI_HOST_CONTROL_TX_TRIG_FIFO (1 << 12)
28#define DSI_HOST_CONTROL_TX_TRIG_HOST (2 << 12)
Thierry Redingdec72732013-09-03 08:45:46 +020029#define DSI_HOST_CONTROL_RAW (1 << 6)
30#define DSI_HOST_CONTROL_HS (1 << 5)
Thierry Reding0fffdf62014-11-07 17:25:26 +010031#define DSI_HOST_CONTROL_FIFO_SEL (1 << 4)
32#define DSI_HOST_CONTROL_IMM_BTA (1 << 3)
33#define DSI_HOST_CONTROL_PKT_BTA (1 << 2)
Thierry Redingdec72732013-09-03 08:45:46 +020034#define DSI_HOST_CONTROL_CS (1 << 1)
35#define DSI_HOST_CONTROL_ECC (1 << 0)
36#define DSI_CONTROL 0x10
37#define DSI_CONTROL_HS_CLK_CTRL (1 << 20)
38#define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16)
39#define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12)
40#define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8)
41#define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4)
42#define DSI_CONTROL_DCS_ENABLE (1 << 3)
43#define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2)
44#define DSI_CONTROL_VIDEO_ENABLE (1 << 1)
45#define DSI_CONTROL_HOST_ENABLE (1 << 0)
46#define DSI_SOL_DELAY 0x11
47#define DSI_MAX_THRESHOLD 0x12
48#define DSI_TRIGGER 0x13
Thierry Reding0fffdf62014-11-07 17:25:26 +010049#define DSI_TRIGGER_HOST (1 << 1)
50#define DSI_TRIGGER_VIDEO (1 << 0)
Thierry Redingdec72732013-09-03 08:45:46 +020051#define DSI_TX_CRC 0x14
52#define DSI_STATUS 0x15
53#define DSI_STATUS_IDLE (1 << 10)
Thierry Reding0fffdf62014-11-07 17:25:26 +010054#define DSI_STATUS_UNDERFLOW (1 << 9)
55#define DSI_STATUS_OVERFLOW (1 << 8)
Thierry Redingdec72732013-09-03 08:45:46 +020056#define DSI_INIT_SEQ_CONTROL 0x1a
57#define DSI_INIT_SEQ_DATA_0 0x1b
58#define DSI_INIT_SEQ_DATA_1 0x1c
59#define DSI_INIT_SEQ_DATA_2 0x1d
60#define DSI_INIT_SEQ_DATA_3 0x1e
61#define DSI_INIT_SEQ_DATA_4 0x1f
62#define DSI_INIT_SEQ_DATA_5 0x20
63#define DSI_INIT_SEQ_DATA_6 0x21
64#define DSI_INIT_SEQ_DATA_7 0x22
65#define DSI_PKT_SEQ_0_LO 0x23
66#define DSI_PKT_SEQ_0_HI 0x24
67#define DSI_PKT_SEQ_1_LO 0x25
68#define DSI_PKT_SEQ_1_HI 0x26
69#define DSI_PKT_SEQ_2_LO 0x27
70#define DSI_PKT_SEQ_2_HI 0x28
71#define DSI_PKT_SEQ_3_LO 0x29
72#define DSI_PKT_SEQ_3_HI 0x2a
73#define DSI_PKT_SEQ_4_LO 0x2b
74#define DSI_PKT_SEQ_4_HI 0x2c
75#define DSI_PKT_SEQ_5_LO 0x2d
76#define DSI_PKT_SEQ_5_HI 0x2e
77#define DSI_DCS_CMDS 0x33
78#define DSI_PKT_LEN_0_1 0x34
79#define DSI_PKT_LEN_2_3 0x35
80#define DSI_PKT_LEN_4_5 0x36
81#define DSI_PKT_LEN_6_7 0x37
82#define DSI_PHY_TIMING_0 0x3c
83#define DSI_PHY_TIMING_1 0x3d
84#define DSI_PHY_TIMING_2 0x3e
85#define DSI_BTA_TIMING 0x3f
86
87#define DSI_TIMING_FIELD(value, period, hwinc) \
88 ((DIV_ROUND_CLOSEST(value, period) - (hwinc)) & 0xff)
89
90#define DSI_TIMEOUT_0 0x44
91#define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16)
92#define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0)
93#define DSI_TIMEOUT_1 0x45
94#define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16)
95#define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0)
96#define DSI_TO_TALLY 0x46
97#define DSI_TALLY_TA(x) (((x) & 0xff) << 16)
98#define DSI_TALLY_LRX(x) (((x) & 0xff) << 8)
99#define DSI_TALLY_HTX(x) (((x) & 0xff) << 0)
100#define DSI_PAD_CONTROL_0 0x4b
101#define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0)
102#define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8)
103#define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16)
104#define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24)
105#define DSI_PAD_CONTROL_CD 0x4c
106#define DSI_PAD_CD_STATUS 0x4d
107#define DSI_VIDEO_MODE_CONTROL 0x4e
108#define DSI_PAD_CONTROL_1 0x4f
109#define DSI_PAD_CONTROL_2 0x50
110#define DSI_PAD_OUT_CLK(x) (((x) & 0x7) << 0)
111#define DSI_PAD_LP_DN(x) (((x) & 0x7) << 4)
112#define DSI_PAD_LP_UP(x) (((x) & 0x7) << 8)
113#define DSI_PAD_SLEW_DN(x) (((x) & 0x7) << 12)
114#define DSI_PAD_SLEW_UP(x) (((x) & 0x7) << 16)
115#define DSI_PAD_CONTROL_3 0x51
Thierry Redingddfb4062015-04-08 16:56:22 +0200116#define DSI_PAD_PREEMP_PD_CLK(x) (((x) & 0x3) << 12)
117#define DSI_PAD_PREEMP_PU_CLK(x) (((x) & 0x3) << 8)
118#define DSI_PAD_PREEMP_PD(x) (((x) & 0x3) << 4)
119#define DSI_PAD_PREEMP_PU(x) (((x) & 0x3) << 0)
Thierry Redingdec72732013-09-03 08:45:46 +0200120#define DSI_PAD_CONTROL_4 0x52
121#define DSI_GANGED_MODE_CONTROL 0x53
Thierry Redinge94236c2014-10-07 16:10:24 +0200122#define DSI_GANGED_MODE_CONTROL_ENABLE (1 << 0)
Thierry Redingdec72732013-09-03 08:45:46 +0200123#define DSI_GANGED_MODE_START 0x54
124#define DSI_GANGED_MODE_SIZE 0x55
125#define DSI_RAW_DATA_BYTE_COUNT 0x56
126#define DSI_ULTRA_LOW_POWER_CONTROL 0x57
127#define DSI_INIT_SEQ_DATA_8 0x58
128#define DSI_INIT_SEQ_DATA_9 0x59
129#define DSI_INIT_SEQ_DATA_10 0x5a
130#define DSI_INIT_SEQ_DATA_11 0x5b
131#define DSI_INIT_SEQ_DATA_12 0x5c
132#define DSI_INIT_SEQ_DATA_13 0x5d
133#define DSI_INIT_SEQ_DATA_14 0x5e
134#define DSI_INIT_SEQ_DATA_15 0x5f
135
Thierry Redingf7d68892014-03-13 08:50:39 +0100136/*
137 * pixel format as used in the DSI_CONTROL_FORMAT field
138 */
139enum tegra_dsi_format {
140 TEGRA_DSI_FORMAT_16P,
141 TEGRA_DSI_FORMAT_18NP,
142 TEGRA_DSI_FORMAT_18P,
143 TEGRA_DSI_FORMAT_24P,
144};
145
Thierry Redingdec72732013-09-03 08:45:46 +0200146#endif