blob: 25d2d8ccb12062567eee7e0a2ed6894bbdd0fa94 [file] [log] [blame]
Stephen Warrena7db2c12011-10-25 02:01:28 +00001/dts-v1/;
2
Stephen Warrena7db2c12011-10-25 02:01:28 +00003/include/ "tegra20.dtsi"
4
5/ {
6 model = "Compulab TrimSlice board";
7 compatible = "compulab,trimslice", "nvidia,tegra20";
8
Stephen Warrenf9eb26a2012-05-11 16:17:47 -06009 memory {
Stephen Warren95decf82012-05-11 16:11:38 -060010 reg = <0x00000000 0x40000000>;
Stephen Warrena7db2c12011-10-25 02:01:28 +000011 };
12
Stephen Warrenf9eb26a2012-05-11 16:17:47 -060013 pinmux {
Stephen Warrenecc295b2012-03-15 16:27:36 -060014 pinctrl-names = "default";
15 pinctrl-0 = <&state_default>;
16
17 state_default: pinmux {
18 ata {
19 nvidia,pins = "ata";
20 nvidia,function = "ide";
21 };
22 atb {
23 nvidia,pins = "atb", "gma";
24 nvidia,function = "sdio4";
25 };
26 atc {
27 nvidia,pins = "atc", "gmb";
28 nvidia,function = "nand";
29 };
30 atd {
31 nvidia,pins = "atd", "ate", "gme", "pta";
32 nvidia,function = "gmi";
33 };
34 cdev1 {
35 nvidia,pins = "cdev1";
36 nvidia,function = "plla_out";
37 };
38 cdev2 {
39 nvidia,pins = "cdev2";
40 nvidia,function = "pllp_out4";
41 };
42 crtp {
43 nvidia,pins = "crtp";
44 nvidia,function = "crt";
45 };
46 csus {
47 nvidia,pins = "csus";
48 nvidia,function = "vi_sensor_clk";
49 };
50 dap1 {
51 nvidia,pins = "dap1";
52 nvidia,function = "dap1";
53 };
54 dap2 {
55 nvidia,pins = "dap2";
56 nvidia,function = "dap2";
57 };
58 dap3 {
59 nvidia,pins = "dap3";
60 nvidia,function = "dap3";
61 };
62 dap4 {
63 nvidia,pins = "dap4";
64 nvidia,function = "dap4";
65 };
66 ddc {
67 nvidia,pins = "ddc";
68 nvidia,function = "i2c2";
69 };
70 dta {
71 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
72 nvidia,function = "vi";
73 };
74 dtf {
75 nvidia,pins = "dtf";
76 nvidia,function = "i2c3";
77 };
78 gmc {
79 nvidia,pins = "gmc", "gmd";
80 nvidia,function = "sflash";
81 };
82 gpu {
83 nvidia,pins = "gpu";
84 nvidia,function = "uarta";
85 };
86 gpu7 {
87 nvidia,pins = "gpu7";
88 nvidia,function = "rtck";
89 };
90 gpv {
91 nvidia,pins = "gpv", "slxa", "slxk";
92 nvidia,function = "pcie";
93 };
94 hdint {
95 nvidia,pins = "hdint";
96 nvidia,function = "hdmi";
97 };
98 i2cp {
99 nvidia,pins = "i2cp";
100 nvidia,function = "i2cp";
101 };
102 irrx {
103 nvidia,pins = "irrx", "irtx";
104 nvidia,function = "uartb";
105 };
106 kbca {
107 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
108 "kbce", "kbcf";
109 nvidia,function = "kbc";
110 };
111 lcsn {
112 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
113 "ld3", "ld4", "ld5", "ld6", "ld7",
114 "ld8", "ld9", "ld10", "ld11", "ld12",
115 "ld13", "ld14", "ld15", "ld16", "ld17",
116 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
117 "lhs", "lm0", "lm1", "lpp", "lpw0",
118 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
119 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
120 "lvs";
121 nvidia,function = "displaya";
122 };
123 owc {
124 nvidia,pins = "owc", "uac";
125 nvidia,function = "rsvd2";
126 };
127 pmc {
128 nvidia,pins = "pmc";
129 nvidia,function = "pwr_on";
130 };
131 rm {
132 nvidia,pins = "rm";
133 nvidia,function = "i2c1";
134 };
135 sdb {
136 nvidia,pins = "sdb", "sdc", "sdd";
137 nvidia,function = "pwm";
138 };
139 sdio1 {
140 nvidia,pins = "sdio1";
141 nvidia,function = "sdio1";
142 };
143 slxc {
144 nvidia,pins = "slxc", "slxd";
145 nvidia,function = "sdio3";
146 };
147 spdi {
148 nvidia,pins = "spdi", "spdo";
149 nvidia,function = "spdif";
150 };
151 spia {
152 nvidia,pins = "spia", "spib", "spic";
153 nvidia,function = "spi2";
154 };
155 spid {
156 nvidia,pins = "spid", "spie", "spif";
157 nvidia,function = "spi1";
158 };
159 spig {
160 nvidia,pins = "spig", "spih";
161 nvidia,function = "spi2_alt";
162 };
163 uaa {
164 nvidia,pins = "uaa", "uab", "uda";
165 nvidia,function = "ulpi";
166 };
167 uad {
168 nvidia,pins = "uad";
169 nvidia,function = "irda";
170 };
171 uca {
172 nvidia,pins = "uca", "ucb";
173 nvidia,function = "uartc";
174 };
175 conf_ata {
176 nvidia,pins = "ata", "atc", "atd", "ate",
177 "crtp", "dap2", "dap3", "dap4", "dta",
178 "dtb", "dtc", "dtd", "dte", "gmb",
179 "gme", "i2cp", "pta", "slxc", "slxd",
180 "spdi", "spdo", "uda";
181 nvidia,pull = <0>;
182 nvidia,tristate = <1>;
183 };
184 conf_atb {
Stephen Warren563da212012-04-13 16:35:20 -0600185 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
186 "gma", "gmc", "gmd", "gpu", "gpu7",
187 "gpv", "sdio1", "slxa", "slxk", "uac";
Stephen Warrenecc295b2012-03-15 16:27:36 -0600188 nvidia,pull = <0>;
189 nvidia,tristate = <0>;
190 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600191 conf_ck32 {
192 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
193 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
194 nvidia,pull = <0>;
195 };
Stephen Warren563da212012-04-13 16:35:20 -0600196 conf_csus {
197 nvidia,pins = "csus", "spia", "spib",
198 "spid", "spif";
199 nvidia,pull = <1>;
200 nvidia,tristate = <1>;
201 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600202 conf_ddc {
203 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
204 nvidia,pull = <2>;
205 nvidia,tristate = <0>;
206 };
207 conf_hdint {
208 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
209 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
210 "lvp0", "pmc";
211 nvidia,tristate = <1>;
212 };
213 conf_irrx {
214 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
215 "kbcc", "kbcd", "kbce", "kbcf", "owc",
216 "spic", "spie", "spig", "spih", "uaa",
217 "uab", "uad", "uca", "ucb";
218 nvidia,pull = <2>;
219 nvidia,tristate = <1>;
220 };
221 conf_lc {
222 nvidia,pins = "lc", "ls";
223 nvidia,pull = <2>;
224 };
225 conf_ld0 {
226 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
227 "ld5", "ld6", "ld7", "ld8", "ld9",
228 "ld10", "ld11", "ld12", "ld13", "ld14",
229 "ld15", "ld16", "ld17", "ldi", "lhp0",
230 "lhp1", "lhp2", "lhs", "lm0", "lpp",
231 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
232 "lvs", "sdb";
233 nvidia,tristate = <0>;
234 };
235 conf_ld17_0 {
236 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
237 "ld23_22";
238 nvidia,pull = <1>;
239 };
240 };
241 };
242
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600243 i2s@70002800 {
244 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600245 };
246
247 serial@70006000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600248 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600249 clock-frequency = <216000000>;
250 };
251
Stephen Warrena7db2c12011-10-25 02:01:28 +0000252 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600253 status = "okay";
Stephen Warrena7db2c12011-10-25 02:01:28 +0000254 clock-frequency = <400000>;
255 };
256
257 i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600258 status = "okay";
Stephen Warrena7db2c12011-10-25 02:01:28 +0000259 clock-frequency = <400000>;
260 };
261
262 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600263 status = "okay";
Stephen Warrena7db2c12011-10-25 02:01:28 +0000264 clock-frequency = <400000>;
Stephen Warren081cc0a2012-04-27 09:22:44 -0600265
Stephen Warren22bfe102012-04-27 13:24:03 -0600266 codec: codec@1a {
267 compatible = "ti,tlv320aic23";
268 reg = <0x1a>;
269 };
270
Stephen Warren081cc0a2012-04-27 09:22:44 -0600271 rtc@56 {
272 compatible = "emmicro,em3027";
273 reg = <0x56>;
274 };
Stephen Warrena7db2c12011-10-25 02:01:28 +0000275 };
276
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600277 usb@c5000000 {
278 status = "okay";
Stephen Warren01ad8062012-07-25 14:02:44 -0600279 nvidia,vbus-gpio = <&gpio 170 0>; /* gpio PV2 */
Stephen Warren88950f3b2011-11-21 14:44:09 -0700280 };
281
Stephen Warrenc04abb32012-05-11 17:03:26 -0600282 usb@c5004000 {
283 nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
Stephen Warren31c1ec92011-11-21 14:44:10 -0700284 };
285
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600286 usb@c5008000 {
287 status = "okay";
Stephen Warren1292c122011-11-21 14:44:11 -0700288 };
289
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600290 sdhci@c8000000 {
291 status = "okay";
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200292 bus-width = <4>;
Stephen Warren1292c122011-11-21 14:44:11 -0700293 };
294
Stephen Warrena7db2c12011-10-25 02:01:28 +0000295 sdhci@c8000600 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600296 status = "okay";
Stephen Warrenc44e4382012-05-11 16:21:10 -0600297 cd-gpios = <&gpio 121 0>; /* gpio PP1 */
298 wp-gpios = <&gpio 122 0>; /* gpio PP2 */
Arnd Bergmanndeb88cc2012-05-14 22:35:04 +0200299 bus-width = <4>;
Stephen Warrena7db2c12011-10-25 02:01:28 +0000300 };
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600301
Stephen Warrenc04abb32012-05-11 17:03:26 -0600302 sound {
303 compatible = "nvidia,tegra-audio-trimslice";
304 nvidia,i2s-controller = <&tegra_i2s1>;
305 nvidia,audio-codec = <&codec>;
Stephen Warrenaa607eb2012-04-12 15:46:49 -0600306 };
Stephen Warrena7db2c12011-10-25 02:01:28 +0000307};