blob: 35c55505b3eb32e38536c2abbce86cfe523b6288 [file] [log] [blame]
Johannes Thumshirne264ebf2014-04-17 15:47:58 +02001/*
2 * MEN 16z135 High Speed UART
3 *
4 * Copyright (C) 2014 MEN Mikroelektronik GmbH (www.men.de)
5 * Author: Johannes Thumshirn <johannes.thumshirn@men.de>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; version 2 of the License.
10 */
11#define pr_fmt(fmt) KBUILD_MODNAME ":" fmt
12
13#include <linux/kernel.h>
14#include <linux/module.h>
15#include <linux/interrupt.h>
16#include <linux/serial_core.h>
17#include <linux/ioport.h>
18#include <linux/io.h>
19#include <linux/tty_flip.h>
20#include <linux/bitops.h>
21#include <linux/mcb.h>
22
23#define MEN_Z135_MAX_PORTS 12
24#define MEN_Z135_BASECLK 29491200
25#define MEN_Z135_FIFO_SIZE 1024
Johannes Thumshirne264ebf2014-04-17 15:47:58 +020026#define MEN_Z135_FIFO_WATERMARK 1020
27
28#define MEN_Z135_STAT_REG 0x0
29#define MEN_Z135_RX_RAM 0x4
30#define MEN_Z135_TX_RAM 0x400
31#define MEN_Z135_RX_CTRL 0x800
32#define MEN_Z135_TX_CTRL 0x804
33#define MEN_Z135_CONF_REG 0x808
34#define MEN_Z135_UART_FREQ 0x80c
35#define MEN_Z135_BAUD_REG 0x810
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +010036#define MEN_Z135_TIMEOUT 0x814
Johannes Thumshirne264ebf2014-04-17 15:47:58 +020037
38#define MEN_Z135_MEM_SIZE 0x818
39
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +010040#define IRQ_ID(x) ((x) & 0x1f)
Johannes Thumshirne264ebf2014-04-17 15:47:58 +020041
Johannes Thumshirn10389e62014-05-12 10:34:59 +020042#define MEN_Z135_IER_RXCIEN BIT(0) /* RX Space IRQ */
43#define MEN_Z135_IER_TXCIEN BIT(1) /* TX Space IRQ */
Johannes Thumshirne264ebf2014-04-17 15:47:58 +020044#define MEN_Z135_IER_RLSIEN BIT(2) /* Receiver Line Status IRQ */
45#define MEN_Z135_IER_MSIEN BIT(3) /* Modem Status IRQ */
46#define MEN_Z135_ALL_IRQS (MEN_Z135_IER_RXCIEN \
47 | MEN_Z135_IER_RLSIEN \
48 | MEN_Z135_IER_MSIEN \
49 | MEN_Z135_IER_TXCIEN)
50
51#define MEN_Z135_MCR_DTR BIT(24)
52#define MEN_Z135_MCR_RTS BIT(25)
53#define MEN_Z135_MCR_OUT1 BIT(26)
54#define MEN_Z135_MCR_OUT2 BIT(27)
55#define MEN_Z135_MCR_LOOP BIT(28)
56#define MEN_Z135_MCR_RCFC BIT(29)
57
58#define MEN_Z135_MSR_DCTS BIT(0)
59#define MEN_Z135_MSR_DDSR BIT(1)
60#define MEN_Z135_MSR_DRI BIT(2)
61#define MEN_Z135_MSR_DDCD BIT(3)
62#define MEN_Z135_MSR_CTS BIT(4)
63#define MEN_Z135_MSR_DSR BIT(5)
64#define MEN_Z135_MSR_RI BIT(6)
65#define MEN_Z135_MSR_DCD BIT(7)
66
67#define MEN_Z135_LCR_SHIFT 8 /* LCR shift mask */
68
69#define MEN_Z135_WL5 0 /* CS5 */
70#define MEN_Z135_WL6 1 /* CS6 */
71#define MEN_Z135_WL7 2 /* CS7 */
72#define MEN_Z135_WL8 3 /* CS8 */
73
74#define MEN_Z135_STB_SHIFT 2 /* Stopbits */
75#define MEN_Z135_NSTB1 0
76#define MEN_Z135_NSTB2 1
77
78#define MEN_Z135_PEN_SHIFT 3 /* Parity enable */
79#define MEN_Z135_PAR_DIS 0
80#define MEN_Z135_PAR_ENA 1
81
82#define MEN_Z135_PTY_SHIFT 4 /* Parity type */
83#define MEN_Z135_PTY_ODD 0
84#define MEN_Z135_PTY_EVN 1
85
86#define MEN_Z135_LSR_DR BIT(0)
87#define MEN_Z135_LSR_OE BIT(1)
88#define MEN_Z135_LSR_PE BIT(2)
89#define MEN_Z135_LSR_FE BIT(3)
90#define MEN_Z135_LSR_BI BIT(4)
91#define MEN_Z135_LSR_THEP BIT(5)
92#define MEN_Z135_LSR_TEXP BIT(6)
93#define MEN_Z135_LSR_RXFIFOERR BIT(7)
94
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +010095#define MEN_Z135_IRQ_ID_RLS BIT(0)
96#define MEN_Z135_IRQ_ID_RDA BIT(1)
97#define MEN_Z135_IRQ_ID_CTI BIT(2)
98#define MEN_Z135_IRQ_ID_TSA BIT(3)
99#define MEN_Z135_IRQ_ID_MST BIT(4)
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200100
101#define LCR(x) (((x) >> MEN_Z135_LCR_SHIFT) & 0xff)
102
103#define BYTES_TO_ALIGN(x) ((x) & 0x3)
104
105static int line;
106
107static int txlvl = 5;
108module_param(txlvl, int, S_IRUGO);
109MODULE_PARM_DESC(txlvl, "TX IRQ trigger level 0-7, default 5 (128 byte)");
110
111static int rxlvl = 6;
112module_param(rxlvl, int, S_IRUGO);
113MODULE_PARM_DESC(rxlvl, "RX IRQ trigger level 0-7, default 6 (256 byte)");
114
115static int align;
116module_param(align, int, S_IRUGO);
117MODULE_PARM_DESC(align, "Keep hardware FIFO write pointer aligned, default 0");
118
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100119static uint rx_timeout;
120module_param(rx_timeout, uint, S_IRUGO);
121MODULE_PARM_DESC(rx_timeout, "RX timeout. "
122 "Timeout in seconds = (timeout_reg * baud_reg * 4) / freq_reg");
123
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200124struct men_z135_port {
125 struct uart_port port;
126 struct mcb_device *mdev;
127 unsigned char *rxbuf;
128 u32 stat_reg;
129 spinlock_t lock;
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100130 bool automode;
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200131};
132#define to_men_z135(port) container_of((port), struct men_z135_port, port)
133
134/**
135 * men_z135_reg_set() - Set value in register
136 * @uart: The UART port
137 * @addr: Register address
138 * @val: value to set
139 */
140static inline void men_z135_reg_set(struct men_z135_port *uart,
141 u32 addr, u32 val)
142{
143 struct uart_port *port = &uart->port;
144 unsigned long flags;
145 u32 reg;
146
147 spin_lock_irqsave(&uart->lock, flags);
148
149 reg = ioread32(port->membase + addr);
150 reg |= val;
151 iowrite32(reg, port->membase + addr);
152
153 spin_unlock_irqrestore(&uart->lock, flags);
154}
155
156/**
157 * men_z135_reg_clr() - Unset value in register
158 * @uart: The UART port
159 * @addr: Register address
160 * @val: value to clear
161 */
162static inline void men_z135_reg_clr(struct men_z135_port *uart,
163 u32 addr, u32 val)
164{
165 struct uart_port *port = &uart->port;
166 unsigned long flags;
167 u32 reg;
168
169 spin_lock_irqsave(&uart->lock, flags);
170
171 reg = ioread32(port->membase + addr);
172 reg &= ~val;
173 iowrite32(reg, port->membase + addr);
174
175 spin_unlock_irqrestore(&uart->lock, flags);
176}
177
178/**
179 * men_z135_handle_modem_status() - Handle change of modem status
180 * @port: The UART port
181 *
182 * Handle change of modem status register. This is done by reading the "delta"
183 * versions of DCD (Data Carrier Detect) and CTS (Clear To Send).
184 */
185static void men_z135_handle_modem_status(struct men_z135_port *uart)
186{
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100187 u8 msr;
188
189 msr = (uart->stat_reg >> 8) & 0xff;
190
191 if (msr & MEN_Z135_MSR_DDCD)
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200192 uart_handle_dcd_change(&uart->port,
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100193 msr & MEN_Z135_MSR_DCD);
194 if (msr & MEN_Z135_MSR_DCTS)
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200195 uart_handle_cts_change(&uart->port,
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100196 msr & MEN_Z135_MSR_CTS);
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200197}
198
199static void men_z135_handle_lsr(struct men_z135_port *uart)
200{
201 struct uart_port *port = &uart->port;
202 u8 lsr;
203
204 lsr = (uart->stat_reg >> 16) & 0xff;
205
206 if (lsr & MEN_Z135_LSR_OE)
207 port->icount.overrun++;
208 if (lsr & MEN_Z135_LSR_PE)
209 port->icount.parity++;
210 if (lsr & MEN_Z135_LSR_FE)
211 port->icount.frame++;
212 if (lsr & MEN_Z135_LSR_BI) {
213 port->icount.brk++;
214 uart_handle_break(port);
215 }
216}
217
218/**
219 * get_rx_fifo_content() - Get the number of bytes in RX FIFO
220 * @uart: The UART port
221 *
222 * Read RXC register from hardware and return current FIFO fill size.
223 */
224static u16 get_rx_fifo_content(struct men_z135_port *uart)
225{
226 struct uart_port *port = &uart->port;
227 u32 stat_reg;
228 u16 rxc;
229 u8 rxc_lo;
230 u8 rxc_hi;
231
232 stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG);
233 rxc_lo = stat_reg >> 24;
234 rxc_hi = (stat_reg & 0xC0) >> 6;
235
236 rxc = rxc_lo | (rxc_hi << 8);
237
238 return rxc;
239}
240
241/**
242 * men_z135_handle_rx() - RX tasklet routine
243 * @arg: Pointer to struct men_z135_port
244 *
245 * Copy from RX FIFO and acknowledge number of bytes copied.
246 */
247static void men_z135_handle_rx(struct men_z135_port *uart)
248{
249 struct uart_port *port = &uart->port;
250 struct tty_port *tport = &port->state->port;
251 int copied;
252 u16 size;
253 int room;
254
255 size = get_rx_fifo_content(uart);
256
257 if (size == 0)
258 return;
259
260 /* Avoid accidently accessing TX FIFO instead of RX FIFO. Last
261 * longword in RX FIFO cannot be read.(0x004-0x3FF)
262 */
263 if (size > MEN_Z135_FIFO_WATERMARK)
264 size = MEN_Z135_FIFO_WATERMARK;
265
266 room = tty_buffer_request_room(tport, size);
267 if (room != size)
268 dev_warn(&uart->mdev->dev,
269 "Not enough room in flip buffer, truncating to %d\n",
270 room);
271
272 if (room == 0)
273 return;
274
275 memcpy_fromio(uart->rxbuf, port->membase + MEN_Z135_RX_RAM, room);
276 /* Be sure to first copy all data and then acknowledge it */
277 mb();
278 iowrite32(room, port->membase + MEN_Z135_RX_CTRL);
279
280 copied = tty_insert_flip_string(tport, uart->rxbuf, room);
281 if (copied != room)
282 dev_warn(&uart->mdev->dev,
283 "Only copied %d instead of %d bytes\n",
284 copied, room);
285
286 port->icount.rx += copied;
287
288 tty_flip_buffer_push(tport);
289
290}
291
292/**
293 * men_z135_handle_tx() - TX tasklet routine
294 * @arg: Pointer to struct men_z135_port
295 *
296 */
297static void men_z135_handle_tx(struct men_z135_port *uart)
298{
299 struct uart_port *port = &uart->port;
300 struct circ_buf *xmit = &port->state->xmit;
301 u32 txc;
302 u32 wptr;
303 int qlen;
304 int n;
305 int txfree;
306 int head;
307 int tail;
308 int s;
309
310 if (uart_circ_empty(xmit))
311 goto out;
312
313 if (uart_tx_stopped(port))
314 goto out;
315
316 if (port->x_char)
317 goto out;
318
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200319 /* calculate bytes to copy */
320 qlen = uart_circ_chars_pending(xmit);
321 if (qlen <= 0)
322 goto out;
323
324 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
325 txc = (wptr >> 16) & 0x3ff;
326 wptr &= 0x3ff;
327
328 if (txc > MEN_Z135_FIFO_WATERMARK)
329 txc = MEN_Z135_FIFO_WATERMARK;
330
331 txfree = MEN_Z135_FIFO_WATERMARK - txc;
332 if (txfree <= 0) {
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100333 dev_err(&uart->mdev->dev,
334 "Not enough room in TX FIFO have %d, need %d\n",
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200335 txfree, qlen);
336 goto irq_en;
337 }
338
339 /* if we're not aligned, it's better to copy only 1 or 2 bytes and
340 * then the rest.
341 */
342 if (align && qlen >= 3 && BYTES_TO_ALIGN(wptr))
343 n = 4 - BYTES_TO_ALIGN(wptr);
344 else if (qlen > txfree)
345 n = txfree;
346 else
347 n = qlen;
348
349 if (n <= 0)
350 goto irq_en;
351
352 head = xmit->head & (UART_XMIT_SIZE - 1);
353 tail = xmit->tail & (UART_XMIT_SIZE - 1);
354
355 s = ((head >= tail) ? head : UART_XMIT_SIZE) - tail;
356 n = min(n, s);
357
358 memcpy_toio(port->membase + MEN_Z135_TX_RAM, &xmit->buf[xmit->tail], n);
359 xmit->tail = (xmit->tail + n) & (UART_XMIT_SIZE - 1);
360 mmiowb();
361
362 iowrite32(n & 0x3ff, port->membase + MEN_Z135_TX_CTRL);
363
364 port->icount.tx += n;
365
Johannes Thumshirna9977622014-06-16 07:33:38 +0200366 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
367 uart_write_wakeup(port);
368
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200369irq_en:
370 if (!uart_circ_empty(xmit))
371 men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
372 else
373 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
374
375out:
376 return;
377
378}
379
380/**
381 * men_z135_intr() - Handle legacy IRQs
382 * @irq: The IRQ number
383 * @data: Pointer to UART port
384 *
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100385 * Check IIR register to find the cause of the interrupt and handle it.
386 * It is possible that multiple interrupts reason bits are set and reading
387 * the IIR is a destructive read, so we always need to check for all possible
388 * interrupts and handle them.
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200389 */
390static irqreturn_t men_z135_intr(int irq, void *data)
391{
392 struct men_z135_port *uart = (struct men_z135_port *)data;
393 struct uart_port *port = &uart->port;
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100394 bool handled = false;
395 unsigned long flags;
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200396 int irq_id;
397
398 uart->stat_reg = ioread32(port->membase + MEN_Z135_STAT_REG);
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200399 irq_id = IRQ_ID(uart->stat_reg);
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100400
401 if (!irq_id)
402 goto out;
403
404 spin_lock_irqsave(&port->lock, flags);
405 /* It's save to write to IIR[7:6] RXC[9:8] */
406 iowrite8(irq_id, port->membase + MEN_Z135_STAT_REG);
407
408 if (irq_id & MEN_Z135_IRQ_ID_RLS) {
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200409 men_z135_handle_lsr(uart);
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100410 handled = true;
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200411 }
412
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100413 if (irq_id & (MEN_Z135_IRQ_ID_RDA | MEN_Z135_IRQ_ID_CTI)) {
414 if (irq_id & MEN_Z135_IRQ_ID_CTI)
415 dev_dbg(&uart->mdev->dev, "Character Timeout Indication\n");
416 men_z135_handle_rx(uart);
417 handled = true;
418 }
419
420 if (irq_id & MEN_Z135_IRQ_ID_TSA) {
421 men_z135_handle_tx(uart);
422 handled = true;
423 }
424
425 if (irq_id & MEN_Z135_IRQ_ID_MST) {
426 men_z135_handle_modem_status(uart);
427 handled = true;
428 }
429
430 spin_unlock_irqrestore(&port->lock, flags);
431out:
432 return IRQ_RETVAL(handled);
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200433}
434
435/**
436 * men_z135_request_irq() - Request IRQ for 16z135 core
437 * @uart: z135 private uart port structure
438 *
439 * Request an IRQ for 16z135 to use. First try using MSI, if it fails
440 * fall back to using legacy interrupts.
441 */
442static int men_z135_request_irq(struct men_z135_port *uart)
443{
444 struct device *dev = &uart->mdev->dev;
445 struct uart_port *port = &uart->port;
446 int err = 0;
447
448 err = request_irq(port->irq, men_z135_intr, IRQF_SHARED,
449 "men_z135_intr", uart);
450 if (err)
451 dev_err(dev, "Error %d getting interrupt\n", err);
452
453 return err;
454}
455
456/**
457 * men_z135_tx_empty() - Handle tx_empty call
458 * @port: The UART port
459 *
460 * This function tests whether the TX FIFO and shifter for the port
461 * described by @port is empty.
462 */
463static unsigned int men_z135_tx_empty(struct uart_port *port)
464{
465 u32 wptr;
466 u16 txc;
467
468 wptr = ioread32(port->membase + MEN_Z135_TX_CTRL);
469 txc = (wptr >> 16) & 0x3ff;
470
471 if (txc == 0)
472 return TIOCSER_TEMT;
473 else
474 return 0;
475}
476
477/**
478 * men_z135_set_mctrl() - Set modem control lines
479 * @port: The UART port
480 * @mctrl: The modem control lines
481 *
482 * This function sets the modem control lines for a port described by @port
483 * to the state described by @mctrl
484 */
485static void men_z135_set_mctrl(struct uart_port *port, unsigned int mctrl)
486{
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100487 u32 old;
488 u32 conf_reg;
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200489
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100490 conf_reg = old = ioread32(port->membase + MEN_Z135_CONF_REG);
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200491 if (mctrl & TIOCM_RTS)
492 conf_reg |= MEN_Z135_MCR_RTS;
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100493 else
494 conf_reg &= ~MEN_Z135_MCR_RTS;
495
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200496 if (mctrl & TIOCM_DTR)
497 conf_reg |= MEN_Z135_MCR_DTR;
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100498 else
499 conf_reg &= ~MEN_Z135_MCR_DTR;
500
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200501 if (mctrl & TIOCM_OUT1)
502 conf_reg |= MEN_Z135_MCR_OUT1;
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100503 else
504 conf_reg &= ~MEN_Z135_MCR_OUT1;
505
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200506 if (mctrl & TIOCM_OUT2)
507 conf_reg |= MEN_Z135_MCR_OUT2;
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100508 else
509 conf_reg &= ~MEN_Z135_MCR_OUT2;
510
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200511 if (mctrl & TIOCM_LOOP)
512 conf_reg |= MEN_Z135_MCR_LOOP;
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100513 else
514 conf_reg &= ~MEN_Z135_MCR_LOOP;
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200515
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100516 if (conf_reg != old)
517 iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200518}
519
520/**
521 * men_z135_get_mctrl() - Get modem control lines
522 * @port: The UART port
523 *
524 * Retruns the current state of modem control inputs.
525 */
526static unsigned int men_z135_get_mctrl(struct uart_port *port)
527{
528 unsigned int mctrl = 0;
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200529 u8 msr;
530
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100531 msr = ioread8(port->membase + MEN_Z135_STAT_REG + 1);
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200532
533 if (msr & MEN_Z135_MSR_CTS)
534 mctrl |= TIOCM_CTS;
535 if (msr & MEN_Z135_MSR_DSR)
536 mctrl |= TIOCM_DSR;
537 if (msr & MEN_Z135_MSR_RI)
538 mctrl |= TIOCM_RI;
539 if (msr & MEN_Z135_MSR_DCD)
540 mctrl |= TIOCM_CAR;
541
542 return mctrl;
543}
544
545/**
546 * men_z135_stop_tx() - Stop transmitting characters
547 * @port: The UART port
548 *
549 * Stop transmitting characters. This might be due to CTS line becomming
550 * inactive or the tty layer indicating we want to stop transmission due to
551 * an XOFF character.
552 */
553static void men_z135_stop_tx(struct uart_port *port)
554{
555 struct men_z135_port *uart = to_men_z135(port);
556
557 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_TXCIEN);
558}
559
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100560/*
561 * men_z135_disable_ms() - Disable Modem Status
562 * port: The UART port
563 *
564 * Enable Modem Status IRQ.
565 */
566static void men_z135_disable_ms(struct uart_port *port)
567{
568 struct men_z135_port *uart = to_men_z135(port);
569
570 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN);
571}
572
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200573/**
574 * men_z135_start_tx() - Start transmitting characters
575 * @port: The UART port
576 *
577 * Start transmitting character. This actually doesn't transmit anything, but
578 * fires off the TX tasklet.
579 */
580static void men_z135_start_tx(struct uart_port *port)
581{
582 struct men_z135_port *uart = to_men_z135(port);
583
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100584 if (uart->automode)
585 men_z135_disable_ms(port);
586
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200587 men_z135_handle_tx(uart);
588}
589
590/**
591 * men_z135_stop_rx() - Stop receiving characters
592 * @port: The UART port
593 *
594 * Stop receiving characters; the port is in the process of being closed.
595 */
596static void men_z135_stop_rx(struct uart_port *port)
597{
598 struct men_z135_port *uart = to_men_z135(port);
599
600 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_RXCIEN);
601}
602
603/**
604 * men_z135_enable_ms() - Enable Modem Status
605 * port:
606 *
607 * Enable Modem Status IRQ.
608 */
609static void men_z135_enable_ms(struct uart_port *port)
610{
611 struct men_z135_port *uart = to_men_z135(port);
612
613 men_z135_reg_set(uart, MEN_Z135_CONF_REG, MEN_Z135_IER_MSIEN);
614}
615
616static int men_z135_startup(struct uart_port *port)
617{
618 struct men_z135_port *uart = to_men_z135(port);
619 int err;
620 u32 conf_reg = 0;
621
622 err = men_z135_request_irq(uart);
623 if (err)
624 return -ENODEV;
625
626 conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG);
627
Johannes Thumshirn10389e62014-05-12 10:34:59 +0200628 /* Activate all but TX space available IRQ */
629 conf_reg |= MEN_Z135_ALL_IRQS & ~MEN_Z135_IER_TXCIEN;
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200630 conf_reg &= ~(0xff << 16);
631 conf_reg |= (txlvl << 16);
632 conf_reg |= (rxlvl << 20);
633
634 iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
635
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100636 if (rx_timeout)
637 iowrite32(rx_timeout, port->membase + MEN_Z135_TIMEOUT);
638
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200639 return 0;
640}
641
642static void men_z135_shutdown(struct uart_port *port)
643{
644 struct men_z135_port *uart = to_men_z135(port);
645 u32 conf_reg = 0;
646
647 conf_reg |= MEN_Z135_ALL_IRQS;
648
649 men_z135_reg_clr(uart, MEN_Z135_CONF_REG, conf_reg);
650
651 free_irq(uart->port.irq, uart);
652}
653
654static void men_z135_set_termios(struct uart_port *port,
655 struct ktermios *termios,
656 struct ktermios *old)
657{
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100658 struct men_z135_port *uart = to_men_z135(port);
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200659 unsigned int baud;
660 u32 conf_reg;
661 u32 bd_reg;
662 u32 uart_freq;
663 u8 lcr;
664
665 conf_reg = ioread32(port->membase + MEN_Z135_CONF_REG);
666 lcr = LCR(conf_reg);
667
668 /* byte size */
669 switch (termios->c_cflag & CSIZE) {
670 case CS5:
671 lcr |= MEN_Z135_WL5;
672 break;
673 case CS6:
674 lcr |= MEN_Z135_WL6;
675 break;
676 case CS7:
677 lcr |= MEN_Z135_WL7;
678 break;
679 case CS8:
680 lcr |= MEN_Z135_WL8;
681 break;
682 }
683
684 /* stop bits */
685 if (termios->c_cflag & CSTOPB)
686 lcr |= MEN_Z135_NSTB2 << MEN_Z135_STB_SHIFT;
687
688 /* parity */
689 if (termios->c_cflag & PARENB) {
690 lcr |= MEN_Z135_PAR_ENA << MEN_Z135_PEN_SHIFT;
691
692 if (termios->c_cflag & PARODD)
693 lcr |= MEN_Z135_PTY_ODD << MEN_Z135_PTY_SHIFT;
694 else
695 lcr |= MEN_Z135_PTY_EVN << MEN_Z135_PTY_SHIFT;
696 } else
697 lcr |= MEN_Z135_PAR_DIS << MEN_Z135_PEN_SHIFT;
698
Johannes Thumshirn01ba8d62015-01-19 07:44:41 +0100699 conf_reg |= MEN_Z135_IER_MSIEN;
700 if (termios->c_cflag & CRTSCTS) {
701 conf_reg |= MEN_Z135_MCR_RCFC;
702 uart->automode = true;
703 termios->c_cflag &= ~CLOCAL;
704 } else {
705 conf_reg &= ~MEN_Z135_MCR_RCFC;
706 uart->automode = false;
707 }
708
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200709 termios->c_cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
710
711 conf_reg |= lcr << MEN_Z135_LCR_SHIFT;
712 iowrite32(conf_reg, port->membase + MEN_Z135_CONF_REG);
713
714 uart_freq = ioread32(port->membase + MEN_Z135_UART_FREQ);
715 if (uart_freq == 0)
716 uart_freq = MEN_Z135_BASECLK;
717
718 baud = uart_get_baud_rate(port, termios, old, 0, uart_freq / 16);
719
720 spin_lock(&port->lock);
721 if (tty_termios_baud_rate(termios))
722 tty_termios_encode_baud_rate(termios, baud, baud);
723
724 bd_reg = uart_freq / (4 * baud);
725 iowrite32(bd_reg, port->membase + MEN_Z135_BAUD_REG);
726
727 uart_update_timeout(port, termios->c_cflag, baud);
728 spin_unlock(&port->lock);
729}
730
731static const char *men_z135_type(struct uart_port *port)
732{
733 return KBUILD_MODNAME;
734}
735
736static void men_z135_release_port(struct uart_port *port)
737{
738 iounmap(port->membase);
739 port->membase = NULL;
740
741 release_mem_region(port->mapbase, MEN_Z135_MEM_SIZE);
742}
743
744static int men_z135_request_port(struct uart_port *port)
745{
746 int size = MEN_Z135_MEM_SIZE;
747
748 if (!request_mem_region(port->mapbase, size, "men_z135_port"))
749 return -EBUSY;
750
751 port->membase = ioremap(port->mapbase, MEN_Z135_MEM_SIZE);
752 if (port->membase == NULL) {
753 release_mem_region(port->mapbase, MEN_Z135_MEM_SIZE);
754 return -ENOMEM;
755 }
756
757 return 0;
758}
759
760static void men_z135_config_port(struct uart_port *port, int type)
761{
762 port->type = PORT_MEN_Z135;
763 men_z135_request_port(port);
764}
765
766static int men_z135_verify_port(struct uart_port *port,
767 struct serial_struct *serinfo)
768{
769 return -EINVAL;
770}
771
772static struct uart_ops men_z135_ops = {
773 .tx_empty = men_z135_tx_empty,
774 .set_mctrl = men_z135_set_mctrl,
775 .get_mctrl = men_z135_get_mctrl,
776 .stop_tx = men_z135_stop_tx,
777 .start_tx = men_z135_start_tx,
778 .stop_rx = men_z135_stop_rx,
779 .enable_ms = men_z135_enable_ms,
780 .startup = men_z135_startup,
781 .shutdown = men_z135_shutdown,
782 .set_termios = men_z135_set_termios,
783 .type = men_z135_type,
784 .release_port = men_z135_release_port,
785 .request_port = men_z135_request_port,
786 .config_port = men_z135_config_port,
787 .verify_port = men_z135_verify_port,
788};
789
790static struct uart_driver men_z135_driver = {
791 .owner = THIS_MODULE,
792 .driver_name = KBUILD_MODNAME,
793 .dev_name = "ttyHSU",
794 .major = 0,
795 .minor = 0,
796 .nr = MEN_Z135_MAX_PORTS,
797};
798
799/**
800 * men_z135_probe() - Probe a z135 instance
801 * @mdev: The MCB device
802 * @id: The MCB device ID
803 *
804 * men_z135_probe does the basic setup of hardware resources and registers the
805 * new uart port to the tty layer.
806 */
807static int men_z135_probe(struct mcb_device *mdev,
808 const struct mcb_device_id *id)
809{
810 struct men_z135_port *uart;
811 struct resource *mem;
812 struct device *dev;
813 int err;
814
815 dev = &mdev->dev;
816
817 uart = devm_kzalloc(dev, sizeof(struct men_z135_port), GFP_KERNEL);
818 if (!uart)
819 return -ENOMEM;
820
821 uart->rxbuf = (unsigned char *)__get_free_page(GFP_KERNEL);
822 if (!uart->rxbuf)
823 return -ENOMEM;
824
825 mem = &mdev->mem;
826
827 mcb_set_drvdata(mdev, uart);
828
829 uart->port.uartclk = MEN_Z135_BASECLK * 16;
830 uart->port.fifosize = MEN_Z135_FIFO_SIZE;
831 uart->port.iotype = UPIO_MEM;
832 uart->port.ops = &men_z135_ops;
833 uart->port.irq = mcb_get_irq(mdev);
834 uart->port.iotype = UPIO_MEM;
835 uart->port.flags = UPF_BOOT_AUTOCONF | UPF_IOREMAP;
836 uart->port.line = line++;
837 uart->port.dev = dev;
838 uart->port.type = PORT_MEN_Z135;
839 uart->port.mapbase = mem->start;
840 uart->port.membase = NULL;
841 uart->mdev = mdev;
842
843 spin_lock_init(&uart->port.lock);
844 spin_lock_init(&uart->lock);
845
846 err = uart_add_one_port(&men_z135_driver, &uart->port);
847 if (err)
848 goto err;
849
850 return 0;
851
852err:
853 free_page((unsigned long) uart->rxbuf);
854 dev_err(dev, "Failed to add UART: %d\n", err);
855
856 return err;
857}
858
859/**
860 * men_z135_remove() - Remove a z135 instance from the system
861 *
862 * @mdev: The MCB device
863 */
864static void men_z135_remove(struct mcb_device *mdev)
865{
866 struct men_z135_port *uart = mcb_get_drvdata(mdev);
867
868 line--;
869 uart_remove_one_port(&men_z135_driver, &uart->port);
870 free_page((unsigned long) uart->rxbuf);
871}
872
873static const struct mcb_device_id men_z135_ids[] = {
874 { .device = 0x87 },
Axel Lin6b1f40c2014-11-10 16:05:03 +0800875 { }
Johannes Thumshirne264ebf2014-04-17 15:47:58 +0200876};
877MODULE_DEVICE_TABLE(mcb, men_z135_ids);
878
879static struct mcb_driver mcb_driver = {
880 .driver = {
881 .name = "z135-uart",
882 .owner = THIS_MODULE,
883 },
884 .probe = men_z135_probe,
885 .remove = men_z135_remove,
886 .id_table = men_z135_ids,
887};
888
889/**
890 * men_z135_init() - Driver Registration Routine
891 *
892 * men_z135_init is the first routine called when the driver is loaded. All it
893 * does is register with the legacy MEN Chameleon subsystem.
894 */
895static int __init men_z135_init(void)
896{
897 int err;
898
899 err = uart_register_driver(&men_z135_driver);
900 if (err) {
901 pr_err("Failed to register UART: %d\n", err);
902 return err;
903 }
904
905 err = mcb_register_driver(&mcb_driver);
906 if (err) {
907 pr_err("Failed to register MCB driver: %d\n", err);
908 uart_unregister_driver(&men_z135_driver);
909 return err;
910 }
911
912 return 0;
913}
914module_init(men_z135_init);
915
916/**
917 * men_z135_exit() - Driver Exit Routine
918 *
919 * men_z135_exit is called just before the driver is removed from memory.
920 */
921static void __exit men_z135_exit(void)
922{
923 mcb_unregister_driver(&mcb_driver);
924 uart_unregister_driver(&men_z135_driver);
925}
926module_exit(men_z135_exit);
927
928MODULE_AUTHOR("Johannes Thumshirn <johannes.thumshirn@men.de>");
929MODULE_LICENSE("GPL v2");
930MODULE_DESCRIPTION("MEN 16z135 High Speed UART");
931MODULE_ALIAS("mcb:16z135");