blob: be0f05efac6d1c93a87628b37d1a3d62afc9ad4e [file] [log] [blame]
Jeff Garzik669a5db2006-08-29 18:12:40 -04001/*
2 * pata_hpt3x3 - HPT3x3 driver
3 * (c) Copyright 2005-2006 Red Hat
4 *
5 * Was pata_hpt34x but the naming was confusing as it supported the
6 * 343 and 363 so it has been renamed.
7 *
8 * Based on:
9 * linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002
10 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
11 *
12 * May be copied or modified under the terms of the GNU General Public
13 * License
14 */
Jeff Garzik85cd7252006-08-31 00:03:49 -040015
Jeff Garzik669a5db2006-08-29 18:12:40 -040016#include <linux/kernel.h>
17#include <linux/module.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/blkdev.h>
21#include <linux/delay.h>
22#include <scsi/scsi_host.h>
23#include <linux/libata.h>
24
25#define DRV_NAME "pata_hpt3x3"
Alan Cox66e7da42007-07-09 11:46:22 -070026#define DRV_VERSION "0.5.3"
Jeff Garzik669a5db2006-08-29 18:12:40 -040027
Jeff Garzik669a5db2006-08-29 18:12:40 -040028/**
29 * hpt3x3_set_piomode - PIO setup
30 * @ap: ATA interface
31 * @adev: device on the interface
32 *
33 * Set our PIO requirements. This is fairly simple on the HPT3x3 as
34 * all we have to do is clear the MWDMA and UDMA bits then load the
35 * mode number.
36 */
37
38static void hpt3x3_set_piomode(struct ata_port *ap, struct ata_device *adev)
39{
40 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
41 u32 r1, r2;
42 int dn = 2 * ap->port_no + adev->devno;
43
44 pci_read_config_dword(pdev, 0x44, &r1);
45 pci_read_config_dword(pdev, 0x48, &r2);
46 /* Load the PIO timing number */
47 r1 &= ~(7 << (3 * dn));
48 r1 |= (adev->pio_mode - XFER_PIO_0) << (3 * dn);
49 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
50
51 pci_write_config_dword(pdev, 0x44, r1);
52 pci_write_config_dword(pdev, 0x48, r2);
53}
54
Jeff Garzik790956e2007-07-10 21:36:13 -040055#if defined(CONFIG_PATA_HPT3X3_DMA)
Jeff Garzik669a5db2006-08-29 18:12:40 -040056/**
57 * hpt3x3_set_dmamode - DMA timing setup
58 * @ap: ATA interface
59 * @adev: Device being configured
60 *
61 * Set up the channel for MWDMA or UDMA modes. Much the same as with
62 * PIO, load the mode number and then set MWDMA or UDMA flag.
Alan Cox66e7da42007-07-09 11:46:22 -070063 *
64 * 0x44 : bit 0-2 master mode, 3-5 slave mode, etc
65 * 0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
Jeff Garzik669a5db2006-08-29 18:12:40 -040066 */
67
68static void hpt3x3_set_dmamode(struct ata_port *ap, struct ata_device *adev)
69{
70 struct pci_dev *pdev = to_pci_dev(ap->host->dev);
71 u32 r1, r2;
72 int dn = 2 * ap->port_no + adev->devno;
73 int mode_num = adev->dma_mode & 0x0F;
74
75 pci_read_config_dword(pdev, 0x44, &r1);
76 pci_read_config_dword(pdev, 0x48, &r2);
77 /* Load the timing number */
78 r1 &= ~(7 << (3 * dn));
79 r1 |= (mode_num << (3 * dn));
80 r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
81
82 if (adev->dma_mode >= XFER_UDMA_0)
Alan Cox66e7da42007-07-09 11:46:22 -070083 r2 |= (0x10 << dn); /* Ultra mode */
Jeff Garzik669a5db2006-08-29 18:12:40 -040084 else
Alan Cox66e7da42007-07-09 11:46:22 -070085 r2 |= (0x01 << dn); /* MWDMA */
Jeff Garzik669a5db2006-08-29 18:12:40 -040086
87 pci_write_config_dword(pdev, 0x44, r1);
88 pci_write_config_dword(pdev, 0x48, r2);
89}
Jeff Garzik790956e2007-07-10 21:36:13 -040090#endif /* CONFIG_PATA_HPT3X3_DMA */
Jeff Garzik669a5db2006-08-29 18:12:40 -040091
Alan Cox66e7da42007-07-09 11:46:22 -070092/**
93 * hpt3x3_atapi_dma - ATAPI DMA check
94 * @qc: Queued command
95 *
96 * Just say no - we don't do ATAPI DMA
97 */
98
99static int hpt3x3_atapi_dma(struct ata_queued_cmd *qc)
100{
101 return 1;
102}
103
Jeff Garzik669a5db2006-08-29 18:12:40 -0400104static struct scsi_host_template hpt3x3_sht = {
105 .module = THIS_MODULE,
106 .name = DRV_NAME,
107 .ioctl = ata_scsi_ioctl,
108 .queuecommand = ata_scsi_queuecmd,
109 .can_queue = ATA_DEF_QUEUE,
110 .this_id = ATA_SHT_THIS_ID,
111 .sg_tablesize = LIBATA_MAX_PRD,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400112 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
113 .emulated = ATA_SHT_EMULATED,
114 .use_clustering = ATA_SHT_USE_CLUSTERING,
115 .proc_name = DRV_NAME,
116 .dma_boundary = ATA_DMA_BOUNDARY,
117 .slave_configure = ata_scsi_slave_config,
Tejun Heoafdfe892006-11-29 11:26:47 +0900118 .slave_destroy = ata_scsi_slave_destroy,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400119 .bios_param = ata_std_bios_param,
120};
121
122static struct ata_port_operations hpt3x3_port_ops = {
123 .port_disable = ata_port_disable,
124 .set_piomode = hpt3x3_set_piomode,
Jeff Garzik790956e2007-07-10 21:36:13 -0400125#if defined(CONFIG_PATA_HPT3X3_DMA)
126 .set_dmamode = hpt3x3_set_dmamode,
127#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400128 .mode_filter = ata_pci_default_filter,
129
130 .tf_load = ata_tf_load,
131 .tf_read = ata_tf_read,
132 .check_status = ata_check_status,
133 .exec_command = ata_exec_command,
134 .dev_select = ata_std_dev_select,
135
136 .freeze = ata_bmdma_freeze,
137 .thaw = ata_bmdma_thaw,
Jeff Garzika73984a2007-03-09 08:37:46 -0500138 .error_handler = ata_bmdma_error_handler,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400139 .post_internal_cmd = ata_bmdma_post_internal_cmd,
Jeff Garzika73984a2007-03-09 08:37:46 -0500140 .cable_detect = ata_cable_40wire,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400141
142 .bmdma_setup = ata_bmdma_setup,
143 .bmdma_start = ata_bmdma_start,
144 .bmdma_stop = ata_bmdma_stop,
145 .bmdma_status = ata_bmdma_status,
Alan Cox66e7da42007-07-09 11:46:22 -0700146 .check_atapi_dma= hpt3x3_atapi_dma,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400147
148 .qc_prep = ata_qc_prep,
149 .qc_issue = ata_qc_issue_prot,
Jeff Garzikbda30282006-09-27 05:41:13 -0400150
Tejun Heo0d5ff562007-02-01 15:06:36 +0900151 .data_xfer = ata_data_xfer,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400152
153 .irq_handler = ata_interrupt,
154 .irq_clear = ata_bmdma_irq_clear,
Akira Iguchi246ce3b2007-01-26 16:27:58 +0900155 .irq_on = ata_irq_on,
156 .irq_ack = ata_irq_ack,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400157
158 .port_start = ata_port_start,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400159};
160
161/**
Alanaff0df02006-11-27 16:25:51 +0000162 * hpt3x3_init_chipset - chip setup
163 * @dev: PCI device
164 *
165 * Perform the setup required at boot and on resume.
166 */
Jeff Garzikf20b16f2006-12-11 11:14:06 -0500167
Alanaff0df02006-11-27 16:25:51 +0000168static void hpt3x3_init_chipset(struct pci_dev *dev)
169{
170 u16 cmd;
171 /* Initialize the board */
172 pci_write_config_word(dev, 0x80, 0x00);
173 /* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */
174 pci_read_config_word(dev, PCI_COMMAND, &cmd);
175 if (cmd & PCI_COMMAND_MEMORY)
176 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
177 else
178 pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
179}
180
Alanaff0df02006-11-27 16:25:51 +0000181/**
Jeff Garzik669a5db2006-08-29 18:12:40 -0400182 * hpt3x3_init_one - Initialise an HPT343/363
Alan Cox66e7da42007-07-09 11:46:22 -0700183 * @pdev: PCI device
Jeff Garzik669a5db2006-08-29 18:12:40 -0400184 * @id: Entry in match table
185 *
Alan Cox66e7da42007-07-09 11:46:22 -0700186 * Perform basic initialisation. We set the device up so we access all
187 * ports via BAR4. This is neccessary to work around errata.
Jeff Garzik669a5db2006-08-29 18:12:40 -0400188 */
189
Alan Cox66e7da42007-07-09 11:46:22 -0700190static int hpt3x3_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
Jeff Garzik669a5db2006-08-29 18:12:40 -0400191{
Alan Cox66e7da42007-07-09 11:46:22 -0700192 static int printed_version;
Tejun Heo1626aeb2007-05-04 12:43:58 +0200193 static const struct ata_port_info info = {
Jeff Garzik669a5db2006-08-29 18:12:40 -0400194 .sht = &hpt3x3_sht,
Jeff Garzik1d2808f2007-05-28 06:59:48 -0400195 .flags = ATA_FLAG_SLAVE_POSS,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400196 .pio_mask = 0x1f,
Alan Cox66e7da42007-07-09 11:46:22 -0700197#if defined(CONFIG_PATA_HPT3X3_DMA)
198 /* Further debug needed */
Jeff Garzik669a5db2006-08-29 18:12:40 -0400199 .mwdma_mask = 0x07,
200 .udma_mask = 0x07,
Alan Cox66e7da42007-07-09 11:46:22 -0700201#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400202 .port_ops = &hpt3x3_port_ops
203 };
Alan Cox66e7da42007-07-09 11:46:22 -0700204 /* Register offsets of taskfiles in BAR4 area */
205 static const u8 offset_cmd[2] = { 0x20, 0x28 };
206 static const u8 offset_ctl[2] = { 0x36, 0x3E };
Tejun Heo1626aeb2007-05-04 12:43:58 +0200207 const struct ata_port_info *ppi[] = { &info, NULL };
Alan Cox66e7da42007-07-09 11:46:22 -0700208 struct ata_host *host;
209 int i, rc;
210 void __iomem *base;
Jeff Garzik669a5db2006-08-29 18:12:40 -0400211
Alan Cox66e7da42007-07-09 11:46:22 -0700212 hpt3x3_init_chipset(pdev);
213
214 if (!printed_version++)
215 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
216
217 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
218 if (!host)
219 return -ENOMEM;
220 /* acquire resources and fill host */
221 rc = pcim_enable_device(pdev);
222 if (rc)
223 return rc;
224
225 /* Everything is relative to BAR4 if we set up this way */
226 rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME);
227 if (rc == -EBUSY)
228 pcim_pin_device(pdev);
229 if (rc)
230 return rc;
231 host->iomap = pcim_iomap_table(pdev);
232 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
233 if (rc)
234 return rc;
235 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
236 if (rc)
237 return rc;
238
239 base = host->iomap[4]; /* Bus mastering base */
240
241 for (i = 0; i < host->n_ports; i++) {
242 struct ata_ioports *ioaddr = &host->ports[i]->ioaddr;
243
244 ioaddr->cmd_addr = base + offset_cmd[i];
245 ioaddr->altstatus_addr =
246 ioaddr->ctl_addr = base + offset_ctl[i];
247 ioaddr->scr_addr = NULL;
248 ata_std_ports(ioaddr);
249 ioaddr->bmdma_addr = base + 8 * i;
250 }
251 pci_set_master(pdev);
252 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
253 &hpt3x3_sht);
Jeff Garzik669a5db2006-08-29 18:12:40 -0400254}
255
Tejun Heo438ac6d2007-03-02 17:31:26 +0900256#ifdef CONFIG_PM
Alanaff0df02006-11-27 16:25:51 +0000257static int hpt3x3_reinit_one(struct pci_dev *dev)
258{
259 hpt3x3_init_chipset(dev);
260 return ata_pci_device_resume(dev);
261}
Tejun Heo438ac6d2007-03-02 17:31:26 +0900262#endif
Alanaff0df02006-11-27 16:25:51 +0000263
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400264static const struct pci_device_id hpt3x3[] = {
265 { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), },
266
267 { },
Jeff Garzik669a5db2006-08-29 18:12:40 -0400268};
269
270static struct pci_driver hpt3x3_pci_driver = {
Jeff Garzik2d2744f2006-09-28 20:21:59 -0400271 .name = DRV_NAME,
Jeff Garzik669a5db2006-08-29 18:12:40 -0400272 .id_table = hpt3x3,
273 .probe = hpt3x3_init_one,
Alanaff0df02006-11-27 16:25:51 +0000274 .remove = ata_pci_remove_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900275#ifdef CONFIG_PM
Alanaff0df02006-11-27 16:25:51 +0000276 .suspend = ata_pci_device_suspend,
277 .resume = hpt3x3_reinit_one,
Tejun Heo438ac6d2007-03-02 17:31:26 +0900278#endif
Jeff Garzik669a5db2006-08-29 18:12:40 -0400279};
280
281static int __init hpt3x3_init(void)
282{
283 return pci_register_driver(&hpt3x3_pci_driver);
284}
285
286
287static void __exit hpt3x3_exit(void)
288{
289 pci_unregister_driver(&hpt3x3_pci_driver);
290}
291
292
293MODULE_AUTHOR("Alan Cox");
294MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363");
295MODULE_LICENSE("GPL");
296MODULE_DEVICE_TABLE(pci, hpt3x3);
297MODULE_VERSION(DRV_VERSION);
298
299module_init(hpt3x3_init);
300module_exit(hpt3x3_exit);