Dhaval Patel | 14d46ce | 2017-01-17 16:28:12 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2014-2017 The Linux Foundation. All rights reserved. |
| 3 | * Copyright (C) 2013 Red Hat |
| 4 | * Author: Rob Clark <robdclark@gmail.com> |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 5 | * |
Dhaval Patel | 14d46ce | 2017-01-17 16:28:12 -0800 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License version 2 as published by |
| 8 | * the Free Software Foundation. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 9 | * |
Dhaval Patel | 14d46ce | 2017-01-17 16:28:12 -0800 | [diff] [blame] | 10 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 11 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | * more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License along with |
| 16 | * this program. If not, see <http://www.gnu.org/licenses/>. |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 17 | */ |
| 18 | |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 19 | #define pr_fmt(fmt) "[drm:%s:%d] " fmt, __func__, __LINE__ |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 20 | #include <linux/sort.h> |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 21 | #include <linux/debugfs.h> |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 22 | #include <linux/ktime.h> |
Clarence Ip | 4c1d977 | 2016-06-26 09:35:38 -0400 | [diff] [blame] | 23 | #include <uapi/drm/sde_drm.h> |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 24 | #include <drm/drm_mode.h> |
| 25 | #include <drm/drm_crtc.h> |
| 26 | #include <drm/drm_crtc_helper.h> |
| 27 | #include <drm/drm_flip_work.h> |
| 28 | |
| 29 | #include "sde_kms.h" |
| 30 | #include "sde_hw_lm.h" |
Clarence Ip | c475b08 | 2016-06-26 09:27:23 -0400 | [diff] [blame] | 31 | #include "sde_hw_ctl.h" |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 32 | #include "sde_crtc.h" |
Alan Kwong | 83285fb | 2016-10-21 20:51:17 -0400 | [diff] [blame] | 33 | #include "sde_plane.h" |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 34 | #include "sde_color_processing.h" |
Alan Kwong | 83285fb | 2016-10-21 20:51:17 -0400 | [diff] [blame] | 35 | #include "sde_encoder.h" |
| 36 | #include "sde_connector.h" |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 37 | #include "sde_power_handle.h" |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 38 | #include "sde_core_perf.h" |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 39 | #include "sde_trace.h" |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 40 | |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 41 | struct sde_crtc_irq_info { |
| 42 | struct sde_irq_callback irq; |
| 43 | u32 event; |
| 44 | int (*func)(struct drm_crtc *crtc, bool en, |
| 45 | struct sde_irq_callback *irq); |
| 46 | struct list_head list; |
| 47 | }; |
| 48 | |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 49 | struct sde_crtc_custom_events { |
| 50 | u32 event; |
| 51 | int (*func)(struct drm_crtc *crtc, bool en, |
| 52 | struct sde_irq_callback *irq); |
| 53 | }; |
| 54 | |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 55 | static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm, |
| 56 | bool en, struct sde_irq_callback *ad_irq); |
| 57 | |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 58 | static struct sde_crtc_custom_events custom_events[] = { |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 59 | {DRM_EVENT_AD_BACKLIGHT, sde_cp_ad_interrupt}, |
| 60 | {DRM_EVENT_CRTC_POWER, sde_crtc_power_interrupt_handler} |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 61 | }; |
| 62 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 63 | /* default input fence timeout, in ms */ |
| 64 | #define SDE_CRTC_INPUT_FENCE_TIMEOUT 2000 |
| 65 | |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 66 | /* |
| 67 | * The default input fence timeout is 2 seconds while max allowed |
| 68 | * range is 10 seconds. Any value above 10 seconds adds glitches beyond |
| 69 | * tolerance limit. |
| 70 | */ |
| 71 | #define SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT 10000 |
| 72 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 73 | /* layer mixer index on sde_crtc */ |
| 74 | #define LEFT_MIXER 0 |
| 75 | #define RIGHT_MIXER 1 |
| 76 | |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 77 | #define MISR_BUFF_SIZE 256 |
| 78 | |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 79 | static inline struct sde_kms *_sde_crtc_get_kms(struct drm_crtc *crtc) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 80 | { |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 81 | struct msm_drm_private *priv; |
| 82 | |
| 83 | if (!crtc || !crtc->dev || !crtc->dev->dev_private) { |
| 84 | SDE_ERROR("invalid crtc\n"); |
| 85 | return NULL; |
| 86 | } |
| 87 | priv = crtc->dev->dev_private; |
| 88 | if (!priv || !priv->kms) { |
| 89 | SDE_ERROR("invalid kms\n"); |
| 90 | return NULL; |
| 91 | } |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 92 | |
Ben Chan | 78647cd | 2016-06-26 22:02:47 -0400 | [diff] [blame] | 93 | return to_sde_kms(priv->kms); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 94 | } |
| 95 | |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 96 | static inline int _sde_crtc_power_enable(struct sde_crtc *sde_crtc, bool enable) |
| 97 | { |
| 98 | struct drm_crtc *crtc; |
| 99 | struct msm_drm_private *priv; |
| 100 | struct sde_kms *sde_kms; |
| 101 | |
| 102 | if (!sde_crtc) { |
| 103 | SDE_ERROR("invalid sde crtc\n"); |
| 104 | return -EINVAL; |
| 105 | } |
| 106 | |
| 107 | crtc = &sde_crtc->base; |
| 108 | if (!crtc->dev || !crtc->dev->dev_private) { |
| 109 | SDE_ERROR("invalid drm device\n"); |
| 110 | return -EINVAL; |
| 111 | } |
| 112 | |
| 113 | priv = crtc->dev->dev_private; |
| 114 | if (!priv->kms) { |
| 115 | SDE_ERROR("invalid kms\n"); |
| 116 | return -EINVAL; |
| 117 | } |
| 118 | |
| 119 | sde_kms = to_sde_kms(priv->kms); |
| 120 | |
| 121 | return sde_power_resource_enable(&priv->phandle, sde_kms->core_client, |
| 122 | enable); |
| 123 | } |
| 124 | |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 125 | /** |
| 126 | * _sde_crtc_rp_to_crtc - get crtc from resource pool object |
| 127 | * @rp: Pointer to resource pool |
| 128 | * return: Pointer to drm crtc if success; null otherwise |
| 129 | */ |
| 130 | static struct drm_crtc *_sde_crtc_rp_to_crtc(struct sde_crtc_respool *rp) |
| 131 | { |
| 132 | if (!rp) |
| 133 | return NULL; |
| 134 | |
| 135 | return container_of(rp, struct sde_crtc_state, rp)->base.crtc; |
| 136 | } |
| 137 | |
| 138 | /** |
| 139 | * _sde_crtc_rp_reclaim - reclaim unused, or all if forced, resources in pool |
| 140 | * @rp: Pointer to resource pool |
| 141 | * @force: True to reclaim all resources; otherwise, reclaim only unused ones |
| 142 | * return: None |
| 143 | */ |
| 144 | static void _sde_crtc_rp_reclaim(struct sde_crtc_respool *rp, bool force) |
| 145 | { |
| 146 | struct sde_crtc_res *res, *next; |
| 147 | struct drm_crtc *crtc; |
| 148 | |
| 149 | crtc = _sde_crtc_rp_to_crtc(rp); |
| 150 | if (!crtc) { |
| 151 | SDE_ERROR("invalid crtc\n"); |
| 152 | return; |
| 153 | } |
| 154 | |
| 155 | SDE_DEBUG("crtc%d.%u %s\n", crtc->base.id, rp->sequence_id, |
| 156 | force ? "destroy" : "free_unused"); |
| 157 | |
| 158 | list_for_each_entry_safe(res, next, &rp->res_list, list) { |
| 159 | if (!force && !(res->flags & SDE_CRTC_RES_FLAG_FREE)) |
| 160 | continue; |
| 161 | SDE_DEBUG("crtc%d.%u reclaim res:0x%x/0x%llx/%pK/%d\n", |
| 162 | crtc->base.id, rp->sequence_id, |
| 163 | res->type, res->tag, res->val, |
| 164 | atomic_read(&res->refcount)); |
| 165 | list_del(&res->list); |
| 166 | if (res->ops.put) |
| 167 | res->ops.put(res->val); |
| 168 | kfree(res); |
| 169 | } |
| 170 | } |
| 171 | |
| 172 | /** |
| 173 | * _sde_crtc_rp_free_unused - free unused resource in pool |
| 174 | * @rp: Pointer to resource pool |
| 175 | * return: none |
| 176 | */ |
| 177 | static void _sde_crtc_rp_free_unused(struct sde_crtc_respool *rp) |
| 178 | { |
| 179 | _sde_crtc_rp_reclaim(rp, false); |
| 180 | } |
| 181 | |
| 182 | /** |
| 183 | * _sde_crtc_rp_destroy - destroy resource pool |
| 184 | * @rp: Pointer to resource pool |
| 185 | * return: None |
| 186 | */ |
| 187 | static void _sde_crtc_rp_destroy(struct sde_crtc_respool *rp) |
| 188 | { |
| 189 | _sde_crtc_rp_reclaim(rp, true); |
| 190 | } |
| 191 | |
| 192 | /** |
| 193 | * _sde_crtc_hw_blk_get - get callback for hardware block |
| 194 | * @val: Resource handle |
| 195 | * @type: Resource type |
| 196 | * @tag: Search tag for given resource |
| 197 | * return: Resource handle |
| 198 | */ |
| 199 | static void *_sde_crtc_hw_blk_get(void *val, u32 type, u64 tag) |
| 200 | { |
| 201 | SDE_DEBUG("res:%d/0x%llx/%pK\n", type, tag, val); |
| 202 | return sde_hw_blk_get(val, type, tag); |
| 203 | } |
| 204 | |
| 205 | /** |
| 206 | * _sde_crtc_hw_blk_put - put callback for hardware block |
| 207 | * @val: Resource handle |
| 208 | * return: None |
| 209 | */ |
| 210 | static void _sde_crtc_hw_blk_put(void *val) |
| 211 | { |
| 212 | SDE_DEBUG("res://%pK\n", val); |
| 213 | sde_hw_blk_put(val); |
| 214 | } |
| 215 | |
| 216 | /** |
| 217 | * _sde_crtc_rp_duplicate - duplicate resource pool and reset reference count |
| 218 | * @rp: Pointer to original resource pool |
| 219 | * @dup_rp: Pointer to duplicated resource pool |
| 220 | * return: None |
| 221 | */ |
| 222 | static void _sde_crtc_rp_duplicate(struct sde_crtc_respool *rp, |
| 223 | struct sde_crtc_respool *dup_rp) |
| 224 | { |
| 225 | struct sde_crtc_res *res, *dup_res; |
| 226 | struct drm_crtc *crtc; |
| 227 | |
| 228 | if (!rp || !dup_rp) { |
| 229 | SDE_ERROR("invalid resource pool\n"); |
| 230 | return; |
| 231 | } |
| 232 | |
| 233 | crtc = _sde_crtc_rp_to_crtc(rp); |
| 234 | if (!crtc) { |
| 235 | SDE_ERROR("invalid crtc\n"); |
| 236 | return; |
| 237 | } |
| 238 | |
| 239 | SDE_DEBUG("crtc%d.%u duplicate\n", crtc->base.id, rp->sequence_id); |
| 240 | |
| 241 | dup_rp->sequence_id = rp->sequence_id + 1; |
| 242 | INIT_LIST_HEAD(&dup_rp->res_list); |
| 243 | dup_rp->ops = rp->ops; |
| 244 | list_for_each_entry(res, &rp->res_list, list) { |
| 245 | dup_res = kzalloc(sizeof(struct sde_crtc_res), GFP_KERNEL); |
| 246 | if (!dup_res) |
| 247 | return; |
| 248 | INIT_LIST_HEAD(&dup_res->list); |
| 249 | atomic_set(&dup_res->refcount, 0); |
| 250 | dup_res->type = res->type; |
| 251 | dup_res->tag = res->tag; |
| 252 | dup_res->val = res->val; |
| 253 | dup_res->ops = res->ops; |
| 254 | dup_res->flags = SDE_CRTC_RES_FLAG_FREE; |
| 255 | SDE_DEBUG("crtc%d.%u dup res:0x%x/0x%llx/%pK/%d\n", |
| 256 | crtc->base.id, dup_rp->sequence_id, |
| 257 | dup_res->type, dup_res->tag, dup_res->val, |
| 258 | atomic_read(&dup_res->refcount)); |
| 259 | list_add_tail(&dup_res->list, &dup_rp->res_list); |
| 260 | if (dup_res->ops.get) |
| 261 | dup_res->ops.get(dup_res->val, 0, -1); |
| 262 | } |
| 263 | } |
| 264 | |
| 265 | /** |
| 266 | * _sde_crtc_rp_reset - reset resource pool after allocation |
| 267 | * @rp: Pointer to original resource pool |
| 268 | * return: None |
| 269 | */ |
| 270 | static void _sde_crtc_rp_reset(struct sde_crtc_respool *rp) |
| 271 | { |
| 272 | if (!rp) { |
| 273 | SDE_ERROR("invalid resource pool\n"); |
| 274 | return; |
| 275 | } |
| 276 | |
| 277 | rp->sequence_id = 0; |
| 278 | INIT_LIST_HEAD(&rp->res_list); |
| 279 | rp->ops.get = _sde_crtc_hw_blk_get; |
| 280 | rp->ops.put = _sde_crtc_hw_blk_put; |
| 281 | } |
| 282 | |
| 283 | /** |
| 284 | * _sde_crtc_rp_add - add given resource to resource pool |
| 285 | * @rp: Pointer to original resource pool |
| 286 | * @type: Resource type |
| 287 | * @tag: Search tag for given resource |
| 288 | * @val: Resource handle |
| 289 | * @ops: Resource callback operations |
| 290 | * return: 0 if success; error code otherwise |
| 291 | */ |
| 292 | static int _sde_crtc_rp_add(struct sde_crtc_respool *rp, u32 type, u64 tag, |
| 293 | void *val, struct sde_crtc_res_ops *ops) |
| 294 | { |
| 295 | struct sde_crtc_res *res; |
| 296 | struct drm_crtc *crtc; |
| 297 | |
| 298 | if (!rp || !ops) { |
| 299 | SDE_ERROR("invalid resource pool/ops\n"); |
| 300 | return -EINVAL; |
| 301 | } |
| 302 | |
| 303 | crtc = _sde_crtc_rp_to_crtc(rp); |
| 304 | if (!crtc) { |
| 305 | SDE_ERROR("invalid crtc\n"); |
| 306 | return -EINVAL; |
| 307 | } |
| 308 | |
| 309 | list_for_each_entry(res, &rp->res_list, list) { |
| 310 | if (res->type != type || res->tag != tag) |
| 311 | continue; |
| 312 | SDE_ERROR("crtc%d.%u already exist res:0x%x/0x%llx/%pK/%d\n", |
| 313 | crtc->base.id, rp->sequence_id, |
| 314 | res->type, res->tag, res->val, |
| 315 | atomic_read(&res->refcount)); |
| 316 | return -EEXIST; |
| 317 | } |
| 318 | res = kzalloc(sizeof(struct sde_crtc_res), GFP_KERNEL); |
| 319 | if (!res) |
| 320 | return -ENOMEM; |
| 321 | INIT_LIST_HEAD(&res->list); |
| 322 | atomic_set(&res->refcount, 1); |
| 323 | res->type = type; |
| 324 | res->tag = tag; |
| 325 | res->val = val; |
| 326 | res->ops = *ops; |
| 327 | list_add_tail(&res->list, &rp->res_list); |
| 328 | SDE_DEBUG("crtc%d.%u added res:0x%x/0x%llx\n", |
| 329 | crtc->base.id, rp->sequence_id, type, tag); |
| 330 | return 0; |
| 331 | } |
| 332 | |
| 333 | /** |
| 334 | * _sde_crtc_rp_get - lookup the resource from given resource pool and obtain |
| 335 | * if available; otherwise, obtain resource from global pool |
| 336 | * @rp: Pointer to original resource pool |
| 337 | * @type: Resource type |
| 338 | * @tag: Search tag for given resource |
| 339 | * return: Resource handle if success; pointer error or null otherwise |
| 340 | */ |
| 341 | static void *_sde_crtc_rp_get(struct sde_crtc_respool *rp, u32 type, u64 tag) |
| 342 | { |
| 343 | struct sde_crtc_res *res; |
| 344 | void *val = NULL; |
| 345 | int rc; |
| 346 | struct drm_crtc *crtc; |
| 347 | |
| 348 | if (!rp) { |
| 349 | SDE_ERROR("invalid resource pool\n"); |
| 350 | return NULL; |
| 351 | } |
| 352 | |
| 353 | crtc = _sde_crtc_rp_to_crtc(rp); |
| 354 | if (!crtc) { |
| 355 | SDE_ERROR("invalid crtc\n"); |
| 356 | return NULL; |
| 357 | } |
| 358 | |
| 359 | list_for_each_entry(res, &rp->res_list, list) { |
| 360 | if (res->type != type || res->tag != tag) |
| 361 | continue; |
| 362 | SDE_DEBUG("crtc%d.%u found res:0x%x/0x%llx/%pK/%d\n", |
| 363 | crtc->base.id, rp->sequence_id, |
| 364 | res->type, res->tag, res->val, |
| 365 | atomic_read(&res->refcount)); |
| 366 | atomic_inc(&res->refcount); |
| 367 | res->flags &= ~SDE_CRTC_RES_FLAG_FREE; |
| 368 | return res->val; |
| 369 | } |
| 370 | list_for_each_entry(res, &rp->res_list, list) { |
| 371 | if (res->type != type || !(res->flags & SDE_CRTC_RES_FLAG_FREE)) |
| 372 | continue; |
| 373 | SDE_DEBUG("crtc%d.%u retag res:0x%x/0x%llx/%pK/%d\n", |
| 374 | crtc->base.id, rp->sequence_id, |
| 375 | res->type, res->tag, res->val, |
| 376 | atomic_read(&res->refcount)); |
| 377 | atomic_inc(&res->refcount); |
| 378 | res->tag = tag; |
| 379 | res->flags &= ~SDE_CRTC_RES_FLAG_FREE; |
| 380 | return res->val; |
| 381 | } |
| 382 | if (rp->ops.get) |
| 383 | val = rp->ops.get(NULL, type, -1); |
| 384 | if (IS_ERR_OR_NULL(val)) { |
Alan Kwong | 42e3505 | 2017-05-05 06:52:51 -0700 | [diff] [blame] | 385 | SDE_DEBUG("crtc%d.%u failed to get res:0x%x//\n", |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 386 | crtc->base.id, rp->sequence_id, type); |
| 387 | return NULL; |
| 388 | } |
| 389 | rc = _sde_crtc_rp_add(rp, type, tag, val, &rp->ops); |
| 390 | if (rc) { |
| 391 | SDE_ERROR("crtc%d.%u failed to add res:0x%x/0x%llx\n", |
| 392 | crtc->base.id, rp->sequence_id, type, tag); |
| 393 | if (rp->ops.put) |
| 394 | rp->ops.put(val); |
| 395 | val = NULL; |
| 396 | } |
| 397 | return val; |
| 398 | } |
| 399 | |
| 400 | /** |
| 401 | * _sde_crtc_rp_put - return given resource to resource pool |
| 402 | * @rp: Pointer to original resource pool |
| 403 | * @type: Resource type |
| 404 | * @tag: Search tag for given resource |
| 405 | * return: None |
| 406 | */ |
| 407 | static void _sde_crtc_rp_put(struct sde_crtc_respool *rp, u32 type, u64 tag) |
| 408 | { |
| 409 | struct sde_crtc_res *res, *next; |
| 410 | struct drm_crtc *crtc; |
| 411 | |
| 412 | if (!rp) { |
| 413 | SDE_ERROR("invalid resource pool\n"); |
| 414 | return; |
| 415 | } |
| 416 | |
| 417 | crtc = _sde_crtc_rp_to_crtc(rp); |
| 418 | if (!crtc) { |
| 419 | SDE_ERROR("invalid crtc\n"); |
| 420 | return; |
| 421 | } |
| 422 | |
| 423 | list_for_each_entry_safe(res, next, &rp->res_list, list) { |
| 424 | if (res->type != type || res->tag != tag) |
| 425 | continue; |
| 426 | SDE_DEBUG("crtc%d.%u found res:0x%x/0x%llx/%pK/%d\n", |
| 427 | crtc->base.id, rp->sequence_id, |
| 428 | res->type, res->tag, res->val, |
| 429 | atomic_read(&res->refcount)); |
| 430 | if (res->flags & SDE_CRTC_RES_FLAG_FREE) |
| 431 | SDE_ERROR( |
| 432 | "crtc%d.%u already free res:0x%x/0x%llx/%pK/%d\n", |
| 433 | crtc->base.id, rp->sequence_id, |
| 434 | res->type, res->tag, res->val, |
| 435 | atomic_read(&res->refcount)); |
| 436 | else if (atomic_dec_return(&res->refcount) == 0) |
| 437 | res->flags |= SDE_CRTC_RES_FLAG_FREE; |
| 438 | |
| 439 | return; |
| 440 | } |
| 441 | SDE_ERROR("crtc%d.%u not found res:0x%x/0x%llx\n", |
| 442 | crtc->base.id, rp->sequence_id, type, tag); |
| 443 | } |
| 444 | |
| 445 | int sde_crtc_res_add(struct drm_crtc_state *state, u32 type, u64 tag, |
| 446 | void *val, struct sde_crtc_res_ops *ops) |
| 447 | { |
| 448 | struct sde_crtc_respool *rp; |
| 449 | |
| 450 | if (!state) { |
| 451 | SDE_ERROR("invalid parameters\n"); |
| 452 | return -EINVAL; |
| 453 | } |
| 454 | |
| 455 | rp = &to_sde_crtc_state(state)->rp; |
| 456 | return _sde_crtc_rp_add(rp, type, tag, val, ops); |
| 457 | } |
| 458 | |
| 459 | void *sde_crtc_res_get(struct drm_crtc_state *state, u32 type, u64 tag) |
| 460 | { |
| 461 | struct sde_crtc_respool *rp; |
| 462 | void *val; |
| 463 | |
| 464 | if (!state) { |
| 465 | SDE_ERROR("invalid parameters\n"); |
| 466 | return NULL; |
| 467 | } |
| 468 | |
| 469 | rp = &to_sde_crtc_state(state)->rp; |
| 470 | val = _sde_crtc_rp_get(rp, type, tag); |
| 471 | if (IS_ERR(val)) { |
| 472 | SDE_ERROR("failed to get res type:0x%x:0x%llx\n", |
| 473 | type, tag); |
| 474 | return NULL; |
| 475 | } |
| 476 | |
| 477 | return val; |
| 478 | } |
| 479 | |
| 480 | void sde_crtc_res_put(struct drm_crtc_state *state, u32 type, u64 tag) |
| 481 | { |
| 482 | struct sde_crtc_respool *rp; |
| 483 | |
| 484 | if (!state) { |
| 485 | SDE_ERROR("invalid parameters\n"); |
| 486 | return; |
| 487 | } |
| 488 | |
| 489 | rp = &to_sde_crtc_state(state)->rp; |
| 490 | _sde_crtc_rp_put(rp, type, tag); |
| 491 | } |
| 492 | |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 493 | static void _sde_crtc_deinit_events(struct sde_crtc *sde_crtc) |
| 494 | { |
| 495 | if (!sde_crtc) |
| 496 | return; |
| 497 | |
| 498 | if (sde_crtc->event_thread) { |
| 499 | kthread_flush_worker(&sde_crtc->event_worker); |
| 500 | kthread_stop(sde_crtc->event_thread); |
| 501 | sde_crtc->event_thread = NULL; |
| 502 | } |
| 503 | } |
| 504 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 505 | static void sde_crtc_destroy(struct drm_crtc *crtc) |
| 506 | { |
| 507 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 508 | |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 509 | SDE_DEBUG("\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 510 | |
| 511 | if (!crtc) |
| 512 | return; |
| 513 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 514 | if (sde_crtc->blob_info) |
| 515 | drm_property_unreference_blob(sde_crtc->blob_info); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 516 | msm_property_destroy(&sde_crtc->property_info); |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 517 | sde_cp_crtc_destroy_properties(crtc); |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 518 | |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 519 | sde_fence_deinit(&sde_crtc->output_fence); |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 520 | _sde_crtc_deinit_events(sde_crtc); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 521 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 522 | drm_crtc_cleanup(crtc); |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 523 | mutex_destroy(&sde_crtc->crtc_lock); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 524 | kfree(sde_crtc); |
| 525 | } |
| 526 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 527 | static bool sde_crtc_mode_fixup(struct drm_crtc *crtc, |
| 528 | const struct drm_display_mode *mode, |
| 529 | struct drm_display_mode *adjusted_mode) |
| 530 | { |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 531 | SDE_DEBUG("\n"); |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 532 | |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 533 | if (msm_is_mode_seamless(adjusted_mode) && |
| 534 | (!crtc->enabled || crtc->state->active_changed)) { |
| 535 | SDE_ERROR("crtc state prevents seamless transition\n"); |
| 536 | return false; |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 537 | } |
| 538 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 539 | return true; |
| 540 | } |
| 541 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 542 | static void _sde_crtc_setup_blend_cfg(struct sde_crtc_mixer *mixer, |
| 543 | struct sde_plane_state *pstate, struct sde_format *format) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 544 | { |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 545 | uint32_t blend_op, fg_alpha, bg_alpha; |
| 546 | uint32_t blend_type; |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 547 | struct sde_hw_mixer *lm = mixer->hw_lm; |
| 548 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 549 | /* default to opaque blending */ |
| 550 | fg_alpha = sde_plane_get_property(pstate, PLANE_PROP_ALPHA); |
| 551 | bg_alpha = 0xFF - fg_alpha; |
| 552 | blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | SDE_BLEND_BG_ALPHA_BG_CONST; |
| 553 | blend_type = sde_plane_get_property(pstate, PLANE_PROP_BLEND_OP); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 554 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 555 | SDE_DEBUG("blend type:0x%x blend alpha:0x%x\n", blend_type, fg_alpha); |
| 556 | |
| 557 | switch (blend_type) { |
| 558 | |
| 559 | case SDE_DRM_BLEND_OP_OPAQUE: |
| 560 | blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | |
| 561 | SDE_BLEND_BG_ALPHA_BG_CONST; |
| 562 | break; |
| 563 | |
| 564 | case SDE_DRM_BLEND_OP_PREMULTIPLIED: |
| 565 | if (format->alpha_enable) { |
| 566 | blend_op = SDE_BLEND_FG_ALPHA_FG_CONST | |
| 567 | SDE_BLEND_BG_ALPHA_FG_PIXEL; |
| 568 | if (fg_alpha != 0xff) { |
| 569 | bg_alpha = fg_alpha; |
| 570 | blend_op |= SDE_BLEND_BG_MOD_ALPHA | |
| 571 | SDE_BLEND_BG_INV_MOD_ALPHA; |
| 572 | } else { |
| 573 | blend_op |= SDE_BLEND_BG_INV_ALPHA; |
| 574 | } |
| 575 | } |
| 576 | break; |
| 577 | |
| 578 | case SDE_DRM_BLEND_OP_COVERAGE: |
| 579 | if (format->alpha_enable) { |
| 580 | blend_op = SDE_BLEND_FG_ALPHA_FG_PIXEL | |
| 581 | SDE_BLEND_BG_ALPHA_FG_PIXEL; |
| 582 | if (fg_alpha != 0xff) { |
| 583 | bg_alpha = fg_alpha; |
| 584 | blend_op |= SDE_BLEND_FG_MOD_ALPHA | |
| 585 | SDE_BLEND_FG_INV_MOD_ALPHA | |
| 586 | SDE_BLEND_BG_MOD_ALPHA | |
| 587 | SDE_BLEND_BG_INV_MOD_ALPHA; |
| 588 | } else { |
| 589 | blend_op |= SDE_BLEND_BG_INV_ALPHA; |
| 590 | } |
| 591 | } |
| 592 | break; |
| 593 | default: |
| 594 | /* do nothing */ |
| 595 | break; |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 596 | } |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 597 | |
| 598 | lm->ops.setup_blend_config(lm, pstate->stage, fg_alpha, |
| 599 | bg_alpha, blend_op); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 600 | SDE_DEBUG( |
| 601 | "format: %4.4s, alpha_enable %u fg alpha:0x%x bg alpha:0x%x blend_op:0x%x\n", |
| 602 | (char *) &format->base.pixel_format, |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 603 | format->alpha_enable, fg_alpha, bg_alpha, blend_op); |
| 604 | } |
| 605 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 606 | static void _sde_crtc_setup_dim_layer_cfg(struct drm_crtc *crtc, |
| 607 | struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer, |
| 608 | struct sde_hw_dim_layer *dim_layer) |
| 609 | { |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 610 | struct sde_crtc_state *cstate; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 611 | struct sde_hw_mixer *lm; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 612 | struct sde_hw_dim_layer split_dim_layer; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 613 | int i; |
| 614 | |
| 615 | if (!dim_layer->rect.w || !dim_layer->rect.h) { |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 616 | SDE_DEBUG("empty dim_layer\n"); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 617 | return; |
| 618 | } |
| 619 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 620 | cstate = to_sde_crtc_state(crtc->state); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 621 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 622 | SDE_DEBUG("dim_layer - flags:%d, stage:%d\n", |
| 623 | dim_layer->flags, dim_layer->stage); |
| 624 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 625 | split_dim_layer.stage = dim_layer->stage; |
| 626 | split_dim_layer.color_fill = dim_layer->color_fill; |
| 627 | |
| 628 | /* |
| 629 | * traverse through the layer mixers attached to crtc and find the |
| 630 | * intersecting dim layer rect in each LM and program accordingly. |
| 631 | */ |
| 632 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
| 633 | split_dim_layer.flags = dim_layer->flags; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 634 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 635 | sde_kms_rect_intersect(&cstate->lm_bounds[i], &dim_layer->rect, |
Lloyd Atkinson | e0e11e2 | 2017-01-17 12:08:48 -0500 | [diff] [blame] | 636 | &split_dim_layer.rect); |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 637 | if (sde_kms_rect_is_null(&split_dim_layer.rect)) { |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 638 | /* |
| 639 | * no extra programming required for non-intersecting |
| 640 | * layer mixers with INCLUSIVE dim layer |
| 641 | */ |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 642 | if (split_dim_layer.flags & SDE_DRM_DIM_LAYER_INCLUSIVE) |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 643 | continue; |
| 644 | |
| 645 | /* |
| 646 | * program the other non-intersecting layer mixers with |
| 647 | * INCLUSIVE dim layer of full size for uniformity |
| 648 | * with EXCLUSIVE dim layer config. |
| 649 | */ |
| 650 | split_dim_layer.flags &= ~SDE_DRM_DIM_LAYER_EXCLUSIVE; |
| 651 | split_dim_layer.flags |= SDE_DRM_DIM_LAYER_INCLUSIVE; |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 652 | memcpy(&split_dim_layer.rect, &cstate->lm_bounds[i], |
| 653 | sizeof(split_dim_layer.rect)); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 654 | |
| 655 | } else { |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 656 | split_dim_layer.rect.x = |
| 657 | split_dim_layer.rect.x - |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 658 | cstate->lm_bounds[i].x; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 659 | } |
| 660 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 661 | SDE_DEBUG("split_dim_layer - LM:%d, rect:{%d,%d,%d,%d}}\n", |
| 662 | i, split_dim_layer.rect.x, split_dim_layer.rect.y, |
| 663 | split_dim_layer.rect.w, split_dim_layer.rect.h); |
| 664 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 665 | lm = mixer[i].hw_lm; |
| 666 | mixer[i].mixer_op_mode |= 1 << split_dim_layer.stage; |
| 667 | lm->ops.setup_dim_layer(lm, &split_dim_layer); |
| 668 | } |
| 669 | } |
| 670 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 671 | void sde_crtc_get_crtc_roi(struct drm_crtc_state *state, |
| 672 | const struct sde_rect **crtc_roi) |
| 673 | { |
| 674 | struct sde_crtc_state *crtc_state; |
| 675 | |
| 676 | if (!state || !crtc_roi) |
| 677 | return; |
| 678 | |
| 679 | crtc_state = to_sde_crtc_state(state); |
| 680 | *crtc_roi = &crtc_state->crtc_roi; |
| 681 | } |
| 682 | |
| 683 | static int _sde_crtc_set_roi_v1(struct drm_crtc_state *state, |
| 684 | void *usr_ptr) |
| 685 | { |
| 686 | struct drm_crtc *crtc; |
| 687 | struct sde_crtc_state *cstate; |
| 688 | struct sde_drm_roi_v1 roi_v1; |
| 689 | int i; |
| 690 | |
| 691 | if (!state) { |
| 692 | SDE_ERROR("invalid args\n"); |
| 693 | return -EINVAL; |
| 694 | } |
| 695 | |
| 696 | cstate = to_sde_crtc_state(state); |
| 697 | crtc = cstate->base.crtc; |
| 698 | |
| 699 | memset(&cstate->user_roi_list, 0, sizeof(cstate->user_roi_list)); |
| 700 | |
| 701 | if (!usr_ptr) { |
| 702 | SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc)); |
| 703 | return 0; |
| 704 | } |
| 705 | |
| 706 | if (copy_from_user(&roi_v1, usr_ptr, sizeof(roi_v1))) { |
| 707 | SDE_ERROR("crtc%d: failed to copy roi_v1 data\n", DRMID(crtc)); |
| 708 | return -EINVAL; |
| 709 | } |
| 710 | |
| 711 | SDE_DEBUG("crtc%d: num_rects %d\n", DRMID(crtc), roi_v1.num_rects); |
| 712 | |
| 713 | if (roi_v1.num_rects == 0) { |
| 714 | SDE_DEBUG("crtc%d: rois cleared\n", DRMID(crtc)); |
| 715 | return 0; |
| 716 | } |
| 717 | |
| 718 | if (roi_v1.num_rects > SDE_MAX_ROI_V1) { |
| 719 | SDE_ERROR("crtc%d: too many rects specified: %d\n", DRMID(crtc), |
| 720 | roi_v1.num_rects); |
| 721 | return -EINVAL; |
| 722 | } |
| 723 | |
| 724 | cstate->user_roi_list.num_rects = roi_v1.num_rects; |
| 725 | for (i = 0; i < roi_v1.num_rects; ++i) { |
| 726 | cstate->user_roi_list.roi[i] = roi_v1.roi[i]; |
| 727 | SDE_DEBUG("crtc%d: roi%d: roi (%d,%d) (%d,%d)\n", |
| 728 | DRMID(crtc), i, |
| 729 | cstate->user_roi_list.roi[i].x1, |
| 730 | cstate->user_roi_list.roi[i].y1, |
| 731 | cstate->user_roi_list.roi[i].x2, |
| 732 | cstate->user_roi_list.roi[i].y2); |
| 733 | } |
| 734 | |
| 735 | return 0; |
| 736 | } |
| 737 | |
Ingrid Gallardo | 8353222 | 2017-06-02 16:48:51 -0700 | [diff] [blame] | 738 | static bool _sde_crtc_setup_is_3dmux_dsc(struct drm_crtc_state *state) |
| 739 | { |
| 740 | int i; |
| 741 | struct sde_crtc_state *cstate; |
| 742 | bool is_3dmux_dsc = false; |
| 743 | |
| 744 | cstate = to_sde_crtc_state(state); |
| 745 | |
| 746 | for (i = 0; i < cstate->num_connectors; i++) { |
| 747 | struct drm_connector *conn = cstate->connectors[i]; |
| 748 | |
| 749 | if (sde_connector_get_topology_name(conn) == |
| 750 | SDE_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC) |
| 751 | is_3dmux_dsc = true; |
| 752 | } |
| 753 | |
| 754 | return is_3dmux_dsc; |
| 755 | } |
| 756 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 757 | static int _sde_crtc_set_crtc_roi(struct drm_crtc *crtc, |
| 758 | struct drm_crtc_state *state) |
| 759 | { |
| 760 | struct drm_connector *conn; |
| 761 | struct drm_connector_state *conn_state; |
| 762 | struct sde_crtc *sde_crtc; |
| 763 | struct sde_crtc_state *crtc_state; |
| 764 | struct sde_rect *crtc_roi; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 765 | int i, num_attached_conns = 0; |
| 766 | |
| 767 | if (!crtc || !state) |
| 768 | return -EINVAL; |
| 769 | |
| 770 | sde_crtc = to_sde_crtc(crtc); |
| 771 | crtc_state = to_sde_crtc_state(state); |
| 772 | crtc_roi = &crtc_state->crtc_roi; |
| 773 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 774 | for_each_connector_in_state(state->state, conn, conn_state, i) { |
| 775 | struct sde_connector_state *sde_conn_state; |
| 776 | |
| 777 | if (!conn_state || conn_state->crtc != crtc) |
| 778 | continue; |
| 779 | |
| 780 | if (num_attached_conns) { |
| 781 | SDE_ERROR( |
| 782 | "crtc%d: unsupported: roi on crtc w/ >1 connectors\n", |
| 783 | DRMID(crtc)); |
| 784 | return -EINVAL; |
| 785 | } |
| 786 | ++num_attached_conns; |
| 787 | |
| 788 | sde_conn_state = to_sde_connector_state(conn_state); |
| 789 | |
Ingrid Gallardo | 8353222 | 2017-06-02 16:48:51 -0700 | [diff] [blame] | 790 | /* |
| 791 | * current driver only supports same connector and crtc size, |
| 792 | * but if support for different sizes is added, driver needs |
| 793 | * to check the connector roi here to make sure is full screen |
| 794 | * for dsc 3d-mux topology that doesn't support partial update. |
| 795 | */ |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 796 | if (memcmp(&sde_conn_state->rois, &crtc_state->user_roi_list, |
| 797 | sizeof(crtc_state->user_roi_list))) { |
| 798 | SDE_ERROR("%s: crtc -> conn roi scaling unsupported\n", |
| 799 | sde_crtc->name); |
| 800 | return -EINVAL; |
| 801 | } |
| 802 | } |
| 803 | |
Lloyd Atkinson | c2baf41 | 2017-04-19 17:53:09 -0400 | [diff] [blame] | 804 | sde_kms_rect_merge_rectangles(&crtc_state->user_roi_list, crtc_roi); |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 805 | |
Ingrid Gallardo | 8353222 | 2017-06-02 16:48:51 -0700 | [diff] [blame] | 806 | /* |
| 807 | * for 3dmux dsc, make sure is full ROI, since current driver doesn't |
| 808 | * support partial update for this configuration. |
| 809 | */ |
| 810 | if (!sde_kms_rect_is_null(crtc_roi) && |
| 811 | _sde_crtc_setup_is_3dmux_dsc(state)) { |
| 812 | struct drm_display_mode *adj_mode = &state->adjusted_mode; |
| 813 | |
| 814 | if (crtc_roi->w != adj_mode->hdisplay || |
| 815 | crtc_roi->h != adj_mode->vdisplay) { |
| 816 | SDE_ERROR("%s: unsupported top roi[%d %d] wxh[%d %d]\n", |
| 817 | sde_crtc->name, crtc_roi->w, crtc_roi->h, |
| 818 | adj_mode->hdisplay, adj_mode->vdisplay); |
| 819 | return -EINVAL; |
| 820 | } |
| 821 | } |
| 822 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 823 | SDE_DEBUG("%s: crtc roi (%d,%d,%d,%d)\n", sde_crtc->name, |
| 824 | crtc_roi->x, crtc_roi->y, crtc_roi->w, crtc_roi->h); |
| 825 | |
| 826 | return 0; |
| 827 | } |
| 828 | |
Lloyd Atkinson | 7738220 | 2017-02-01 14:59:43 -0500 | [diff] [blame] | 829 | static int _sde_crtc_check_autorefresh(struct drm_crtc *crtc, |
| 830 | struct drm_crtc_state *state) |
| 831 | { |
| 832 | struct sde_crtc *sde_crtc; |
| 833 | struct sde_crtc_state *crtc_state; |
| 834 | struct drm_connector *conn; |
| 835 | struct drm_connector_state *conn_state; |
| 836 | int i; |
| 837 | |
| 838 | if (!crtc || !state) |
| 839 | return -EINVAL; |
| 840 | |
| 841 | sde_crtc = to_sde_crtc(crtc); |
| 842 | crtc_state = to_sde_crtc_state(state); |
| 843 | |
| 844 | if (sde_kms_rect_is_null(&crtc_state->crtc_roi)) |
| 845 | return 0; |
| 846 | |
| 847 | /* partial update active, check if autorefresh is also requested */ |
| 848 | for_each_connector_in_state(state->state, conn, conn_state, i) { |
| 849 | uint64_t autorefresh; |
| 850 | |
| 851 | if (!conn_state || conn_state->crtc != crtc) |
| 852 | continue; |
| 853 | |
| 854 | autorefresh = sde_connector_get_property(conn_state, |
| 855 | CONNECTOR_PROP_AUTOREFRESH); |
| 856 | if (autorefresh) { |
| 857 | SDE_ERROR( |
| 858 | "%s: autorefresh & partial crtc roi incompatible %llu\n", |
| 859 | sde_crtc->name, autorefresh); |
| 860 | return -EINVAL; |
| 861 | } |
| 862 | } |
| 863 | |
| 864 | return 0; |
| 865 | } |
| 866 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 867 | static int _sde_crtc_set_lm_roi(struct drm_crtc *crtc, |
| 868 | struct drm_crtc_state *state, int lm_idx) |
| 869 | { |
| 870 | struct sde_crtc *sde_crtc; |
| 871 | struct sde_crtc_state *crtc_state; |
| 872 | const struct sde_rect *crtc_roi; |
| 873 | const struct sde_rect *lm_bounds; |
| 874 | struct sde_rect *lm_roi; |
| 875 | |
| 876 | if (!crtc || !state || lm_idx >= ARRAY_SIZE(crtc_state->lm_bounds)) |
| 877 | return -EINVAL; |
| 878 | |
| 879 | sde_crtc = to_sde_crtc(crtc); |
| 880 | crtc_state = to_sde_crtc_state(state); |
| 881 | crtc_roi = &crtc_state->crtc_roi; |
| 882 | lm_bounds = &crtc_state->lm_bounds[lm_idx]; |
| 883 | lm_roi = &crtc_state->lm_roi[lm_idx]; |
| 884 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 885 | if (sde_kms_rect_is_null(crtc_roi)) |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 886 | memcpy(lm_roi, lm_bounds, sizeof(*lm_roi)); |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 887 | else |
| 888 | sde_kms_rect_intersect(crtc_roi, lm_bounds, lm_roi); |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 889 | |
| 890 | SDE_DEBUG("%s: lm%d roi (%d,%d,%d,%d)\n", sde_crtc->name, lm_idx, |
| 891 | lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h); |
| 892 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 893 | /* if any dimension is zero, clear all dimensions for clarity */ |
| 894 | if (sde_kms_rect_is_null(lm_roi)) |
| 895 | memset(lm_roi, 0, sizeof(*lm_roi)); |
| 896 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 897 | return 0; |
| 898 | } |
| 899 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 900 | static u32 _sde_crtc_get_displays_affected(struct drm_crtc *crtc, |
| 901 | struct drm_crtc_state *state) |
| 902 | { |
| 903 | struct sde_crtc *sde_crtc; |
| 904 | struct sde_crtc_state *crtc_state; |
| 905 | u32 disp_bitmask = 0; |
| 906 | int i; |
| 907 | |
| 908 | sde_crtc = to_sde_crtc(crtc); |
| 909 | crtc_state = to_sde_crtc_state(state); |
| 910 | |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 911 | /* pingpong split: one ROI, one LM, two physical displays */ |
| 912 | if (crtc_state->is_ppsplit) { |
| 913 | u32 lm_split_width = crtc_state->lm_bounds[0].w / 2; |
| 914 | struct sde_rect *roi = &crtc_state->lm_roi[0]; |
| 915 | |
| 916 | if (sde_kms_rect_is_null(roi)) |
| 917 | disp_bitmask = 0; |
| 918 | else if ((u32)roi->x + (u32)roi->w <= lm_split_width) |
| 919 | disp_bitmask = BIT(0); /* left only */ |
| 920 | else if (roi->x >= lm_split_width) |
| 921 | disp_bitmask = BIT(1); /* right only */ |
| 922 | else |
| 923 | disp_bitmask = BIT(0) | BIT(1); /* left and right */ |
| 924 | } else { |
| 925 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
| 926 | if (!sde_kms_rect_is_null(&crtc_state->lm_roi[i])) |
| 927 | disp_bitmask |= BIT(i); |
| 928 | } |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 929 | } |
| 930 | |
| 931 | SDE_DEBUG("affected displays 0x%x\n", disp_bitmask); |
| 932 | |
| 933 | return disp_bitmask; |
| 934 | } |
| 935 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 936 | static int _sde_crtc_check_rois_centered_and_symmetric(struct drm_crtc *crtc, |
| 937 | struct drm_crtc_state *state) |
| 938 | { |
| 939 | struct sde_crtc *sde_crtc; |
| 940 | struct sde_crtc_state *crtc_state; |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 941 | const struct sde_rect *roi[CRTC_DUAL_MIXERS]; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 942 | |
| 943 | if (!crtc || !state) |
| 944 | return -EINVAL; |
| 945 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 946 | sde_crtc = to_sde_crtc(crtc); |
| 947 | crtc_state = to_sde_crtc_state(state); |
| 948 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 949 | if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) { |
| 950 | SDE_ERROR("%s: unsupported number of mixers: %d\n", |
| 951 | sde_crtc->name, sde_crtc->num_mixers); |
| 952 | return -EINVAL; |
| 953 | } |
| 954 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 955 | /* |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 956 | * If using pingpong split: one ROI, one LM, two physical displays |
| 957 | * then the ROI must be centered on the panel split boundary and |
| 958 | * be of equal width across the split. |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 959 | */ |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 960 | if (crtc_state->is_ppsplit) { |
| 961 | u16 panel_split_width; |
| 962 | u32 display_mask; |
| 963 | |
| 964 | roi[0] = &crtc_state->lm_roi[0]; |
| 965 | |
| 966 | if (sde_kms_rect_is_null(roi[0])) |
| 967 | return 0; |
| 968 | |
| 969 | display_mask = _sde_crtc_get_displays_affected(crtc, state); |
| 970 | if (display_mask != (BIT(0) | BIT(1))) |
| 971 | return 0; |
| 972 | |
| 973 | panel_split_width = crtc_state->lm_bounds[0].w / 2; |
| 974 | if (roi[0]->x + roi[0]->w / 2 != panel_split_width) { |
| 975 | SDE_ERROR("%s: roi x %d w %d split %d\n", |
| 976 | sde_crtc->name, roi[0]->x, roi[0]->w, |
| 977 | panel_split_width); |
| 978 | return -EINVAL; |
| 979 | } |
| 980 | |
| 981 | return 0; |
| 982 | } |
| 983 | |
| 984 | /* |
| 985 | * On certain HW, if using 2 LM, ROIs must be split evenly between the |
| 986 | * LMs and be of equal width. |
| 987 | */ |
| 988 | if (sde_crtc->num_mixers == 1) |
| 989 | return 0; |
| 990 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 991 | roi[0] = &crtc_state->lm_roi[0]; |
| 992 | roi[1] = &crtc_state->lm_roi[1]; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 993 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 994 | /* if one of the roi is null it's a left/right-only update */ |
| 995 | if (sde_kms_rect_is_null(roi[0]) || sde_kms_rect_is_null(roi[1])) |
| 996 | return 0; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 997 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 998 | /* check lm rois are equal width & first roi ends at 2nd roi */ |
| 999 | if (roi[0]->x + roi[0]->w != roi[1]->x || roi[0]->w != roi[1]->w) { |
| 1000 | SDE_ERROR( |
| 1001 | "%s: rois not centered and symmetric: roi0 x %d w %d roi1 x %d w %d\n", |
| 1002 | sde_crtc->name, roi[0]->x, roi[0]->w, |
| 1003 | roi[1]->x, roi[1]->w); |
| 1004 | return -EINVAL; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1005 | } |
| 1006 | |
| 1007 | return 0; |
| 1008 | } |
| 1009 | |
| 1010 | static int _sde_crtc_check_planes_within_crtc_roi(struct drm_crtc *crtc, |
| 1011 | struct drm_crtc_state *state) |
| 1012 | { |
| 1013 | struct sde_crtc *sde_crtc; |
| 1014 | struct sde_crtc_state *crtc_state; |
| 1015 | const struct sde_rect *crtc_roi; |
| 1016 | struct drm_plane_state *pstate; |
| 1017 | struct drm_plane *plane; |
| 1018 | |
| 1019 | if (!crtc || !state) |
| 1020 | return -EINVAL; |
| 1021 | |
| 1022 | /* |
| 1023 | * Reject commit if a Plane CRTC destination coordinates fall outside |
| 1024 | * the partial CRTC ROI. LM output is determined via connector ROIs, |
| 1025 | * if they are specified, not Plane CRTC ROIs. |
| 1026 | */ |
| 1027 | |
| 1028 | sde_crtc = to_sde_crtc(crtc); |
| 1029 | crtc_state = to_sde_crtc_state(state); |
| 1030 | crtc_roi = &crtc_state->crtc_roi; |
| 1031 | |
| 1032 | if (sde_kms_rect_is_null(crtc_roi)) |
| 1033 | return 0; |
| 1034 | |
| 1035 | drm_atomic_crtc_state_for_each_plane(plane, state) { |
| 1036 | struct sde_rect plane_roi, intersection; |
| 1037 | |
| 1038 | pstate = drm_atomic_get_plane_state(state->state, plane); |
| 1039 | if (IS_ERR_OR_NULL(pstate)) { |
| 1040 | int rc = PTR_ERR(pstate); |
| 1041 | |
| 1042 | SDE_ERROR("%s: failed to get plane%d state, %d\n", |
| 1043 | sde_crtc->name, plane->base.id, rc); |
| 1044 | return rc; |
| 1045 | } |
| 1046 | |
| 1047 | plane_roi.x = pstate->crtc_x; |
| 1048 | plane_roi.y = pstate->crtc_y; |
| 1049 | plane_roi.w = pstate->crtc_w; |
| 1050 | plane_roi.h = pstate->crtc_h; |
| 1051 | sde_kms_rect_intersect(crtc_roi, &plane_roi, &intersection); |
| 1052 | if (!sde_kms_rect_is_equal(&plane_roi, &intersection)) { |
| 1053 | SDE_ERROR( |
| 1054 | "%s: plane%d crtc roi (%d,%d,%d,%d) outside crtc roi (%d,%d,%d,%d)\n", |
| 1055 | sde_crtc->name, plane->base.id, |
| 1056 | plane_roi.x, plane_roi.y, |
| 1057 | plane_roi.w, plane_roi.h, |
| 1058 | crtc_roi->x, crtc_roi->y, |
| 1059 | crtc_roi->w, crtc_roi->h); |
| 1060 | return -E2BIG; |
| 1061 | } |
| 1062 | } |
| 1063 | |
| 1064 | return 0; |
| 1065 | } |
| 1066 | |
| 1067 | static int _sde_crtc_check_rois(struct drm_crtc *crtc, |
| 1068 | struct drm_crtc_state *state) |
| 1069 | { |
| 1070 | struct sde_crtc *sde_crtc; |
| 1071 | int lm_idx; |
| 1072 | int rc; |
| 1073 | |
| 1074 | if (!crtc || !state) |
| 1075 | return -EINVAL; |
| 1076 | |
| 1077 | sde_crtc = to_sde_crtc(crtc); |
| 1078 | |
| 1079 | rc = _sde_crtc_set_crtc_roi(crtc, state); |
| 1080 | if (rc) |
| 1081 | return rc; |
| 1082 | |
Lloyd Atkinson | 7738220 | 2017-02-01 14:59:43 -0500 | [diff] [blame] | 1083 | rc = _sde_crtc_check_autorefresh(crtc, state); |
| 1084 | if (rc) |
| 1085 | return rc; |
| 1086 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1087 | for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) { |
| 1088 | rc = _sde_crtc_set_lm_roi(crtc, state, lm_idx); |
| 1089 | if (rc) |
| 1090 | return rc; |
| 1091 | } |
| 1092 | |
| 1093 | rc = _sde_crtc_check_rois_centered_and_symmetric(crtc, state); |
| 1094 | if (rc) |
| 1095 | return rc; |
| 1096 | |
| 1097 | rc = _sde_crtc_check_planes_within_crtc_roi(crtc, state); |
| 1098 | if (rc) |
| 1099 | return rc; |
| 1100 | |
| 1101 | return 0; |
| 1102 | } |
| 1103 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1104 | static void _sde_crtc_program_lm_output_roi(struct drm_crtc *crtc) |
| 1105 | { |
| 1106 | struct sde_crtc *sde_crtc; |
| 1107 | struct sde_crtc_state *crtc_state; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1108 | const struct sde_rect *lm_roi; |
| 1109 | struct sde_hw_mixer *hw_lm; |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1110 | int lm_idx, lm_horiz_position; |
| 1111 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1112 | if (!crtc) |
| 1113 | return; |
| 1114 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1115 | sde_crtc = to_sde_crtc(crtc); |
| 1116 | crtc_state = to_sde_crtc_state(crtc->state); |
| 1117 | |
| 1118 | lm_horiz_position = 0; |
| 1119 | for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) { |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1120 | struct sde_hw_mixer_cfg cfg; |
| 1121 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1122 | lm_roi = &crtc_state->lm_roi[lm_idx]; |
| 1123 | hw_lm = sde_crtc->mixers[lm_idx].hw_lm; |
| 1124 | |
| 1125 | SDE_EVT32(DRMID(crtc_state->base.crtc), lm_idx, |
| 1126 | lm_roi->x, lm_roi->y, lm_roi->w, lm_roi->h); |
| 1127 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1128 | if (sde_kms_rect_is_null(lm_roi)) |
| 1129 | continue; |
| 1130 | |
Ping Li | f41c2ef | 2017-05-04 14:40:45 -0700 | [diff] [blame] | 1131 | hw_lm->cfg.out_width = lm_roi->w; |
| 1132 | hw_lm->cfg.out_height = lm_roi->h; |
| 1133 | hw_lm->cfg.right_mixer = lm_horiz_position; |
| 1134 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1135 | cfg.out_width = lm_roi->w; |
| 1136 | cfg.out_height = lm_roi->h; |
| 1137 | cfg.right_mixer = lm_horiz_position++; |
| 1138 | cfg.flags = 0; |
| 1139 | hw_lm->ops.setup_mixer_out(hw_lm, &cfg); |
| 1140 | } |
| 1141 | } |
| 1142 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1143 | static void _sde_crtc_blend_setup_mixer(struct drm_crtc *crtc, |
| 1144 | struct sde_crtc *sde_crtc, struct sde_crtc_mixer *mixer) |
| 1145 | { |
| 1146 | struct drm_plane *plane; |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1147 | struct drm_framebuffer *fb; |
| 1148 | struct drm_plane_state *state; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1149 | struct sde_crtc_state *cstate; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1150 | struct sde_plane_state *pstate = NULL; |
| 1151 | struct sde_format *format; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1152 | struct sde_hw_ctl *ctl; |
| 1153 | struct sde_hw_mixer *lm; |
| 1154 | struct sde_hw_stage_cfg *stage_cfg; |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1155 | struct sde_rect plane_crtc_roi; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1156 | |
Clarence Ip | 7e5f000 | 2017-05-29 18:46:56 -0400 | [diff] [blame] | 1157 | u32 flush_mask, flush_sbuf, flush_tmp; |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1158 | uint32_t stage_idx, lm_idx; |
| 1159 | int zpos_cnt[SDE_STAGE_MAX + 1] = { 0 }; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1160 | int i; |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1161 | bool bg_alpha_enable = false; |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 1162 | u32 prefill = 0; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1163 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1164 | if (!sde_crtc || !mixer) { |
| 1165 | SDE_ERROR("invalid sde_crtc or mixer\n"); |
| 1166 | return; |
| 1167 | } |
| 1168 | |
| 1169 | ctl = mixer->hw_ctl; |
| 1170 | lm = mixer->hw_lm; |
| 1171 | stage_cfg = &sde_crtc->stage_cfg; |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1172 | cstate = to_sde_crtc_state(crtc->state); |
Clarence Ip | 7e5f000 | 2017-05-29 18:46:56 -0400 | [diff] [blame] | 1173 | flush_sbuf = 0x0; |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1174 | |
Clarence Ip | 7eb9045 | 2017-05-23 11:41:19 -0400 | [diff] [blame] | 1175 | cstate->sbuf_cfg.rot_op_mode = SDE_CTL_ROT_OP_MODE_OFFLINE; |
| 1176 | cstate->sbuf_prefill_line = 0; |
| 1177 | |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1178 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1179 | state = plane->state; |
| 1180 | if (!state) |
| 1181 | continue; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1182 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1183 | plane_crtc_roi.x = state->crtc_x; |
| 1184 | plane_crtc_roi.y = state->crtc_y; |
| 1185 | plane_crtc_roi.w = state->crtc_w; |
| 1186 | plane_crtc_roi.h = state->crtc_h; |
| 1187 | |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1188 | pstate = to_sde_plane_state(state); |
| 1189 | fb = state->fb; |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1190 | |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 1191 | if (sde_plane_is_sbuf_mode(plane, &prefill)) |
Clarence Ip | 7eb9045 | 2017-05-23 11:41:19 -0400 | [diff] [blame] | 1192 | cstate->sbuf_cfg.rot_op_mode = |
| 1193 | SDE_CTL_ROT_OP_MODE_INLINE_SYNC; |
| 1194 | if (prefill > cstate->sbuf_prefill_line) |
| 1195 | cstate->sbuf_prefill_line = prefill; |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 1196 | |
Clarence Ip | 7e5f000 | 2017-05-29 18:46:56 -0400 | [diff] [blame] | 1197 | sde_plane_get_ctl_flush(plane, ctl, &flush_mask, &flush_tmp); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1198 | |
Clarence Ip | 7e5f000 | 2017-05-29 18:46:56 -0400 | [diff] [blame] | 1199 | /* persist rotator flush bit(s) for one more commit */ |
| 1200 | flush_mask |= cstate->sbuf_flush_mask | flush_tmp; |
| 1201 | flush_sbuf |= flush_tmp; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1202 | |
| 1203 | SDE_DEBUG("crtc %d stage:%d - plane %d sspp %d fb %d\n", |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 1204 | crtc->base.id, |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 1205 | pstate->stage, |
| 1206 | plane->base.id, |
| 1207 | sde_plane_pipe(plane) - SSPP_VIG0, |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1208 | state->fb ? state->fb->base.id : -1); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1209 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1210 | format = to_sde_format(msm_framebuffer_format(pstate->base.fb)); |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1211 | if (pstate->stage == SDE_STAGE_BASE && format->alpha_enable) |
| 1212 | bg_alpha_enable = true; |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1213 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1214 | SDE_EVT32(DRMID(crtc), DRMID(plane), |
| 1215 | state->fb ? state->fb->base.id : -1, |
| 1216 | state->src_x >> 16, state->src_y >> 16, |
| 1217 | state->src_w >> 16, state->src_h >> 16, |
| 1218 | state->crtc_x, state->crtc_y, |
Clarence Ip | 7eb9045 | 2017-05-23 11:41:19 -0400 | [diff] [blame] | 1219 | state->crtc_w, state->crtc_h, |
| 1220 | cstate->sbuf_cfg.rot_op_mode); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1221 | |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1222 | stage_idx = zpos_cnt[pstate->stage]++; |
| 1223 | stage_cfg->stage[pstate->stage][stage_idx] = |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1224 | sde_plane_pipe(plane); |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1225 | stage_cfg->multirect_index[pstate->stage][stage_idx] = |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1226 | pstate->multirect_index; |
| 1227 | |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1228 | SDE_EVT32(DRMID(crtc), DRMID(plane), stage_idx, |
| 1229 | sde_plane_pipe(plane) - SSPP_VIG0, pstate->stage, |
| 1230 | pstate->multirect_index, pstate->multirect_mode, |
| 1231 | format->base.pixel_format, fb ? fb->modifier[0] : 0); |
| 1232 | |
| 1233 | /* blend config update */ |
| 1234 | for (lm_idx = 0; lm_idx < sde_crtc->num_mixers; lm_idx++) { |
| 1235 | _sde_crtc_setup_blend_cfg(mixer + lm_idx, pstate, |
| 1236 | format); |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1237 | mixer[lm_idx].flush_mask |= flush_mask; |
| 1238 | |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1239 | if (bg_alpha_enable && !format->alpha_enable) |
| 1240 | mixer[lm_idx].mixer_op_mode = 0; |
| 1241 | else |
| 1242 | mixer[lm_idx].mixer_op_mode |= |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1243 | 1 << pstate->stage; |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1244 | } |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1245 | } |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1246 | |
Clarence Ip | 7e5f000 | 2017-05-29 18:46:56 -0400 | [diff] [blame] | 1247 | cstate->sbuf_flush_mask = flush_sbuf; |
| 1248 | |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1249 | if (lm && lm->ops.setup_dim_layer) { |
| 1250 | cstate = to_sde_crtc_state(crtc->state); |
| 1251 | for (i = 0; i < cstate->num_dim_layers; i++) |
| 1252 | _sde_crtc_setup_dim_layer_cfg(crtc, sde_crtc, |
| 1253 | mixer, &cstate->dim_layer[i]); |
| 1254 | } |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 1255 | |
Clarence Ip | 7eb9045 | 2017-05-23 11:41:19 -0400 | [diff] [blame] | 1256 | if (ctl->ops.setup_sbuf_cfg) |
Alan Kwong | 4dd64c8 | 2017-02-04 18:41:51 -0800 | [diff] [blame] | 1257 | ctl->ops.setup_sbuf_cfg(ctl, &cstate->sbuf_cfg); |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1258 | |
| 1259 | _sde_crtc_program_lm_output_roi(crtc); |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1260 | } |
| 1261 | |
Lloyd Atkinson | 094780d | 2017-04-24 17:25:08 -0400 | [diff] [blame] | 1262 | static void _sde_crtc_swap_mixers_for_right_partial_update( |
| 1263 | struct drm_crtc *crtc) |
| 1264 | { |
| 1265 | struct sde_crtc *sde_crtc; |
| 1266 | struct sde_crtc_state *cstate; |
| 1267 | struct drm_encoder *drm_enc; |
| 1268 | bool is_right_only; |
| 1269 | bool encoder_in_dsc_merge = false; |
| 1270 | |
| 1271 | if (!crtc || !crtc->state) |
| 1272 | return; |
| 1273 | |
| 1274 | sde_crtc = to_sde_crtc(crtc); |
| 1275 | cstate = to_sde_crtc_state(crtc->state); |
| 1276 | |
| 1277 | if (sde_crtc->num_mixers != CRTC_DUAL_MIXERS) |
| 1278 | return; |
| 1279 | |
| 1280 | drm_for_each_encoder(drm_enc, crtc->dev) { |
| 1281 | if (drm_enc->crtc == crtc && |
| 1282 | sde_encoder_is_dsc_merge(drm_enc)) { |
| 1283 | encoder_in_dsc_merge = true; |
| 1284 | break; |
| 1285 | } |
| 1286 | } |
| 1287 | |
| 1288 | /** |
| 1289 | * For right-only partial update with DSC merge, we swap LM0 & LM1. |
| 1290 | * This is due to two reasons: |
| 1291 | * - On 8996, there is a DSC HW requirement that in DSC Merge Mode, |
| 1292 | * the left DSC must be used, right DSC cannot be used alone. |
| 1293 | * For right-only partial update, this means swap layer mixers to map |
| 1294 | * Left LM to Right INTF. On later HW this was relaxed. |
| 1295 | * - In DSC Merge mode, the physical encoder has already registered |
| 1296 | * PP0 as the master, to switch to right-only we would have to |
| 1297 | * reprogram to be driven by PP1 instead. |
| 1298 | * To support both cases, we prefer to support the mixer swap solution. |
| 1299 | */ |
| 1300 | if (!encoder_in_dsc_merge) |
| 1301 | return; |
| 1302 | |
| 1303 | is_right_only = sde_kms_rect_is_null(&cstate->lm_roi[0]) && |
| 1304 | !sde_kms_rect_is_null(&cstate->lm_roi[1]); |
| 1305 | |
| 1306 | if (is_right_only && !sde_crtc->mixers_swapped) { |
| 1307 | /* right-only update swap mixers */ |
| 1308 | swap(sde_crtc->mixers[0], sde_crtc->mixers[1]); |
| 1309 | sde_crtc->mixers_swapped = true; |
| 1310 | } else if (!is_right_only && sde_crtc->mixers_swapped) { |
| 1311 | /* left-only or full update, swap back */ |
| 1312 | swap(sde_crtc->mixers[0], sde_crtc->mixers[1]); |
| 1313 | sde_crtc->mixers_swapped = false; |
| 1314 | } |
| 1315 | |
| 1316 | SDE_DEBUG("%s: right_only %d swapped %d, mix0->lm%d, mix1->lm%d\n", |
| 1317 | sde_crtc->name, is_right_only, sde_crtc->mixers_swapped, |
| 1318 | sde_crtc->mixers[0].hw_lm->idx - LM_0, |
| 1319 | sde_crtc->mixers[1].hw_lm->idx - LM_0); |
| 1320 | SDE_EVT32(DRMID(crtc), is_right_only, sde_crtc->mixers_swapped, |
| 1321 | sde_crtc->mixers[0].hw_lm->idx - LM_0, |
| 1322 | sde_crtc->mixers[1].hw_lm->idx - LM_0); |
| 1323 | } |
| 1324 | |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 1325 | /** |
| 1326 | * _sde_crtc_blend_setup - configure crtc mixers |
| 1327 | * @crtc: Pointer to drm crtc structure |
| 1328 | */ |
| 1329 | static void _sde_crtc_blend_setup(struct drm_crtc *crtc) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1330 | { |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1331 | struct sde_crtc *sde_crtc; |
| 1332 | struct sde_crtc_state *sde_crtc_state; |
| 1333 | struct sde_crtc_mixer *mixer; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1334 | struct sde_hw_ctl *ctl; |
| 1335 | struct sde_hw_mixer *lm; |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 1336 | |
| 1337 | int i; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1338 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1339 | if (!crtc) |
| 1340 | return; |
| 1341 | |
| 1342 | sde_crtc = to_sde_crtc(crtc); |
| 1343 | sde_crtc_state = to_sde_crtc_state(crtc->state); |
| 1344 | mixer = sde_crtc->mixers; |
| 1345 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1346 | SDE_DEBUG("%s\n", sde_crtc->name); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1347 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1348 | if (sde_crtc->num_mixers > CRTC_DUAL_MIXERS) { |
| 1349 | SDE_ERROR("invalid number mixers: %d\n", sde_crtc->num_mixers); |
| 1350 | return; |
| 1351 | } |
| 1352 | |
| 1353 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
| 1354 | if (!mixer[i].hw_lm || !mixer[i].hw_ctl) { |
| 1355 | SDE_ERROR("invalid lm or ctl assigned to mixer\n"); |
| 1356 | return; |
| 1357 | } |
| 1358 | mixer[i].mixer_op_mode = 0; |
| 1359 | mixer[i].flush_mask = 0; |
Lloyd Atkinson | e5ec30d | 2016-08-23 14:32:32 -0400 | [diff] [blame] | 1360 | if (mixer[i].hw_ctl->ops.clear_all_blendstages) |
| 1361 | mixer[i].hw_ctl->ops.clear_all_blendstages( |
| 1362 | mixer[i].hw_ctl); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1363 | |
| 1364 | /* clear dim_layer settings */ |
| 1365 | lm = mixer[i].hw_lm; |
| 1366 | if (lm->ops.clear_dim_layer) |
| 1367 | lm->ops.clear_dim_layer(lm); |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1368 | } |
| 1369 | |
Lloyd Atkinson | 094780d | 2017-04-24 17:25:08 -0400 | [diff] [blame] | 1370 | _sde_crtc_swap_mixers_for_right_partial_update(crtc); |
| 1371 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1372 | /* initialize stage cfg */ |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 1373 | memset(&sde_crtc->stage_cfg, 0, sizeof(struct sde_hw_stage_cfg)); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1374 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1375 | _sde_crtc_blend_setup_mixer(crtc, sde_crtc, mixer); |
| 1376 | |
Abhijit Kulkarni | 71002ba | 2016-06-24 18:36:28 -0400 | [diff] [blame] | 1377 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1378 | const struct sde_rect *lm_roi = &sde_crtc_state->lm_roi[i]; |
| 1379 | |
Abhijit Kulkarni | 71002ba | 2016-06-24 18:36:28 -0400 | [diff] [blame] | 1380 | ctl = mixer[i].hw_ctl; |
| 1381 | lm = mixer[i].hw_lm; |
Abhijit Kulkarni | 71002ba | 2016-06-24 18:36:28 -0400 | [diff] [blame] | 1382 | |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 1383 | if (sde_kms_rect_is_null(lm_roi)) { |
| 1384 | SDE_DEBUG( |
| 1385 | "%s: lm%d leave ctl%d mask 0 since null roi\n", |
| 1386 | sde_crtc->name, lm->idx - LM_0, |
| 1387 | ctl->idx - CTL_0); |
| 1388 | continue; |
| 1389 | } |
| 1390 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1391 | lm->ops.setup_alpha_out(lm, mixer[i].mixer_op_mode); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1392 | |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1393 | mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl, |
Abhijit Kulkarni | 71002ba | 2016-06-24 18:36:28 -0400 | [diff] [blame] | 1394 | mixer[i].hw_lm->idx); |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1395 | |
| 1396 | /* stage config flush mask */ |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 1397 | ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); |
| 1398 | |
Clarence Ip | 8e69ad0 | 2016-12-09 09:43:57 -0500 | [diff] [blame] | 1399 | SDE_DEBUG("lm %d, op_mode 0x%X, ctl %d, flush mask 0x%x\n", |
| 1400 | mixer[i].hw_lm->idx - LM_0, |
| 1401 | mixer[i].mixer_op_mode, |
| 1402 | ctl->idx - CTL_0, |
| 1403 | mixer[i].flush_mask); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1404 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1405 | ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, |
Dhaval Patel | 572cfd2 | 2017-06-12 19:33:39 -0700 | [diff] [blame] | 1406 | &sde_crtc->stage_cfg); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1407 | } |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1408 | |
| 1409 | _sde_crtc_program_lm_output_roi(crtc); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1410 | } |
| 1411 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1412 | void sde_crtc_prepare_commit(struct drm_crtc *crtc, |
| 1413 | struct drm_crtc_state *old_state) |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1414 | { |
| 1415 | struct sde_crtc *sde_crtc; |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1416 | struct sde_crtc_state *cstate; |
| 1417 | struct drm_connector *conn; |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1418 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1419 | if (!crtc || !crtc->state) { |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1420 | SDE_ERROR("invalid crtc\n"); |
| 1421 | return; |
| 1422 | } |
| 1423 | |
| 1424 | sde_crtc = to_sde_crtc(crtc); |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1425 | cstate = to_sde_crtc_state(crtc->state); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1426 | SDE_EVT32_VERBOSE(DRMID(crtc)); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1427 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1428 | /* identify connectors attached to this crtc */ |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1429 | cstate->num_connectors = 0; |
| 1430 | |
| 1431 | drm_for_each_connector(conn, crtc->dev) |
| 1432 | if (conn->state && conn->state->crtc == crtc && |
| 1433 | cstate->num_connectors < MAX_CONNECTORS) { |
| 1434 | cstate->connectors[cstate->num_connectors++] = conn; |
| 1435 | sde_connector_prepare_fence(conn); |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1436 | } |
| 1437 | |
| 1438 | /* prepare main output fence */ |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1439 | sde_fence_prepare(&sde_crtc->output_fence); |
| 1440 | } |
| 1441 | |
Abhinav Kumar | f2e94b5 | 2017-02-09 20:27:24 -0800 | [diff] [blame] | 1442 | /** |
| 1443 | * _sde_crtc_complete_flip - signal pending page_flip events |
| 1444 | * Any pending vblank events are added to the vblank_event_list |
| 1445 | * so that the next vblank interrupt shall signal them. |
| 1446 | * However PAGE_FLIP events are not handled through the vblank_event_list. |
| 1447 | * This API signals any pending PAGE_FLIP events requested through |
| 1448 | * DRM_IOCTL_MODE_PAGE_FLIP and are cached in the sde_crtc->event. |
| 1449 | * if file!=NULL, this is preclose potential cancel-flip path |
| 1450 | * @crtc: Pointer to drm crtc structure |
| 1451 | * @file: Pointer to drm file |
| 1452 | */ |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 1453 | static void _sde_crtc_complete_flip(struct drm_crtc *crtc, |
| 1454 | struct drm_file *file) |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 1455 | { |
| 1456 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 1457 | struct drm_device *dev = crtc->dev; |
| 1458 | struct drm_pending_vblank_event *event; |
| 1459 | unsigned long flags; |
| 1460 | |
| 1461 | spin_lock_irqsave(&dev->event_lock, flags); |
| 1462 | event = sde_crtc->event; |
| 1463 | if (event) { |
| 1464 | /* if regular vblank case (!file) or if cancel-flip from |
| 1465 | * preclose on file that requested flip, then send the |
| 1466 | * event: |
| 1467 | */ |
| 1468 | if (!file || (event->base.file_priv == file)) { |
| 1469 | sde_crtc->event = NULL; |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 1470 | DRM_DEBUG_VBL("%s: send event: %pK\n", |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 1471 | sde_crtc->name, event); |
Lloyd Atkinson | 5d40d31 | 2016-09-06 08:34:13 -0400 | [diff] [blame] | 1472 | SDE_EVT32(DRMID(crtc)); |
Lloyd Atkinson | ac93364 | 2016-09-14 11:52:00 -0400 | [diff] [blame] | 1473 | drm_crtc_send_vblank_event(crtc, event); |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 1474 | } |
| 1475 | } |
| 1476 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 1477 | } |
| 1478 | |
Alan Kwong | 3e985f0 | 2017-02-12 15:08:44 -0800 | [diff] [blame] | 1479 | enum sde_intf_mode sde_crtc_get_intf_mode(struct drm_crtc *crtc) |
| 1480 | { |
| 1481 | struct drm_encoder *encoder; |
| 1482 | |
| 1483 | if (!crtc || !crtc->dev) { |
| 1484 | SDE_ERROR("invalid crtc\n"); |
| 1485 | return INTF_MODE_NONE; |
| 1486 | } |
| 1487 | |
| 1488 | drm_for_each_encoder(encoder, crtc->dev) |
| 1489 | if (encoder->crtc == crtc) |
| 1490 | return sde_encoder_get_intf_mode(encoder); |
| 1491 | |
| 1492 | return INTF_MODE_NONE; |
| 1493 | } |
| 1494 | |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 1495 | static void sde_crtc_vblank_cb(void *data) |
| 1496 | { |
| 1497 | struct drm_crtc *crtc = (struct drm_crtc *)data; |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 1498 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 1499 | |
| 1500 | /* keep statistics on vblank callback - with auto reset via debugfs */ |
| 1501 | if (ktime_equal(sde_crtc->vblank_cb_time, ktime_set(0, 0))) |
| 1502 | sde_crtc->vblank_cb_time = ktime_get(); |
| 1503 | else |
| 1504 | sde_crtc->vblank_cb_count++; |
Abhinav Kumar | f2e94b5 | 2017-02-09 20:27:24 -0800 | [diff] [blame] | 1505 | _sde_crtc_complete_flip(crtc, NULL); |
Lloyd Atkinson | ac93364 | 2016-09-14 11:52:00 -0400 | [diff] [blame] | 1506 | drm_crtc_handle_vblank(crtc); |
Lloyd Atkinson | 9eabe7a | 2016-09-14 13:39:15 -0400 | [diff] [blame] | 1507 | DRM_DEBUG_VBL("crtc%d\n", crtc->base.id); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1508 | SDE_EVT32_VERBOSE(DRMID(crtc)); |
Abhijit Kulkarni | 40e3816 | 2016-06-26 22:12:09 -0400 | [diff] [blame] | 1509 | } |
| 1510 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1511 | static void sde_crtc_frame_event_work(struct kthread_work *work) |
| 1512 | { |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 1513 | struct msm_drm_private *priv; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1514 | struct sde_crtc_frame_event *fevent; |
| 1515 | struct drm_crtc *crtc; |
| 1516 | struct sde_crtc *sde_crtc; |
Alan Kwong | a193968 | 2017-05-05 11:30:08 -0700 | [diff] [blame] | 1517 | struct sde_crtc_state *cstate; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1518 | struct sde_kms *sde_kms; |
| 1519 | unsigned long flags; |
Ingrid Gallardo | 79b4439 | 2017-05-30 16:30:52 -0700 | [diff] [blame] | 1520 | bool disable_inprogress = false; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1521 | |
| 1522 | if (!work) { |
| 1523 | SDE_ERROR("invalid work handle\n"); |
| 1524 | return; |
| 1525 | } |
| 1526 | |
| 1527 | fevent = container_of(work, struct sde_crtc_frame_event, work); |
Alan Kwong | a193968 | 2017-05-05 11:30:08 -0700 | [diff] [blame] | 1528 | if (!fevent->crtc || !fevent->crtc->state) { |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1529 | SDE_ERROR("invalid crtc\n"); |
| 1530 | return; |
| 1531 | } |
| 1532 | |
| 1533 | crtc = fevent->crtc; |
| 1534 | sde_crtc = to_sde_crtc(crtc); |
Alan Kwong | a193968 | 2017-05-05 11:30:08 -0700 | [diff] [blame] | 1535 | cstate = to_sde_crtc_state(crtc->state); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1536 | |
| 1537 | sde_kms = _sde_crtc_get_kms(crtc); |
| 1538 | if (!sde_kms) { |
| 1539 | SDE_ERROR("invalid kms handle\n"); |
| 1540 | return; |
| 1541 | } |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 1542 | priv = sde_kms->dev->dev_private; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1543 | |
| 1544 | SDE_DEBUG("crtc%d event:%u ts:%lld\n", crtc->base.id, fevent->event, |
| 1545 | ktime_to_ns(fevent->ts)); |
Ingrid Gallardo | 79b4439 | 2017-05-30 16:30:52 -0700 | [diff] [blame] | 1546 | disable_inprogress = fevent->event & |
| 1547 | SDE_ENCODER_FRAME_EVENT_DURING_DISABLE; |
| 1548 | fevent->event &= ~SDE_ENCODER_FRAME_EVENT_DURING_DISABLE; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1549 | |
| 1550 | if (fevent->event == SDE_ENCODER_FRAME_EVENT_DONE || |
Lloyd Atkinson | 8c49c58 | 2016-11-18 14:23:54 -0500 | [diff] [blame] | 1551 | (fevent->event & SDE_ENCODER_FRAME_EVENT_ERROR) || |
| 1552 | (fevent->event & SDE_ENCODER_FRAME_EVENT_PANEL_DEAD)) { |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1553 | |
| 1554 | if (atomic_read(&sde_crtc->frame_pending) < 1) { |
| 1555 | /* this should not happen */ |
| 1556 | SDE_ERROR("crtc%d ts:%lld invalid frame_pending:%d\n", |
| 1557 | crtc->base.id, |
| 1558 | ktime_to_ns(fevent->ts), |
| 1559 | atomic_read(&sde_crtc->frame_pending)); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1560 | SDE_EVT32(DRMID(crtc), fevent->event, |
| 1561 | SDE_EVTLOG_FUNC_CASE1); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1562 | } else if (atomic_dec_return(&sde_crtc->frame_pending) == 0) { |
| 1563 | /* release bandwidth and other resources */ |
| 1564 | SDE_DEBUG("crtc%d ts:%lld last pending\n", |
| 1565 | crtc->base.id, |
| 1566 | ktime_to_ns(fevent->ts)); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1567 | SDE_EVT32(DRMID(crtc), fevent->event, |
| 1568 | SDE_EVTLOG_FUNC_CASE2); |
Ingrid Gallardo | 79b4439 | 2017-05-30 16:30:52 -0700 | [diff] [blame] | 1569 | if (!disable_inprogress) |
| 1570 | sde_core_perf_crtc_release_bw(crtc); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1571 | } else { |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1572 | SDE_EVT32_VERBOSE(DRMID(crtc), fevent->event, |
| 1573 | SDE_EVTLOG_FUNC_CASE3); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1574 | } |
Alan Kwong | a193968 | 2017-05-05 11:30:08 -0700 | [diff] [blame] | 1575 | |
Ingrid Gallardo | 79b4439 | 2017-05-30 16:30:52 -0700 | [diff] [blame] | 1576 | if (fevent->event == SDE_ENCODER_FRAME_EVENT_DONE && |
| 1577 | !disable_inprogress) |
Alan Kwong | a193968 | 2017-05-05 11:30:08 -0700 | [diff] [blame] | 1578 | sde_core_perf_crtc_update(crtc, 0, false); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1579 | } else { |
| 1580 | SDE_ERROR("crtc%d ts:%lld unknown event %u\n", crtc->base.id, |
| 1581 | ktime_to_ns(fevent->ts), |
| 1582 | fevent->event); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1583 | SDE_EVT32(DRMID(crtc), fevent->event, SDE_EVTLOG_FUNC_CASE4); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1584 | } |
| 1585 | |
Lloyd Atkinson | 8c49c58 | 2016-11-18 14:23:54 -0500 | [diff] [blame] | 1586 | if (fevent->event & SDE_ENCODER_FRAME_EVENT_PANEL_DEAD) |
| 1587 | SDE_ERROR("crtc%d ts:%lld received panel dead event\n", |
| 1588 | crtc->base.id, ktime_to_ns(fevent->ts)); |
| 1589 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1590 | spin_lock_irqsave(&sde_crtc->spin_lock, flags); |
| 1591 | list_add_tail(&fevent->list, &sde_crtc->frame_event_list); |
| 1592 | spin_unlock_irqrestore(&sde_crtc->spin_lock, flags); |
| 1593 | } |
| 1594 | |
| 1595 | static void sde_crtc_frame_event_cb(void *data, u32 event) |
| 1596 | { |
| 1597 | struct drm_crtc *crtc = (struct drm_crtc *)data; |
| 1598 | struct sde_crtc *sde_crtc; |
| 1599 | struct msm_drm_private *priv; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1600 | struct sde_crtc_frame_event *fevent; |
| 1601 | unsigned long flags; |
| 1602 | int pipe_id; |
| 1603 | |
| 1604 | if (!crtc || !crtc->dev || !crtc->dev->dev_private) { |
| 1605 | SDE_ERROR("invalid parameters\n"); |
| 1606 | return; |
| 1607 | } |
| 1608 | sde_crtc = to_sde_crtc(crtc); |
| 1609 | priv = crtc->dev->dev_private; |
| 1610 | pipe_id = drm_crtc_index(crtc); |
| 1611 | |
| 1612 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
Ingrid Gallardo | 79b4439 | 2017-05-30 16:30:52 -0700 | [diff] [blame] | 1613 | SDE_EVT32_VERBOSE(DRMID(crtc), event); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1614 | |
| 1615 | spin_lock_irqsave(&sde_crtc->spin_lock, flags); |
Lloyd Atkinson | 78831f8 | 2016-12-09 11:24:56 -0500 | [diff] [blame] | 1616 | fevent = list_first_entry_or_null(&sde_crtc->frame_event_list, |
| 1617 | struct sde_crtc_frame_event, list); |
| 1618 | if (fevent) |
| 1619 | list_del_init(&fevent->list); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1620 | spin_unlock_irqrestore(&sde_crtc->spin_lock, flags); |
| 1621 | |
Lloyd Atkinson | 78831f8 | 2016-12-09 11:24:56 -0500 | [diff] [blame] | 1622 | if (!fevent) { |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1623 | SDE_ERROR("crtc%d event %d overflow\n", |
| 1624 | crtc->base.id, event); |
| 1625 | SDE_EVT32(DRMID(crtc), event); |
| 1626 | return; |
| 1627 | } |
| 1628 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1629 | fevent->event = event; |
| 1630 | fevent->crtc = crtc; |
| 1631 | fevent->ts = ktime_get(); |
Ingrid Gallardo | 79b4439 | 2017-05-30 16:30:52 -0700 | [diff] [blame] | 1632 | if (event & SDE_ENCODER_FRAME_EVENT_DURING_DISABLE) |
| 1633 | sde_crtc_frame_event_work(&fevent->work); |
| 1634 | else |
| 1635 | kthread_queue_work(&priv->disp_thread[pipe_id].worker, |
| 1636 | &fevent->work); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 1637 | } |
| 1638 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1639 | void sde_crtc_complete_commit(struct drm_crtc *crtc, |
| 1640 | struct drm_crtc_state *old_state) |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1641 | { |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1642 | struct sde_crtc *sde_crtc; |
| 1643 | struct sde_crtc_state *cstate; |
| 1644 | int i; |
| 1645 | |
| 1646 | if (!crtc || !crtc->state) { |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1647 | SDE_ERROR("invalid crtc\n"); |
| 1648 | return; |
| 1649 | } |
| 1650 | |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1651 | sde_crtc = to_sde_crtc(crtc); |
| 1652 | cstate = to_sde_crtc_state(crtc->state); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 1653 | SDE_EVT32_VERBOSE(DRMID(crtc)); |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1654 | |
| 1655 | /* signal output fence(s) at end of commit */ |
| 1656 | sde_fence_signal(&sde_crtc->output_fence, 0); |
| 1657 | |
| 1658 | for (i = 0; i < cstate->num_connectors; ++i) |
| 1659 | sde_connector_complete_commit(cstate->connectors[i]); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 1660 | } |
| 1661 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 1662 | /** |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1663 | * _sde_crtc_set_input_fence_timeout - update ns version of in fence timeout |
| 1664 | * @cstate: Pointer to sde crtc state |
| 1665 | */ |
| 1666 | static void _sde_crtc_set_input_fence_timeout(struct sde_crtc_state *cstate) |
| 1667 | { |
| 1668 | if (!cstate) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 1669 | SDE_ERROR("invalid cstate\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1670 | return; |
| 1671 | } |
| 1672 | cstate->input_fence_timeout_ns = |
| 1673 | sde_crtc_get_property(cstate, CRTC_PROP_INPUT_FENCE_TIMEOUT); |
| 1674 | cstate->input_fence_timeout_ns *= NSEC_PER_MSEC; |
| 1675 | } |
| 1676 | |
| 1677 | /** |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1678 | * _sde_crtc_set_dim_layer_v1 - copy dim layer settings from userspace |
| 1679 | * @cstate: Pointer to sde crtc state |
| 1680 | * @user_ptr: User ptr for sde_drm_dim_layer_v1 struct |
| 1681 | */ |
| 1682 | static void _sde_crtc_set_dim_layer_v1(struct sde_crtc_state *cstate, |
| 1683 | void *usr_ptr) |
| 1684 | { |
| 1685 | struct sde_drm_dim_layer_v1 dim_layer_v1; |
| 1686 | struct sde_drm_dim_layer_cfg *user_cfg; |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 1687 | struct sde_hw_dim_layer *dim_layer; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1688 | u32 count, i; |
| 1689 | |
| 1690 | if (!cstate) { |
| 1691 | SDE_ERROR("invalid cstate\n"); |
| 1692 | return; |
| 1693 | } |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 1694 | dim_layer = cstate->dim_layer; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1695 | |
| 1696 | if (!usr_ptr) { |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 1697 | SDE_DEBUG("dim_layer data removed\n"); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1698 | return; |
| 1699 | } |
| 1700 | |
| 1701 | if (copy_from_user(&dim_layer_v1, usr_ptr, sizeof(dim_layer_v1))) { |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 1702 | SDE_ERROR("failed to copy dim_layer data\n"); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1703 | return; |
| 1704 | } |
| 1705 | |
| 1706 | count = dim_layer_v1.num_layers; |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 1707 | if (count > SDE_MAX_DIM_LAYERS) { |
| 1708 | SDE_ERROR("invalid number of dim_layers:%d", count); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1709 | return; |
| 1710 | } |
| 1711 | |
| 1712 | /* populate from user space */ |
| 1713 | cstate->num_dim_layers = count; |
| 1714 | for (i = 0; i < count; i++) { |
| 1715 | user_cfg = &dim_layer_v1.layer_cfg[i]; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1716 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 1717 | dim_layer[i].flags = user_cfg->flags; |
| 1718 | dim_layer[i].stage = user_cfg->stage + SDE_STAGE_0; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1719 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 1720 | dim_layer[i].rect.x = user_cfg->rect.x1; |
| 1721 | dim_layer[i].rect.y = user_cfg->rect.y1; |
| 1722 | dim_layer[i].rect.w = user_cfg->rect.x2 - user_cfg->rect.x1; |
| 1723 | dim_layer[i].rect.h = user_cfg->rect.y2 - user_cfg->rect.y1; |
| 1724 | |
| 1725 | dim_layer[i].color_fill = (struct sde_mdss_color) { |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1726 | user_cfg->color_fill.color_0, |
| 1727 | user_cfg->color_fill.color_1, |
| 1728 | user_cfg->color_fill.color_2, |
| 1729 | user_cfg->color_fill.color_3, |
| 1730 | }; |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 1731 | |
| 1732 | SDE_DEBUG("dim_layer[%d] - flags:%d, stage:%d\n", |
| 1733 | i, dim_layer[i].flags, dim_layer[i].stage); |
| 1734 | SDE_DEBUG(" rect:{%d,%d,%d,%d}, color:{%d,%d,%d,%d}\n", |
| 1735 | dim_layer[i].rect.x, dim_layer[i].rect.y, |
| 1736 | dim_layer[i].rect.w, dim_layer[i].rect.h, |
| 1737 | dim_layer[i].color_fill.color_0, |
| 1738 | dim_layer[i].color_fill.color_1, |
| 1739 | dim_layer[i].color_fill.color_2, |
| 1740 | dim_layer[i].color_fill.color_3); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 1741 | } |
| 1742 | } |
| 1743 | |
| 1744 | /** |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1745 | * _sde_crtc_wait_for_fences - wait for incoming framebuffer sync fences |
| 1746 | * @crtc: Pointer to CRTC object |
| 1747 | */ |
| 1748 | static void _sde_crtc_wait_for_fences(struct drm_crtc *crtc) |
| 1749 | { |
| 1750 | struct drm_plane *plane = NULL; |
| 1751 | uint32_t wait_ms = 1; |
Clarence Ip | 8dedc23 | 2016-09-09 16:41:00 -0400 | [diff] [blame] | 1752 | ktime_t kt_end, kt_wait; |
Dhaval Patel | 39323d4 | 2017-03-01 23:48:24 -0800 | [diff] [blame] | 1753 | int rc = 0; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1754 | |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 1755 | SDE_DEBUG("\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1756 | |
| 1757 | if (!crtc || !crtc->state) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 1758 | SDE_ERROR("invalid crtc/state %pK\n", crtc); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1759 | return; |
| 1760 | } |
| 1761 | |
| 1762 | /* use monotonic timer to limit total fence wait time */ |
Clarence Ip | 8dedc23 | 2016-09-09 16:41:00 -0400 | [diff] [blame] | 1763 | kt_end = ktime_add_ns(ktime_get(), |
| 1764 | to_sde_crtc_state(crtc->state)->input_fence_timeout_ns); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1765 | |
| 1766 | /* |
| 1767 | * Wait for fences sequentially, as all of them need to be signalled |
| 1768 | * before we can proceed. |
| 1769 | * |
| 1770 | * Limit total wait time to INPUT_FENCE_TIMEOUT, but still call |
| 1771 | * sde_plane_wait_input_fence with wait_ms == 0 after the timeout so |
| 1772 | * that each plane can check its fence status and react appropriately |
Dhaval Patel | 39323d4 | 2017-03-01 23:48:24 -0800 | [diff] [blame] | 1773 | * if its fence has timed out. Call input fence wait multiple times if |
| 1774 | * fence wait is interrupted due to interrupt call. |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1775 | */ |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 1776 | SDE_ATRACE_BEGIN("plane_wait_input_fence"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1777 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
Dhaval Patel | 39323d4 | 2017-03-01 23:48:24 -0800 | [diff] [blame] | 1778 | do { |
Clarence Ip | 8dedc23 | 2016-09-09 16:41:00 -0400 | [diff] [blame] | 1779 | kt_wait = ktime_sub(kt_end, ktime_get()); |
| 1780 | if (ktime_compare(kt_wait, ktime_set(0, 0)) >= 0) |
| 1781 | wait_ms = ktime_to_ms(kt_wait); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1782 | else |
| 1783 | wait_ms = 0; |
Dhaval Patel | 39323d4 | 2017-03-01 23:48:24 -0800 | [diff] [blame] | 1784 | |
| 1785 | rc = sde_plane_wait_input_fence(plane, wait_ms); |
| 1786 | } while (wait_ms && rc == -ERESTARTSYS); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1787 | } |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 1788 | SDE_ATRACE_END("plane_wait_input_fence"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1789 | } |
| 1790 | |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1791 | static void _sde_crtc_setup_mixer_for_encoder( |
| 1792 | struct drm_crtc *crtc, |
| 1793 | struct drm_encoder *enc) |
| 1794 | { |
| 1795 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 1796 | struct sde_kms *sde_kms = _sde_crtc_get_kms(crtc); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1797 | struct sde_rm *rm = &sde_kms->rm; |
| 1798 | struct sde_crtc_mixer *mixer; |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1799 | struct sde_hw_ctl *last_valid_ctl = NULL; |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1800 | int i; |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 1801 | struct sde_rm_hw_iter lm_iter, ctl_iter, dspp_iter; |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1802 | |
| 1803 | sde_rm_init_hw_iter(&lm_iter, enc->base.id, SDE_HW_BLK_LM); |
| 1804 | sde_rm_init_hw_iter(&ctl_iter, enc->base.id, SDE_HW_BLK_CTL); |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 1805 | sde_rm_init_hw_iter(&dspp_iter, enc->base.id, SDE_HW_BLK_DSPP); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1806 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1807 | /* Set up all the mixers and ctls reserved by this encoder */ |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1808 | for (i = sde_crtc->num_mixers; i < ARRAY_SIZE(sde_crtc->mixers); i++) { |
| 1809 | mixer = &sde_crtc->mixers[i]; |
| 1810 | |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1811 | if (!sde_rm_get_hw(rm, &lm_iter)) |
| 1812 | break; |
| 1813 | mixer->hw_lm = (struct sde_hw_mixer *)lm_iter.hw; |
| 1814 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1815 | /* CTL may be <= LMs, if <, multiple LMs controlled by 1 CTL */ |
| 1816 | if (!sde_rm_get_hw(rm, &ctl_iter)) { |
| 1817 | SDE_DEBUG("no ctl assigned to lm %d, using previous\n", |
Clarence Ip | 8e69ad0 | 2016-12-09 09:43:57 -0500 | [diff] [blame] | 1818 | mixer->hw_lm->idx - LM_0); |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1819 | mixer->hw_ctl = last_valid_ctl; |
| 1820 | } else { |
| 1821 | mixer->hw_ctl = (struct sde_hw_ctl *)ctl_iter.hw; |
| 1822 | last_valid_ctl = mixer->hw_ctl; |
| 1823 | } |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1824 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1825 | /* Shouldn't happen, mixers are always >= ctls */ |
| 1826 | if (!mixer->hw_ctl) { |
| 1827 | SDE_ERROR("no valid ctls found for lm %d\n", |
Clarence Ip | 8e69ad0 | 2016-12-09 09:43:57 -0500 | [diff] [blame] | 1828 | mixer->hw_lm->idx - LM_0); |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1829 | return; |
| 1830 | } |
| 1831 | |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 1832 | /* Dspp may be null */ |
| 1833 | (void) sde_rm_get_hw(rm, &dspp_iter); |
| 1834 | mixer->hw_dspp = (struct sde_hw_dspp *)dspp_iter.hw; |
| 1835 | |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1836 | mixer->encoder = enc; |
| 1837 | |
| 1838 | sde_crtc->num_mixers++; |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 1839 | SDE_DEBUG("setup mixer %d: lm %d\n", |
| 1840 | i, mixer->hw_lm->idx - LM_0); |
| 1841 | SDE_DEBUG("setup mixer %d: ctl %d\n", |
| 1842 | i, mixer->hw_ctl->idx - CTL_0); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1843 | } |
| 1844 | } |
| 1845 | |
| 1846 | static void _sde_crtc_setup_mixers(struct drm_crtc *crtc) |
| 1847 | { |
| 1848 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 1849 | struct drm_encoder *enc; |
| 1850 | |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1851 | sde_crtc->num_mixers = 0; |
| 1852 | memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers)); |
| 1853 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 1854 | mutex_lock(&sde_crtc->crtc_lock); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1855 | /* Check for mixers on all encoders attached to this crtc */ |
| 1856 | list_for_each_entry(enc, &crtc->dev->mode_config.encoder_list, head) { |
| 1857 | if (enc->crtc != crtc) |
| 1858 | continue; |
| 1859 | |
| 1860 | _sde_crtc_setup_mixer_for_encoder(crtc, enc); |
| 1861 | } |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1862 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 1863 | mutex_unlock(&sde_crtc->crtc_lock); |
Lloyd Atkinson | 11f3444 | 2016-08-11 11:19:52 -0400 | [diff] [blame] | 1864 | } |
| 1865 | |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 1866 | static void _sde_crtc_setup_is_ppsplit(struct drm_crtc_state *state) |
| 1867 | { |
| 1868 | int i; |
| 1869 | struct sde_crtc_state *cstate; |
| 1870 | |
| 1871 | cstate = to_sde_crtc_state(state); |
| 1872 | |
| 1873 | cstate->is_ppsplit = false; |
| 1874 | for (i = 0; i < cstate->num_connectors; i++) { |
| 1875 | struct drm_connector *conn = cstate->connectors[i]; |
| 1876 | |
| 1877 | if (sde_connector_get_topology_name(conn) == |
| 1878 | SDE_RM_TOPOLOGY_PPSPLIT) |
| 1879 | cstate->is_ppsplit = true; |
| 1880 | } |
| 1881 | } |
| 1882 | |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1883 | static void _sde_crtc_setup_lm_bounds(struct drm_crtc *crtc, |
| 1884 | struct drm_crtc_state *state) |
| 1885 | { |
| 1886 | struct sde_crtc *sde_crtc; |
| 1887 | struct sde_crtc_state *cstate; |
| 1888 | struct drm_display_mode *adj_mode; |
| 1889 | u32 crtc_split_width; |
| 1890 | int i; |
| 1891 | |
| 1892 | if (!crtc || !state) { |
| 1893 | SDE_ERROR("invalid args\n"); |
| 1894 | return; |
| 1895 | } |
| 1896 | |
| 1897 | sde_crtc = to_sde_crtc(crtc); |
| 1898 | cstate = to_sde_crtc_state(state); |
| 1899 | |
| 1900 | adj_mode = &state->adjusted_mode; |
| 1901 | crtc_split_width = sde_crtc_mixer_width(sde_crtc, adj_mode); |
| 1902 | |
| 1903 | for (i = 0; i < sde_crtc->num_mixers; i++) { |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1904 | cstate->lm_bounds[i].x = crtc_split_width * i; |
| 1905 | cstate->lm_bounds[i].y = 0; |
| 1906 | cstate->lm_bounds[i].w = crtc_split_width; |
| 1907 | cstate->lm_bounds[i].h = adj_mode->vdisplay; |
| 1908 | memcpy(&cstate->lm_roi[i], &cstate->lm_bounds[i], |
| 1909 | sizeof(cstate->lm_roi[i])); |
| 1910 | SDE_EVT32(DRMID(crtc), i, |
| 1911 | cstate->lm_bounds[i].x, cstate->lm_bounds[i].y, |
| 1912 | cstate->lm_bounds[i].w, cstate->lm_bounds[i].h); |
| 1913 | SDE_DEBUG("%s: lm%d bnd&roi (%d,%d,%d,%d)\n", sde_crtc->name, i, |
| 1914 | cstate->lm_roi[i].x, cstate->lm_roi[i].y, |
| 1915 | cstate->lm_roi[i].w, cstate->lm_roi[i].h); |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1916 | } |
| 1917 | |
| 1918 | drm_mode_debug_printmodeline(adj_mode); |
| 1919 | } |
| 1920 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1921 | static void sde_crtc_atomic_begin(struct drm_crtc *crtc, |
Clarence Ip | 0d0e96d | 2016-10-24 18:13:13 -0400 | [diff] [blame] | 1922 | struct drm_crtc_state *old_state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1923 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1924 | struct sde_crtc *sde_crtc; |
Dhaval Patel | 0e558f4 | 2017-04-30 00:51:40 -0700 | [diff] [blame] | 1925 | struct drm_encoder *encoder; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1926 | struct drm_device *dev; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1927 | unsigned long flags; |
| 1928 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1929 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 1930 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1931 | return; |
| 1932 | } |
| 1933 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 1934 | if (!crtc->state->enable) { |
| 1935 | SDE_DEBUG("crtc%d -> enable %d, skip atomic_begin\n", |
| 1936 | crtc->base.id, crtc->state->enable); |
| 1937 | return; |
| 1938 | } |
| 1939 | |
| 1940 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
| 1941 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1942 | sde_crtc = to_sde_crtc(crtc); |
| 1943 | dev = crtc->dev; |
| 1944 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1945 | if (!sde_crtc->num_mixers) { |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1946 | _sde_crtc_setup_mixers(crtc); |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 1947 | _sde_crtc_setup_is_ppsplit(crtc->state); |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 1948 | _sde_crtc_setup_lm_bounds(crtc, crtc->state); |
| 1949 | } |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 1950 | |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 1951 | if (sde_crtc->event) { |
| 1952 | WARN_ON(sde_crtc->event); |
| 1953 | } else { |
| 1954 | spin_lock_irqsave(&dev->event_lock, flags); |
| 1955 | sde_crtc->event = crtc->state->event; |
| 1956 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 1957 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1958 | |
Dhaval Patel | 0e558f4 | 2017-04-30 00:51:40 -0700 | [diff] [blame] | 1959 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 1960 | if (encoder->crtc != crtc) |
| 1961 | continue; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 1962 | |
Dhaval Patel | 0e558f4 | 2017-04-30 00:51:40 -0700 | [diff] [blame] | 1963 | /* encoder will trigger pending mask now */ |
| 1964 | sde_encoder_trigger_kickoff_pending(encoder); |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 1965 | } |
| 1966 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1967 | /* |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1968 | * If no mixers have been allocated in sde_crtc_atomic_check(), |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1969 | * it means we are trying to flush a CRTC whose state is disabled: |
| 1970 | * nothing else needs to be done. |
| 1971 | */ |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 1972 | if (unlikely(!sde_crtc->num_mixers)) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1973 | return; |
| 1974 | |
Clarence Ip | d9f9fa6 | 2016-09-09 13:42:32 -0400 | [diff] [blame] | 1975 | _sde_crtc_blend_setup(crtc); |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 1976 | sde_cp_crtc_apply_properties(crtc); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1977 | |
| 1978 | /* |
| 1979 | * PP_DONE irq is only used by command mode for now. |
| 1980 | * It is better to request pending before FLUSH and START trigger |
| 1981 | * to make sure no pp_done irq missed. |
| 1982 | * This is safe because no pp_done will happen before SW trigger |
| 1983 | * in command mode. |
| 1984 | */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1985 | } |
| 1986 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1987 | static void sde_crtc_atomic_flush(struct drm_crtc *crtc, |
| 1988 | struct drm_crtc_state *old_crtc_state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1989 | { |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 1990 | struct drm_encoder *encoder; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1991 | struct sde_crtc *sde_crtc; |
| 1992 | struct drm_device *dev; |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 1993 | struct drm_plane *plane; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 1994 | unsigned long flags; |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 1995 | struct sde_crtc_state *cstate; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 1996 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1997 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 1998 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 1999 | return; |
| 2000 | } |
| 2001 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 2002 | if (!crtc->state->enable) { |
| 2003 | SDE_DEBUG("crtc%d -> enable %d, skip atomic_flush\n", |
| 2004 | crtc->base.id, crtc->state->enable); |
| 2005 | return; |
| 2006 | } |
| 2007 | |
| 2008 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2009 | |
| 2010 | sde_crtc = to_sde_crtc(crtc); |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 2011 | cstate = to_sde_crtc_state(crtc->state); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2012 | dev = crtc->dev; |
| 2013 | |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 2014 | if (sde_crtc->event) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2015 | SDE_DEBUG("already received sde_crtc->event\n"); |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 2016 | } else { |
Lloyd Atkinson | 265d221 | 2016-05-30 13:12:01 -0400 | [diff] [blame] | 2017 | spin_lock_irqsave(&dev->event_lock, flags); |
| 2018 | sde_crtc->event = crtc->state->event; |
| 2019 | spin_unlock_irqrestore(&dev->event_lock, flags); |
| 2020 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2021 | |
| 2022 | /* |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2023 | * If no mixers has been allocated in sde_crtc_atomic_check(), |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2024 | * it means we are trying to flush a CRTC whose state is disabled: |
| 2025 | * nothing else needs to be done. |
| 2026 | */ |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2027 | if (unlikely(!sde_crtc->num_mixers)) |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2028 | return; |
| 2029 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2030 | /* wait for acquire fences before anything else is done */ |
| 2031 | _sde_crtc_wait_for_fences(crtc); |
| 2032 | |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 2033 | if (!cstate->rsc_update) { |
| 2034 | drm_for_each_encoder(encoder, dev) { |
| 2035 | if (encoder->crtc != crtc) |
| 2036 | continue; |
| 2037 | |
| 2038 | cstate->rsc_client = |
Dhaval Patel | 30fae8a | 2017-04-21 18:42:41 -0700 | [diff] [blame] | 2039 | sde_encoder_get_rsc_client(encoder); |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 2040 | } |
| 2041 | cstate->rsc_update = true; |
| 2042 | } |
| 2043 | |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 2044 | /* update performance setting before crtc kickoff */ |
| 2045 | sde_core_perf_crtc_update(crtc, 1, false); |
| 2046 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2047 | /* |
| 2048 | * Final plane updates: Give each plane a chance to complete all |
| 2049 | * required writes/flushing before crtc's "flush |
| 2050 | * everything" call below. |
| 2051 | */ |
| 2052 | drm_atomic_crtc_for_each_plane(plane, crtc) |
| 2053 | sde_plane_flush(plane); |
| 2054 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2055 | /* Kickoff will be scheduled by outer layer */ |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2056 | } |
| 2057 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2058 | /** |
| 2059 | * sde_crtc_destroy_state - state destroy hook |
| 2060 | * @crtc: drm CRTC |
| 2061 | * @state: CRTC state object to release |
| 2062 | */ |
| 2063 | static void sde_crtc_destroy_state(struct drm_crtc *crtc, |
| 2064 | struct drm_crtc_state *state) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2065 | { |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2066 | struct sde_crtc *sde_crtc; |
| 2067 | struct sde_crtc_state *cstate; |
| 2068 | |
| 2069 | if (!crtc || !state) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2070 | SDE_ERROR("invalid argument(s)\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2071 | return; |
| 2072 | } |
| 2073 | |
| 2074 | sde_crtc = to_sde_crtc(crtc); |
| 2075 | cstate = to_sde_crtc_state(state); |
| 2076 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 2077 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2078 | |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 2079 | _sde_crtc_rp_destroy(&cstate->rp); |
| 2080 | |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 2081 | __drm_atomic_helper_crtc_destroy_state(state); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2082 | |
| 2083 | /* destroy value helper */ |
| 2084 | msm_property_destroy_state(&sde_crtc->property_info, cstate, |
| 2085 | cstate->property_values, cstate->property_blobs); |
| 2086 | } |
| 2087 | |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2088 | void sde_crtc_commit_kickoff(struct drm_crtc *crtc) |
| 2089 | { |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 2090 | struct drm_encoder *encoder; |
| 2091 | struct drm_device *dev; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2092 | struct sde_crtc *sde_crtc; |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 2093 | struct msm_drm_private *priv; |
| 2094 | struct sde_kms *sde_kms; |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 2095 | struct sde_crtc_state *cstate; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2096 | |
| 2097 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2098 | SDE_ERROR("invalid argument\n"); |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2099 | return; |
| 2100 | } |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 2101 | dev = crtc->dev; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2102 | sde_crtc = to_sde_crtc(crtc); |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 2103 | sde_kms = _sde_crtc_get_kms(crtc); |
| 2104 | priv = sde_kms->dev->dev_private; |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 2105 | cstate = to_sde_crtc_state(crtc->state); |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2106 | |
Clarence Ip | 90b282d | 2017-05-04 10:00:32 -0700 | [diff] [blame] | 2107 | /* |
| 2108 | * If no mixers has been allocated in sde_crtc_atomic_check(), |
| 2109 | * it means we are trying to start a CRTC whose state is disabled: |
| 2110 | * nothing else needs to be done. |
| 2111 | */ |
| 2112 | if (unlikely(!sde_crtc->num_mixers)) |
| 2113 | return; |
| 2114 | |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 2115 | SDE_ATRACE_BEGIN("crtc_commit"); |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 2116 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 2117 | struct sde_encoder_kickoff_params params = { 0 }; |
| 2118 | |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 2119 | if (encoder->crtc != crtc) |
| 2120 | continue; |
| 2121 | |
| 2122 | /* |
| 2123 | * Encoder will flush/start now, unless it has a tx pending. |
| 2124 | * If so, it may delay and flush at an irq event (e.g. ppdone) |
| 2125 | */ |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 2126 | params.inline_rotate_prefill = cstate->sbuf_prefill_line; |
Lloyd Atkinson | 73fb809 | 2017-02-08 16:02:55 -0500 | [diff] [blame] | 2127 | params.affected_displays = _sde_crtc_get_displays_affected(crtc, |
| 2128 | crtc->state); |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 2129 | sde_encoder_prepare_for_kickoff(encoder, ¶ms); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2130 | } |
| 2131 | |
| 2132 | if (atomic_read(&sde_crtc->frame_pending) > 2) { |
| 2133 | /* framework allows only 1 outstanding + current */ |
| 2134 | SDE_ERROR("crtc%d invalid frame pending\n", |
| 2135 | crtc->base.id); |
| 2136 | SDE_EVT32(DRMID(crtc), 0); |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 2137 | goto end; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2138 | } else if (atomic_inc_return(&sde_crtc->frame_pending) == 1) { |
| 2139 | /* acquire bandwidth and other resources */ |
| 2140 | SDE_DEBUG("crtc%d first commit\n", crtc->base.id); |
| 2141 | SDE_EVT32(DRMID(crtc), 1); |
| 2142 | } else { |
| 2143 | SDE_DEBUG("crtc%d commit\n", crtc->base.id); |
| 2144 | SDE_EVT32(DRMID(crtc), 2); |
| 2145 | } |
Dhaval Patel | d67cf4a | 2017-06-14 18:08:32 -0700 | [diff] [blame] | 2146 | sde_crtc->play_count++; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2147 | |
| 2148 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
| 2149 | if (encoder->crtc != crtc) |
| 2150 | continue; |
| 2151 | |
| 2152 | sde_encoder_kickoff(encoder); |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 2153 | } |
Narendra Muppalla | 77b3293 | 2017-05-10 13:53:11 -0700 | [diff] [blame] | 2154 | end: |
| 2155 | SDE_ATRACE_END("crtc_commit"); |
| 2156 | return; |
Lloyd Atkinson | 5d72278 | 2016-05-30 14:09:41 -0400 | [diff] [blame] | 2157 | } |
| 2158 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2159 | /** |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2160 | * _sde_crtc_vblank_enable_nolock - update power resource and vblank request |
| 2161 | * @sde_crtc: Pointer to sde crtc structure |
| 2162 | * @enable: Whether to enable/disable vblanks |
| 2163 | */ |
| 2164 | static void _sde_crtc_vblank_enable_nolock( |
| 2165 | struct sde_crtc *sde_crtc, bool enable) |
| 2166 | { |
| 2167 | struct drm_device *dev; |
| 2168 | struct drm_crtc *crtc; |
| 2169 | struct drm_encoder *enc; |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2170 | |
| 2171 | if (!sde_crtc) { |
| 2172 | SDE_ERROR("invalid crtc\n"); |
| 2173 | return; |
| 2174 | } |
| 2175 | |
| 2176 | crtc = &sde_crtc->base; |
| 2177 | dev = crtc->dev; |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2178 | |
| 2179 | if (enable) { |
Lloyd Atkinson | 2c554eb | 2017-05-24 16:22:39 -0400 | [diff] [blame] | 2180 | int ret; |
| 2181 | |
| 2182 | /* drop lock since power crtc cb may try to re-acquire lock */ |
| 2183 | mutex_unlock(&sde_crtc->crtc_lock); |
| 2184 | ret = _sde_crtc_power_enable(sde_crtc, true); |
| 2185 | mutex_lock(&sde_crtc->crtc_lock); |
| 2186 | if (ret) |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 2187 | return; |
| 2188 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2189 | list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { |
| 2190 | if (enc->crtc != crtc) |
| 2191 | continue; |
| 2192 | |
| 2193 | SDE_EVT32(DRMID(crtc), DRMID(enc), enable); |
| 2194 | |
| 2195 | sde_encoder_register_vblank_callback(enc, |
| 2196 | sde_crtc_vblank_cb, (void *)crtc); |
| 2197 | } |
| 2198 | } else { |
| 2199 | list_for_each_entry(enc, &dev->mode_config.encoder_list, head) { |
| 2200 | if (enc->crtc != crtc) |
| 2201 | continue; |
| 2202 | |
| 2203 | SDE_EVT32(DRMID(crtc), DRMID(enc), enable); |
| 2204 | |
| 2205 | sde_encoder_register_vblank_callback(enc, NULL, NULL); |
| 2206 | } |
Lloyd Atkinson | 2c554eb | 2017-05-24 16:22:39 -0400 | [diff] [blame] | 2207 | |
| 2208 | /* drop lock since power crtc cb may try to re-acquire lock */ |
| 2209 | mutex_unlock(&sde_crtc->crtc_lock); |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 2210 | _sde_crtc_power_enable(sde_crtc, false); |
Lloyd Atkinson | 2c554eb | 2017-05-24 16:22:39 -0400 | [diff] [blame] | 2211 | mutex_lock(&sde_crtc->crtc_lock); |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2212 | } |
| 2213 | } |
| 2214 | |
| 2215 | /** |
| 2216 | * _sde_crtc_set_suspend - notify crtc of suspend enable/disable |
| 2217 | * @crtc: Pointer to drm crtc object |
| 2218 | * @enable: true to enable suspend, false to indicate resume |
| 2219 | */ |
| 2220 | static void _sde_crtc_set_suspend(struct drm_crtc *crtc, bool enable) |
| 2221 | { |
| 2222 | struct sde_crtc *sde_crtc; |
| 2223 | struct msm_drm_private *priv; |
| 2224 | struct sde_kms *sde_kms; |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 2225 | struct drm_event event; |
| 2226 | u32 power_on; |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2227 | |
| 2228 | if (!crtc || !crtc->dev || !crtc->dev->dev_private) { |
| 2229 | SDE_ERROR("invalid crtc\n"); |
| 2230 | return; |
| 2231 | } |
| 2232 | sde_crtc = to_sde_crtc(crtc); |
| 2233 | priv = crtc->dev->dev_private; |
| 2234 | |
| 2235 | if (!priv->kms) { |
| 2236 | SDE_ERROR("invalid crtc kms\n"); |
| 2237 | return; |
| 2238 | } |
| 2239 | sde_kms = to_sde_kms(priv->kms); |
| 2240 | |
| 2241 | SDE_DEBUG("crtc%d suspend = %d\n", crtc->base.id, enable); |
| 2242 | |
| 2243 | mutex_lock(&sde_crtc->crtc_lock); |
| 2244 | |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 2245 | event.type = DRM_EVENT_CRTC_POWER; |
| 2246 | event.length = sizeof(u32); |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2247 | /* |
Clarence Ip | 2f9beeb | 2017-03-16 11:04:53 -0400 | [diff] [blame] | 2248 | * Update CP on suspend/resume transitions |
| 2249 | */ |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 2250 | if (enable && !sde_crtc->suspend) { |
Clarence Ip | 2f9beeb | 2017-03-16 11:04:53 -0400 | [diff] [blame] | 2251 | sde_cp_crtc_suspend(crtc); |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 2252 | power_on = 0; |
| 2253 | } else if (!enable && sde_crtc->suspend) { |
Clarence Ip | 2f9beeb | 2017-03-16 11:04:53 -0400 | [diff] [blame] | 2254 | sde_cp_crtc_resume(crtc); |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 2255 | power_on = 1; |
| 2256 | } |
Clarence Ip | 2f9beeb | 2017-03-16 11:04:53 -0400 | [diff] [blame] | 2257 | |
| 2258 | /* |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2259 | * If the vblank refcount != 0, release a power reference on suspend |
| 2260 | * and take it back during resume (if it is still != 0). |
| 2261 | */ |
| 2262 | if (sde_crtc->suspend == enable) |
| 2263 | SDE_DEBUG("crtc%d suspend already set to %d, ignoring update\n", |
| 2264 | crtc->base.id, enable); |
| 2265 | else if (atomic_read(&sde_crtc->vblank_refcount) != 0) |
| 2266 | _sde_crtc_vblank_enable_nolock(sde_crtc, !enable); |
| 2267 | |
| 2268 | sde_crtc->suspend = enable; |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 2269 | msm_mode_object_event_nofity(&crtc->base, crtc->dev, &event, |
| 2270 | (u8 *)&power_on); |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2271 | mutex_unlock(&sde_crtc->crtc_lock); |
| 2272 | } |
| 2273 | |
| 2274 | /** |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2275 | * sde_crtc_duplicate_state - state duplicate hook |
| 2276 | * @crtc: Pointer to drm crtc structure |
| 2277 | * @Returns: Pointer to new drm_crtc_state structure |
| 2278 | */ |
| 2279 | static struct drm_crtc_state *sde_crtc_duplicate_state(struct drm_crtc *crtc) |
| 2280 | { |
| 2281 | struct sde_crtc *sde_crtc; |
| 2282 | struct sde_crtc_state *cstate, *old_cstate; |
| 2283 | |
| 2284 | if (!crtc || !crtc->state) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2285 | SDE_ERROR("invalid argument(s)\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2286 | return NULL; |
| 2287 | } |
| 2288 | |
| 2289 | sde_crtc = to_sde_crtc(crtc); |
| 2290 | old_cstate = to_sde_crtc_state(crtc->state); |
| 2291 | cstate = msm_property_alloc_state(&sde_crtc->property_info); |
| 2292 | if (!cstate) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2293 | SDE_ERROR("failed to allocate state\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2294 | return NULL; |
| 2295 | } |
| 2296 | |
| 2297 | /* duplicate value helper */ |
| 2298 | msm_property_duplicate_state(&sde_crtc->property_info, |
| 2299 | old_cstate, cstate, |
| 2300 | cstate->property_values, cstate->property_blobs); |
| 2301 | |
| 2302 | /* duplicate base helper */ |
| 2303 | __drm_atomic_helper_crtc_duplicate_state(crtc, &cstate->base); |
| 2304 | |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 2305 | _sde_crtc_rp_duplicate(&old_cstate->rp, &cstate->rp); |
| 2306 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2307 | return &cstate->base; |
| 2308 | } |
| 2309 | |
| 2310 | /** |
| 2311 | * sde_crtc_reset - reset hook for CRTCs |
| 2312 | * Resets the atomic state for @crtc by freeing the state pointer (which might |
| 2313 | * be NULL, e.g. at driver load time) and allocating a new empty state object. |
| 2314 | * @crtc: Pointer to drm crtc structure |
| 2315 | */ |
| 2316 | static void sde_crtc_reset(struct drm_crtc *crtc) |
| 2317 | { |
| 2318 | struct sde_crtc *sde_crtc; |
| 2319 | struct sde_crtc_state *cstate; |
| 2320 | |
| 2321 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2322 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2323 | return; |
| 2324 | } |
| 2325 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2326 | /* revert suspend actions, if necessary */ |
| 2327 | if (msm_is_suspend_state(crtc->dev)) |
| 2328 | _sde_crtc_set_suspend(crtc, false); |
| 2329 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2330 | /* remove previous state, if present */ |
| 2331 | if (crtc->state) { |
| 2332 | sde_crtc_destroy_state(crtc, crtc->state); |
| 2333 | crtc->state = 0; |
| 2334 | } |
| 2335 | |
| 2336 | sde_crtc = to_sde_crtc(crtc); |
| 2337 | cstate = msm_property_alloc_state(&sde_crtc->property_info); |
| 2338 | if (!cstate) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2339 | SDE_ERROR("failed to allocate state\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2340 | return; |
| 2341 | } |
| 2342 | |
| 2343 | /* reset value helper */ |
| 2344 | msm_property_reset_state(&sde_crtc->property_info, cstate, |
| 2345 | cstate->property_values, cstate->property_blobs); |
| 2346 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2347 | _sde_crtc_set_input_fence_timeout(cstate); |
| 2348 | |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 2349 | _sde_crtc_rp_reset(&cstate->rp); |
| 2350 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2351 | cstate->base.crtc = crtc; |
| 2352 | crtc->state = &cstate->base; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2353 | } |
| 2354 | |
Clarence Ip | 9728a1d | 2017-04-18 22:22:13 -0400 | [diff] [blame] | 2355 | static int _sde_crtc_vblank_no_lock(struct sde_crtc *sde_crtc, bool en) |
| 2356 | { |
| 2357 | if (!sde_crtc) { |
| 2358 | SDE_ERROR("invalid crtc\n"); |
| 2359 | return -EINVAL; |
| 2360 | } else if (en && atomic_inc_return(&sde_crtc->vblank_refcount) == 1) { |
| 2361 | SDE_DEBUG("crtc%d vblank enable\n", sde_crtc->base.base.id); |
| 2362 | if (!sde_crtc->suspend) |
| 2363 | _sde_crtc_vblank_enable_nolock(sde_crtc, true); |
| 2364 | } else if (!en && atomic_read(&sde_crtc->vblank_refcount) < 1) { |
| 2365 | SDE_ERROR("crtc%d invalid vblank disable\n", |
| 2366 | sde_crtc->base.base.id); |
| 2367 | return -EINVAL; |
| 2368 | } else if (!en && atomic_dec_return(&sde_crtc->vblank_refcount) == 0) { |
| 2369 | SDE_DEBUG("crtc%d vblank disable\n", sde_crtc->base.base.id); |
| 2370 | if (!sde_crtc->suspend) |
| 2371 | _sde_crtc_vblank_enable_nolock(sde_crtc, false); |
| 2372 | } else { |
| 2373 | SDE_DEBUG("crtc%d vblank %s refcount:%d\n", |
| 2374 | sde_crtc->base.base.id, |
| 2375 | en ? "enable" : "disable", |
| 2376 | atomic_read(&sde_crtc->vblank_refcount)); |
| 2377 | } |
| 2378 | |
| 2379 | return 0; |
| 2380 | } |
| 2381 | |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2382 | static void sde_crtc_handle_power_event(u32 event_type, void *arg) |
| 2383 | { |
| 2384 | struct drm_crtc *crtc = arg; |
| 2385 | struct sde_crtc *sde_crtc; |
| 2386 | struct drm_encoder *encoder; |
| 2387 | |
| 2388 | if (!crtc) { |
| 2389 | SDE_ERROR("invalid crtc\n"); |
| 2390 | return; |
| 2391 | } |
| 2392 | sde_crtc = to_sde_crtc(crtc); |
| 2393 | |
| 2394 | mutex_lock(&sde_crtc->crtc_lock); |
| 2395 | |
| 2396 | SDE_EVT32(DRMID(crtc), event_type); |
| 2397 | |
| 2398 | if (event_type == SDE_POWER_EVENT_POST_ENABLE) { |
| 2399 | /* restore encoder; crtc will be programmed during commit */ |
| 2400 | drm_for_each_encoder(encoder, crtc->dev) { |
| 2401 | if (encoder->crtc != crtc) |
| 2402 | continue; |
| 2403 | |
| 2404 | sde_encoder_virt_restore(encoder); |
| 2405 | } |
| 2406 | |
| 2407 | } else if (event_type == SDE_POWER_EVENT_POST_DISABLE) { |
| 2408 | struct drm_plane *plane; |
| 2409 | |
| 2410 | /* |
| 2411 | * set revalidate flag in planes, so it will be re-programmed |
| 2412 | * in the next frame update |
| 2413 | */ |
| 2414 | drm_atomic_crtc_for_each_plane(plane, crtc) |
| 2415 | sde_plane_set_revalidate(plane, true); |
| 2416 | } |
| 2417 | |
| 2418 | mutex_unlock(&sde_crtc->crtc_lock); |
| 2419 | } |
| 2420 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2421 | static void sde_crtc_disable(struct drm_crtc *crtc) |
| 2422 | { |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2423 | struct sde_crtc *sde_crtc; |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 2424 | struct sde_crtc_state *cstate; |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 2425 | struct drm_encoder *encoder; |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2426 | struct msm_drm_private *priv; |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 2427 | unsigned long flags; |
| 2428 | struct sde_crtc_irq_info *node = NULL; |
| 2429 | int ret; |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2430 | |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2431 | if (!crtc || !crtc->dev || !crtc->dev->dev_private || !crtc->state) { |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 2432 | SDE_ERROR("invalid crtc\n"); |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2433 | return; |
| 2434 | } |
| 2435 | sde_crtc = to_sde_crtc(crtc); |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 2436 | cstate = to_sde_crtc_state(crtc->state); |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2437 | priv = crtc->dev->dev_private; |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2438 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 2439 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2440 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2441 | if (msm_is_suspend_state(crtc->dev)) |
| 2442 | _sde_crtc_set_suspend(crtc, true); |
| 2443 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 2444 | mutex_lock(&sde_crtc->crtc_lock); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2445 | SDE_EVT32(DRMID(crtc)); |
| 2446 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2447 | if (atomic_read(&sde_crtc->vblank_refcount) && !sde_crtc->suspend) { |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2448 | SDE_ERROR("crtc%d invalid vblank refcount\n", |
| 2449 | crtc->base.id); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 2450 | SDE_EVT32(DRMID(crtc), atomic_read(&sde_crtc->vblank_refcount), |
| 2451 | SDE_EVTLOG_FUNC_CASE1); |
Clarence Ip | 9728a1d | 2017-04-18 22:22:13 -0400 | [diff] [blame] | 2452 | while (atomic_read(&sde_crtc->vblank_refcount)) |
| 2453 | if (_sde_crtc_vblank_no_lock(sde_crtc, false)) |
| 2454 | break; |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 2455 | } |
| 2456 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2457 | if (atomic_read(&sde_crtc->frame_pending)) { |
| 2458 | /* release bandwidth and other resources */ |
Ingrid Gallardo | 79b4439 | 2017-05-30 16:30:52 -0700 | [diff] [blame] | 2459 | SDE_ERROR("crtc%d invalid frame pending\n", crtc->base.id); |
Dhaval Patel | 6c66662 | 2017-03-21 23:02:59 -0700 | [diff] [blame] | 2460 | SDE_EVT32(DRMID(crtc), atomic_read(&sde_crtc->frame_pending), |
| 2461 | SDE_EVTLOG_FUNC_CASE2); |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 2462 | sde_core_perf_crtc_release_bw(crtc); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2463 | atomic_set(&sde_crtc->frame_pending, 0); |
| 2464 | } |
| 2465 | |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 2466 | sde_core_perf_crtc_update(crtc, 0, true); |
| 2467 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2468 | drm_for_each_encoder(encoder, crtc->dev) { |
| 2469 | if (encoder->crtc != crtc) |
| 2470 | continue; |
| 2471 | sde_encoder_register_frame_event_callback(encoder, NULL, NULL); |
Dhaval Patel | 82c8dbc | 2017-02-18 23:15:10 -0800 | [diff] [blame] | 2472 | cstate->rsc_client = NULL; |
| 2473 | cstate->rsc_update = false; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2474 | } |
| 2475 | |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2476 | if (sde_crtc->power_event) |
| 2477 | sde_power_handle_unregister_event(&priv->phandle, |
| 2478 | sde_crtc->power_event); |
| 2479 | |
Lloyd Atkinson | c44a52e | 2016-08-16 16:40:17 -0400 | [diff] [blame] | 2480 | memset(sde_crtc->mixers, 0, sizeof(sde_crtc->mixers)); |
| 2481 | sde_crtc->num_mixers = 0; |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 2482 | |
Alan Kwong | 8411a911 | 2017-06-06 19:29:01 -0400 | [diff] [blame] | 2483 | /* disable clk & bw control until clk & bw properties are set */ |
| 2484 | cstate->bw_control = false; |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame^] | 2485 | cstate->bw_split_vote = false; |
Alan Kwong | 8411a911 | 2017-06-06 19:29:01 -0400 | [diff] [blame] | 2486 | |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 2487 | spin_lock_irqsave(&sde_crtc->spin_lock, flags); |
| 2488 | list_for_each_entry(node, &sde_crtc->user_event_list, list) { |
| 2489 | ret = 0; |
| 2490 | if (node->func) |
| 2491 | ret = node->func(crtc, false, &node->irq); |
| 2492 | if (ret) |
| 2493 | SDE_ERROR("%s failed to disable event %x\n", |
| 2494 | sde_crtc->name, node->event); |
| 2495 | } |
| 2496 | spin_unlock_irqrestore(&sde_crtc->spin_lock, flags); |
| 2497 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 2498 | mutex_unlock(&sde_crtc->crtc_lock); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2499 | } |
| 2500 | |
| 2501 | static void sde_crtc_enable(struct drm_crtc *crtc) |
| 2502 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2503 | struct sde_crtc *sde_crtc; |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2504 | struct drm_encoder *encoder; |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2505 | struct msm_drm_private *priv; |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 2506 | unsigned long flags; |
| 2507 | struct sde_crtc_irq_info *node = NULL; |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 2508 | int ret; |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 2509 | |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2510 | if (!crtc || !crtc->dev || !crtc->dev->dev_private) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2511 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2512 | return; |
| 2513 | } |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2514 | priv = crtc->dev->dev_private; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2515 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 2516 | SDE_DEBUG("crtc%d\n", crtc->base.id); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2517 | SDE_EVT32(DRMID(crtc)); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2518 | sde_crtc = to_sde_crtc(crtc); |
Lloyd Atkinson | af7952d | 2016-06-26 22:41:26 -0400 | [diff] [blame] | 2519 | |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 2520 | drm_for_each_encoder(encoder, crtc->dev) { |
| 2521 | if (encoder->crtc != crtc) |
| 2522 | continue; |
| 2523 | sde_encoder_register_frame_event_callback(encoder, |
| 2524 | sde_crtc_frame_event_cb, (void *)crtc); |
| 2525 | } |
| 2526 | |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 2527 | spin_lock_irqsave(&sde_crtc->spin_lock, flags); |
| 2528 | list_for_each_entry(node, &sde_crtc->user_event_list, list) { |
| 2529 | ret = 0; |
| 2530 | if (node->func) |
| 2531 | ret = node->func(crtc, true, &node->irq); |
| 2532 | if (ret) |
| 2533 | SDE_ERROR("%s failed to enable event %x\n", |
| 2534 | sde_crtc->name, node->event); |
| 2535 | } |
| 2536 | spin_unlock_irqrestore(&sde_crtc->spin_lock, flags); |
Veera Sundaram Sankaran | 82916e0 | 2017-03-29 18:44:22 -0700 | [diff] [blame] | 2537 | |
| 2538 | sde_crtc->power_event = sde_power_handle_register_event( |
| 2539 | &priv->phandle, |
| 2540 | SDE_POWER_EVENT_POST_ENABLE | SDE_POWER_EVENT_POST_DISABLE, |
| 2541 | sde_crtc_handle_power_event, crtc, sde_crtc->name); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2542 | } |
| 2543 | |
| 2544 | struct plane_state { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2545 | struct sde_plane_state *sde_pstate; |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 2546 | const struct drm_plane_state *drm_pstate; |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2547 | int stage; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2548 | u32 pipe_id; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2549 | }; |
| 2550 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2551 | static int pstate_cmp(const void *a, const void *b) |
| 2552 | { |
| 2553 | struct plane_state *pa = (struct plane_state *)a; |
| 2554 | struct plane_state *pb = (struct plane_state *)b; |
| 2555 | int rc = 0; |
| 2556 | int pa_zpos, pb_zpos; |
| 2557 | |
| 2558 | pa_zpos = sde_plane_get_property(pa->sde_pstate, PLANE_PROP_ZPOS); |
| 2559 | pb_zpos = sde_plane_get_property(pb->sde_pstate, PLANE_PROP_ZPOS); |
| 2560 | |
| 2561 | if (pa_zpos != pb_zpos) |
| 2562 | rc = pa_zpos - pb_zpos; |
| 2563 | else |
| 2564 | rc = pa->drm_pstate->crtc_x - pb->drm_pstate->crtc_x; |
| 2565 | |
| 2566 | return rc; |
| 2567 | } |
| 2568 | |
Dhaval Patel | a8d6bc6 | 2017-05-10 17:40:18 -0700 | [diff] [blame] | 2569 | static int _sde_crtc_excl_rect_overlap_check(struct plane_state pstates[], |
| 2570 | int cnt, int curr_cnt, struct sde_rect *excl_rect, int z_pos) |
| 2571 | { |
| 2572 | struct sde_rect dst_rect, intersect; |
| 2573 | int i, rc = -EINVAL; |
| 2574 | const struct drm_plane_state *pstate; |
| 2575 | |
| 2576 | /* start checking from next plane */ |
| 2577 | for (i = curr_cnt; i < cnt; i++) { |
| 2578 | pstate = pstates[i].drm_pstate; |
| 2579 | POPULATE_RECT(&dst_rect, pstate->crtc_x, pstate->crtc_y, |
| 2580 | pstate->crtc_w, pstate->crtc_h, true); |
| 2581 | sde_kms_rect_intersect(&dst_rect, excl_rect, &intersect); |
| 2582 | |
| 2583 | if (intersect.w == excl_rect->w && intersect.h == excl_rect->h |
| 2584 | /* next plane may be on same z-order */ |
| 2585 | && z_pos != pstates[i].stage) { |
| 2586 | rc = 0; |
| 2587 | goto end; |
| 2588 | } |
| 2589 | } |
| 2590 | |
| 2591 | SDE_ERROR("excl rect does not find top overlapping rect\n"); |
| 2592 | end: |
| 2593 | return rc; |
| 2594 | } |
| 2595 | |
| 2596 | /* no input validation - caller API has all the checks */ |
| 2597 | static int _sde_crtc_excl_dim_layer_check(struct drm_crtc_state *state, |
| 2598 | struct plane_state pstates[], int cnt) |
| 2599 | { |
| 2600 | struct sde_crtc_state *cstate = to_sde_crtc_state(state); |
| 2601 | struct drm_display_mode *mode = &state->adjusted_mode; |
| 2602 | const struct drm_plane_state *pstate; |
| 2603 | struct sde_plane_state *sde_pstate; |
| 2604 | int rc = 0, i; |
| 2605 | |
| 2606 | /* Check dim layer rect bounds and stage */ |
| 2607 | for (i = 0; i < cstate->num_dim_layers; i++) { |
| 2608 | if ((CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.y, |
| 2609 | cstate->dim_layer[i].rect.h, mode->vdisplay)) || |
| 2610 | (CHECK_LAYER_BOUNDS(cstate->dim_layer[i].rect.x, |
| 2611 | cstate->dim_layer[i].rect.w, mode->hdisplay)) || |
| 2612 | (cstate->dim_layer[i].stage >= SDE_STAGE_MAX) || |
| 2613 | (!cstate->dim_layer[i].rect.w) || |
| 2614 | (!cstate->dim_layer[i].rect.h)) { |
| 2615 | SDE_ERROR("invalid dim_layer:{%d,%d,%d,%d}, stage:%d\n", |
| 2616 | cstate->dim_layer[i].rect.x, |
| 2617 | cstate->dim_layer[i].rect.y, |
| 2618 | cstate->dim_layer[i].rect.w, |
| 2619 | cstate->dim_layer[i].rect.h, |
| 2620 | cstate->dim_layer[i].stage); |
| 2621 | SDE_ERROR("display: %dx%d\n", mode->hdisplay, |
| 2622 | mode->vdisplay); |
| 2623 | rc = -E2BIG; |
| 2624 | goto end; |
| 2625 | } |
| 2626 | } |
| 2627 | |
| 2628 | /* this is traversing on sorted z-order pstates */ |
| 2629 | for (i = 0; i < cnt; i++) { |
| 2630 | pstate = pstates[i].drm_pstate; |
| 2631 | sde_pstate = to_sde_plane_state(pstate); |
| 2632 | if (sde_pstate->excl_rect.w && sde_pstate->excl_rect.h) { |
| 2633 | /* check overlap on all top z-order */ |
| 2634 | rc = _sde_crtc_excl_rect_overlap_check(pstates, cnt, |
| 2635 | i + 1, &sde_pstate->excl_rect, pstates[i].stage); |
| 2636 | if (rc) |
| 2637 | goto end; |
| 2638 | } |
| 2639 | } |
| 2640 | |
| 2641 | end: |
| 2642 | return rc; |
| 2643 | } |
| 2644 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2645 | static int sde_crtc_atomic_check(struct drm_crtc *crtc, |
| 2646 | struct drm_crtc_state *state) |
| 2647 | { |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2648 | struct sde_crtc *sde_crtc; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2649 | struct plane_state pstates[SDE_STAGE_MAX * 4]; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 2650 | struct sde_crtc_state *cstate; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2651 | |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 2652 | const struct drm_plane_state *pstate; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2653 | struct drm_plane *plane; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2654 | struct drm_display_mode *mode; |
| 2655 | |
| 2656 | int cnt = 0, rc = 0, mixer_width, i, z_pos; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2657 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2658 | struct sde_multirect_plane_states multirect_plane[SDE_STAGE_MAX * 2]; |
| 2659 | int multirect_count = 0; |
| 2660 | const struct drm_plane_state *pipe_staged[SSPP_MAX]; |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2661 | int left_zpos_cnt = 0, right_zpos_cnt = 0; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2662 | |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2663 | if (!crtc) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2664 | SDE_ERROR("invalid crtc\n"); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2665 | return -EINVAL; |
| 2666 | } |
| 2667 | |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 2668 | sde_crtc = to_sde_crtc(crtc); |
| 2669 | cstate = to_sde_crtc_state(state); |
| 2670 | |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 2671 | if (!state->enable || !state->active) { |
| 2672 | SDE_DEBUG("crtc%d -> enable %d, active %d, skip atomic_check\n", |
| 2673 | crtc->base.id, state->enable, state->active); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 2674 | goto end; |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 2675 | } |
| 2676 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2677 | mode = &state->adjusted_mode; |
| 2678 | SDE_DEBUG("%s: check", sde_crtc->name); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 2679 | |
Clarence Ip | 90b282d | 2017-05-04 10:00:32 -0700 | [diff] [blame] | 2680 | /* force a full mode set if active state changed */ |
| 2681 | if (state->active_changed) |
| 2682 | state->mode_changed = true; |
| 2683 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2684 | memset(pipe_staged, 0, sizeof(pipe_staged)); |
| 2685 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2686 | mixer_width = sde_crtc_mixer_width(sde_crtc, mode); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2687 | |
Lloyd Atkinson | 66e7dde | 2017-02-08 15:52:53 -0500 | [diff] [blame] | 2688 | _sde_crtc_setup_is_ppsplit(state); |
Lloyd Atkinson | a9d7e75 | 2017-01-17 16:31:43 -0500 | [diff] [blame] | 2689 | _sde_crtc_setup_lm_bounds(crtc, state); |
| 2690 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2691 | /* get plane state for all drm planes associated with crtc state */ |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 2692 | drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) { |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2693 | if (IS_ERR_OR_NULL(pstate)) { |
| 2694 | rc = PTR_ERR(pstate); |
| 2695 | SDE_ERROR("%s: failed to get plane%d state, %d\n", |
| 2696 | sde_crtc->name, plane->base.id, rc); |
Alan Kwong | 8576728 | 2016-10-03 18:03:37 -0400 | [diff] [blame] | 2697 | goto end; |
| 2698 | } |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2699 | if (cnt >= ARRAY_SIZE(pstates)) |
| 2700 | continue; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2701 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2702 | pstates[cnt].sde_pstate = to_sde_plane_state(pstate); |
| 2703 | pstates[cnt].drm_pstate = pstate; |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2704 | pstates[cnt].stage = sde_plane_get_property( |
| 2705 | pstates[cnt].sde_pstate, PLANE_PROP_ZPOS); |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2706 | pstates[cnt].pipe_id = sde_plane_pipe(plane); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 2707 | |
| 2708 | /* check dim layer stage with every plane */ |
| 2709 | for (i = 0; i < cstate->num_dim_layers; i++) { |
| 2710 | if (pstates[cnt].stage == cstate->dim_layer[i].stage) { |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 2711 | SDE_ERROR( |
| 2712 | "plane:%d/dim_layer:%i-same stage:%d\n", |
| 2713 | plane->base.id, i, |
| 2714 | cstate->dim_layer[i].stage); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 2715 | rc = -EINVAL; |
| 2716 | goto end; |
| 2717 | } |
| 2718 | } |
| 2719 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2720 | if (pipe_staged[pstates[cnt].pipe_id]) { |
| 2721 | multirect_plane[multirect_count].r0 = |
| 2722 | pipe_staged[pstates[cnt].pipe_id]; |
| 2723 | multirect_plane[multirect_count].r1 = pstate; |
| 2724 | multirect_count++; |
| 2725 | |
| 2726 | pipe_staged[pstates[cnt].pipe_id] = NULL; |
| 2727 | } else { |
| 2728 | pipe_staged[pstates[cnt].pipe_id] = pstate; |
| 2729 | } |
| 2730 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2731 | cnt++; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2732 | |
| 2733 | if (CHECK_LAYER_BOUNDS(pstate->crtc_y, pstate->crtc_h, |
| 2734 | mode->vdisplay) || |
| 2735 | CHECK_LAYER_BOUNDS(pstate->crtc_x, pstate->crtc_w, |
| 2736 | mode->hdisplay)) { |
| 2737 | SDE_ERROR("invalid vertical/horizontal destination\n"); |
| 2738 | SDE_ERROR("y:%d h:%d vdisp:%d x:%d w:%d hdisp:%d\n", |
| 2739 | pstate->crtc_y, pstate->crtc_h, mode->vdisplay, |
| 2740 | pstate->crtc_x, pstate->crtc_w, mode->hdisplay); |
| 2741 | rc = -E2BIG; |
| 2742 | goto end; |
| 2743 | } |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2744 | } |
| 2745 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2746 | for (i = 1; i < SSPP_MAX; i++) { |
Jeykumar Sankaran | e964dc7 | 2017-05-10 19:26:43 -0700 | [diff] [blame] | 2747 | if (pipe_staged[i]) { |
| 2748 | sde_plane_clear_multirect(pipe_staged[i]); |
| 2749 | |
| 2750 | if (is_sde_plane_virtual(pipe_staged[i]->plane)) { |
| 2751 | SDE_ERROR("invalid use of virtual plane: %d\n", |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2752 | pipe_staged[i]->plane->base.id); |
Jeykumar Sankaran | e964dc7 | 2017-05-10 19:26:43 -0700 | [diff] [blame] | 2753 | goto end; |
| 2754 | } |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2755 | } |
| 2756 | } |
| 2757 | |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2758 | /* assign mixer stages based on sorted zpos property */ |
| 2759 | sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL); |
| 2760 | |
Dhaval Patel | a8d6bc6 | 2017-05-10 17:40:18 -0700 | [diff] [blame] | 2761 | rc = _sde_crtc_excl_dim_layer_check(state, pstates, cnt); |
| 2762 | if (rc) |
| 2763 | goto end; |
| 2764 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2765 | if (!sde_is_custom_client()) { |
| 2766 | int stage_old = pstates[0].stage; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2767 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2768 | z_pos = 0; |
| 2769 | for (i = 0; i < cnt; i++) { |
| 2770 | if (stage_old != pstates[i].stage) |
| 2771 | ++z_pos; |
| 2772 | stage_old = pstates[i].stage; |
| 2773 | pstates[i].stage = z_pos; |
| 2774 | } |
| 2775 | } |
| 2776 | |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2777 | z_pos = -1; |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2778 | for (i = 0; i < cnt; i++) { |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2779 | /* reset counts at every new blend stage */ |
| 2780 | if (pstates[i].stage != z_pos) { |
| 2781 | left_zpos_cnt = 0; |
| 2782 | right_zpos_cnt = 0; |
| 2783 | z_pos = pstates[i].stage; |
| 2784 | } |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2785 | |
| 2786 | /* verify z_pos setting before using it */ |
Clarence Ip | 649989a | 2016-10-21 14:28:34 -0400 | [diff] [blame] | 2787 | if (z_pos >= SDE_STAGE_MAX - SDE_STAGE_0) { |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2788 | SDE_ERROR("> %d plane stages assigned\n", |
| 2789 | SDE_STAGE_MAX - SDE_STAGE_0); |
| 2790 | rc = -EINVAL; |
| 2791 | goto end; |
| 2792 | } else if (pstates[i].drm_pstate->crtc_x < mixer_width) { |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2793 | if (left_zpos_cnt == 2) { |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2794 | SDE_ERROR("> 2 planes @ stage %d on left\n", |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2795 | z_pos); |
| 2796 | rc = -EINVAL; |
| 2797 | goto end; |
| 2798 | } |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2799 | left_zpos_cnt++; |
| 2800 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2801 | } else { |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2802 | if (right_zpos_cnt == 2) { |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2803 | SDE_ERROR("> 2 planes @ stage %d on right\n", |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2804 | z_pos); |
| 2805 | rc = -EINVAL; |
| 2806 | goto end; |
| 2807 | } |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2808 | right_zpos_cnt++; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2809 | } |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2810 | |
Clarence Ip | c47a069 | 2016-10-11 10:54:17 -0400 | [diff] [blame] | 2811 | pstates[i].sde_pstate->stage = z_pos + SDE_STAGE_0; |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2812 | SDE_DEBUG("%s: zpos %d", sde_crtc->name, z_pos); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2813 | } |
| 2814 | |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2815 | for (i = 0; i < multirect_count; i++) { |
| 2816 | if (sde_plane_validate_multirect_v2(&multirect_plane[i])) { |
| 2817 | SDE_ERROR( |
| 2818 | "multirect validation failed for planes (%d - %d)\n", |
| 2819 | multirect_plane[i].r0->plane->base.id, |
| 2820 | multirect_plane[i].r1->plane->base.id); |
| 2821 | rc = -EINVAL; |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 2822 | goto end; |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 2823 | } |
| 2824 | } |
| 2825 | |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 2826 | rc = sde_core_perf_crtc_check(crtc, state); |
| 2827 | if (rc) { |
| 2828 | SDE_ERROR("crtc%d failed performance check %d\n", |
| 2829 | crtc->base.id, rc); |
| 2830 | goto end; |
| 2831 | } |
| 2832 | |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 2833 | /* validate source split: |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2834 | * use pstates sorted by stage to check planes on same stage |
| 2835 | * we assume that all pipes are in source split so its valid to compare |
| 2836 | * without taking into account left/right mixer placement |
| 2837 | */ |
| 2838 | for (i = 1; i < cnt; i++) { |
| 2839 | struct plane_state *prv_pstate, *cur_pstate; |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 2840 | struct sde_rect left_rect, right_rect; |
| 2841 | int32_t left_pid, right_pid; |
| 2842 | int32_t stage; |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2843 | |
| 2844 | prv_pstate = &pstates[i - 1]; |
| 2845 | cur_pstate = &pstates[i]; |
| 2846 | if (prv_pstate->stage != cur_pstate->stage) |
| 2847 | continue; |
| 2848 | |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 2849 | stage = cur_pstate->stage; |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2850 | |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 2851 | left_pid = prv_pstate->sde_pstate->base.plane->base.id; |
| 2852 | POPULATE_RECT(&left_rect, prv_pstate->drm_pstate->crtc_x, |
| 2853 | prv_pstate->drm_pstate->crtc_y, |
| 2854 | prv_pstate->drm_pstate->crtc_w, |
| 2855 | prv_pstate->drm_pstate->crtc_h, false); |
| 2856 | |
| 2857 | right_pid = cur_pstate->sde_pstate->base.plane->base.id; |
| 2858 | POPULATE_RECT(&right_rect, cur_pstate->drm_pstate->crtc_x, |
| 2859 | cur_pstate->drm_pstate->crtc_y, |
| 2860 | cur_pstate->drm_pstate->crtc_w, |
| 2861 | cur_pstate->drm_pstate->crtc_h, false); |
| 2862 | |
| 2863 | if (right_rect.x < left_rect.x) { |
| 2864 | swap(left_pid, right_pid); |
| 2865 | swap(left_rect, right_rect); |
| 2866 | } |
| 2867 | |
| 2868 | /** |
| 2869 | * - planes are enumerated in pipe-priority order such that |
| 2870 | * planes with lower drm_id must be left-most in a shared |
| 2871 | * blend-stage when using source split. |
| 2872 | * - planes in source split must be contiguous in width |
| 2873 | * - planes in source split must have same dest yoff and height |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2874 | */ |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 2875 | if (right_pid < left_pid) { |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2876 | SDE_ERROR( |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 2877 | "invalid src split cfg. priority mismatch. stage: %d left: %d right: %d\n", |
| 2878 | stage, left_pid, right_pid); |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2879 | rc = -EINVAL; |
| 2880 | goto end; |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 2881 | } else if (right_rect.x != (left_rect.x + left_rect.w)) { |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2882 | SDE_ERROR( |
Jeykumar Sankaran | aaaa071 | 2017-06-12 17:59:16 -0700 | [diff] [blame] | 2883 | "non-contiguous coordinates for src split. stage: %d left: %d - %d right: %d - %d\n", |
| 2884 | stage, left_rect.x, left_rect.w, |
| 2885 | right_rect.x, right_rect.w); |
| 2886 | rc = -EINVAL; |
| 2887 | goto end; |
| 2888 | } else if ((left_rect.y != right_rect.y) || |
| 2889 | (left_rect.h != right_rect.h)) { |
| 2890 | SDE_ERROR( |
| 2891 | "source split at stage: %d. invalid yoff/height: l_y: %d r_y: %d l_h: %d r_h: %d\n", |
| 2892 | stage, left_rect.y, right_rect.y, |
| 2893 | left_rect.h, right_rect.h); |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2894 | rc = -EINVAL; |
| 2895 | goto end; |
| 2896 | } |
| 2897 | } |
| 2898 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 2899 | rc = _sde_crtc_check_rois(crtc, state); |
| 2900 | if (rc) { |
| 2901 | SDE_ERROR("crtc%d failed roi check %d\n", crtc->base.id, rc); |
| 2902 | goto end; |
| 2903 | } |
Lloyd Atkinson | 629ce1f | 2016-10-27 16:50:26 -0400 | [diff] [blame] | 2904 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2905 | end: |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 2906 | _sde_crtc_rp_free_unused(&cstate->rp); |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 2907 | return rc; |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 2908 | } |
| 2909 | |
Abhijit Kulkarni | 7acb326 | 2016-07-05 15:27:25 -0400 | [diff] [blame] | 2910 | int sde_crtc_vblank(struct drm_crtc *crtc, bool en) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2911 | { |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2912 | struct sde_crtc *sde_crtc; |
Clarence Ip | 9728a1d | 2017-04-18 22:22:13 -0400 | [diff] [blame] | 2913 | int rc; |
Abhijit Kulkarni | 7acb326 | 2016-07-05 15:27:25 -0400 | [diff] [blame] | 2914 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2915 | if (!crtc) { |
| 2916 | SDE_ERROR("invalid crtc\n"); |
| 2917 | return -EINVAL; |
| 2918 | } |
| 2919 | sde_crtc = to_sde_crtc(crtc); |
| 2920 | |
| 2921 | mutex_lock(&sde_crtc->crtc_lock); |
Clarence Ip | 9728a1d | 2017-04-18 22:22:13 -0400 | [diff] [blame] | 2922 | rc = _sde_crtc_vblank_no_lock(sde_crtc, en); |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2923 | mutex_unlock(&sde_crtc->crtc_lock); |
Clarence Ip | 9728a1d | 2017-04-18 22:22:13 -0400 | [diff] [blame] | 2924 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 2925 | return rc; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2926 | } |
| 2927 | |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 2928 | void sde_crtc_cancel_pending_flip(struct drm_crtc *crtc, struct drm_file *file) |
| 2929 | { |
| 2930 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
| 2931 | |
Alan Kwong | 163d261 | 2016-11-03 00:56:56 -0400 | [diff] [blame] | 2932 | SDE_DEBUG("%s: cancel: %p\n", sde_crtc->name, file); |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 2933 | _sde_crtc_complete_flip(crtc, file); |
Lloyd Atkinson | 5217336c | 2016-09-15 18:21:18 -0400 | [diff] [blame] | 2934 | } |
| 2935 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2936 | /** |
| 2937 | * sde_crtc_install_properties - install all drm properties for crtc |
| 2938 | * @crtc: Pointer to drm crtc structure |
| 2939 | */ |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 2940 | static void sde_crtc_install_properties(struct drm_crtc *crtc, |
| 2941 | struct sde_mdss_cfg *catalog) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 2942 | { |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2943 | struct sde_crtc *sde_crtc; |
| 2944 | struct drm_device *dev; |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 2945 | struct sde_kms_info *info; |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 2946 | struct sde_kms *sde_kms; |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2947 | |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 2948 | SDE_DEBUG("\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2949 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 2950 | if (!crtc || !catalog) { |
| 2951 | SDE_ERROR("invalid crtc or catalog\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2952 | return; |
| 2953 | } |
| 2954 | |
| 2955 | sde_crtc = to_sde_crtc(crtc); |
| 2956 | dev = crtc->dev; |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 2957 | sde_kms = _sde_crtc_get_kms(crtc); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2958 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 2959 | info = kzalloc(sizeof(struct sde_kms_info), GFP_KERNEL); |
| 2960 | if (!info) { |
| 2961 | SDE_ERROR("failed to allocate info memory\n"); |
| 2962 | return; |
| 2963 | } |
| 2964 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 2965 | /* range properties */ |
| 2966 | msm_property_install_range(&sde_crtc->property_info, |
Dhaval Patel | 4e57484 | 2016-08-23 15:11:37 -0700 | [diff] [blame] | 2967 | "input_fence_timeout", 0x0, 0, SDE_CRTC_MAX_INPUT_FENCE_TIMEOUT, |
| 2968 | SDE_CRTC_INPUT_FENCE_TIMEOUT, CRTC_PROP_INPUT_FENCE_TIMEOUT); |
| 2969 | |
| 2970 | msm_property_install_range(&sde_crtc->property_info, "output_fence", |
| 2971 | 0x0, 0, INR_OPEN_MAX, 0x0, CRTC_PROP_OUTPUT_FENCE); |
Clarence Ip | 1d9728b | 2016-09-01 11:10:54 -0400 | [diff] [blame] | 2972 | |
| 2973 | msm_property_install_range(&sde_crtc->property_info, |
| 2974 | "output_fence_offset", 0x0, 0, 1, 0, |
| 2975 | CRTC_PROP_OUTPUT_FENCE_OFFSET); |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 2976 | |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 2977 | msm_property_install_range(&sde_crtc->property_info, |
| 2978 | "core_clk", 0x0, 0, U64_MAX, |
| 2979 | sde_kms->perf.max_core_clk_rate, |
| 2980 | CRTC_PROP_CORE_CLK); |
| 2981 | msm_property_install_range(&sde_crtc->property_info, |
| 2982 | "core_ab", 0x0, 0, U64_MAX, |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 2983 | catalog->perf.max_bw_high * 1000ULL, |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 2984 | CRTC_PROP_CORE_AB); |
| 2985 | msm_property_install_range(&sde_crtc->property_info, |
| 2986 | "core_ib", 0x0, 0, U64_MAX, |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 2987 | catalog->perf.max_bw_high * 1000ULL, |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 2988 | CRTC_PROP_CORE_IB); |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 2989 | msm_property_install_range(&sde_crtc->property_info, |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame^] | 2990 | "llcc_ab", 0x0, 0, U64_MAX, |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 2991 | catalog->perf.max_bw_high * 1000ULL, |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame^] | 2992 | CRTC_PROP_LLCC_AB); |
Alan Kwong | 8c176bf | 2017-02-09 19:34:32 -0800 | [diff] [blame] | 2993 | msm_property_install_range(&sde_crtc->property_info, |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame^] | 2994 | "llcc_ib", 0x0, 0, U64_MAX, |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 2995 | catalog->perf.max_bw_high * 1000ULL, |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame^] | 2996 | CRTC_PROP_LLCC_IB); |
| 2997 | msm_property_install_range(&sde_crtc->property_info, |
| 2998 | "dram_ab", 0x0, 0, U64_MAX, |
| 2999 | catalog->perf.max_bw_high * 1000ULL, |
| 3000 | CRTC_PROP_DRAM_AB); |
| 3001 | msm_property_install_range(&sde_crtc->property_info, |
| 3002 | "dram_ib", 0x0, 0, U64_MAX, |
| 3003 | catalog->perf.max_bw_high * 1000ULL, |
| 3004 | CRTC_PROP_DRAM_IB); |
Alan Kwong | 8c176bf | 2017-02-09 19:34:32 -0800 | [diff] [blame] | 3005 | msm_property_install_range(&sde_crtc->property_info, |
Alan Kwong | 4aacd53 | 2017-02-04 18:51:33 -0800 | [diff] [blame] | 3006 | "rot_prefill_bw", 0, 0, U64_MAX, |
| 3007 | catalog->perf.max_bw_high * 1000ULL, |
| 3008 | CRTC_PROP_ROT_PREFILL_BW); |
Alan Kwong | 8c176bf | 2017-02-09 19:34:32 -0800 | [diff] [blame] | 3009 | msm_property_install_range(&sde_crtc->property_info, |
| 3010 | "rot_clk", 0, 0, U64_MAX, |
| 3011 | sde_kms->perf.max_core_clk_rate, |
| 3012 | CRTC_PROP_ROT_CLK); |
Alan Kwong | 9aa061c | 2016-11-06 21:17:12 -0500 | [diff] [blame] | 3013 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3014 | msm_property_install_blob(&sde_crtc->property_info, "capabilities", |
| 3015 | DRM_MODE_PROP_IMMUTABLE, CRTC_PROP_INFO); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 3016 | |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 3017 | msm_property_install_volatile_range(&sde_crtc->property_info, |
| 3018 | "sde_drm_roi_v1", 0x0, 0, ~0, 0, CRTC_PROP_ROI_V1); |
| 3019 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3020 | sde_kms_info_reset(info); |
| 3021 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 3022 | if (catalog->has_dim_layer) { |
| 3023 | msm_property_install_volatile_range(&sde_crtc->property_info, |
| 3024 | "dim_layer_v1", 0x0, 0, ~0, 0, CRTC_PROP_DIM_LAYER_V1); |
| 3025 | sde_kms_info_add_keyint(info, "dim_layer_v1_max_layers", |
| 3026 | SDE_MAX_DIM_LAYERS); |
| 3027 | } |
| 3028 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3029 | sde_kms_info_add_keyint(info, "hw_version", catalog->hwversion); |
| 3030 | sde_kms_info_add_keyint(info, "max_linewidth", |
| 3031 | catalog->max_mixer_width); |
| 3032 | sde_kms_info_add_keyint(info, "max_blendstages", |
| 3033 | catalog->max_mixer_blendstages); |
| 3034 | if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED2) |
| 3035 | sde_kms_info_add_keystr(info, "qseed_type", "qseed2"); |
| 3036 | if (catalog->qseed_type == SDE_SSPP_SCALER_QSEED3) |
| 3037 | sde_kms_info_add_keystr(info, "qseed_type", "qseed3"); |
Jeykumar Sankaran | 2e65503 | 2017-02-04 14:05:45 -0800 | [diff] [blame] | 3038 | |
| 3039 | if (sde_is_custom_client()) { |
| 3040 | if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V1) |
| 3041 | sde_kms_info_add_keystr(info, |
| 3042 | "smart_dma_rev", "smart_dma_v1"); |
| 3043 | if (catalog->smart_dma_rev == SDE_SSPP_SMART_DMA_V2) |
| 3044 | sde_kms_info_add_keystr(info, |
| 3045 | "smart_dma_rev", "smart_dma_v2"); |
| 3046 | } |
| 3047 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3048 | sde_kms_info_add_keyint(info, "has_src_split", catalog->has_src_split); |
Alan Kwong | 2f84f8a | 2016-12-29 13:07:47 -0500 | [diff] [blame] | 3049 | if (catalog->perf.max_bw_low) |
| 3050 | sde_kms_info_add_keyint(info, "max_bandwidth_low", |
Alan Kwong | 6259a38 | 2017-04-04 06:18:02 -0700 | [diff] [blame] | 3051 | catalog->perf.max_bw_low * 1000LL); |
Alan Kwong | 2f84f8a | 2016-12-29 13:07:47 -0500 | [diff] [blame] | 3052 | if (catalog->perf.max_bw_high) |
| 3053 | sde_kms_info_add_keyint(info, "max_bandwidth_high", |
Alan Kwong | 6259a38 | 2017-04-04 06:18:02 -0700 | [diff] [blame] | 3054 | catalog->perf.max_bw_high * 1000LL); |
Alan Kwong | 2f84f8a | 2016-12-29 13:07:47 -0500 | [diff] [blame] | 3055 | if (sde_kms->perf.max_core_clk_rate) |
| 3056 | sde_kms_info_add_keyint(info, "max_mdp_clk", |
| 3057 | sde_kms->perf.max_core_clk_rate); |
Alan Kwong | 6259a38 | 2017-04-04 06:18:02 -0700 | [diff] [blame] | 3058 | sde_kms_info_add_keystr(info, "core_ib_ff", |
| 3059 | catalog->perf.core_ib_ff); |
| 3060 | sde_kms_info_add_keystr(info, "core_clk_ff", |
| 3061 | catalog->perf.core_clk_ff); |
| 3062 | sde_kms_info_add_keystr(info, "comp_ratio_rt", |
| 3063 | catalog->perf.comp_ratio_rt); |
| 3064 | sde_kms_info_add_keystr(info, "comp_ratio_nrt", |
| 3065 | catalog->perf.comp_ratio_nrt); |
| 3066 | sde_kms_info_add_keyint(info, "dest_scale_prefill_lines", |
| 3067 | catalog->perf.dest_scale_prefill_lines); |
| 3068 | sde_kms_info_add_keyint(info, "undersized_prefill_lines", |
| 3069 | catalog->perf.undersized_prefill_lines); |
| 3070 | sde_kms_info_add_keyint(info, "macrotile_prefill_lines", |
| 3071 | catalog->perf.macrotile_prefill_lines); |
| 3072 | sde_kms_info_add_keyint(info, "yuv_nv12_prefill_lines", |
| 3073 | catalog->perf.yuv_nv12_prefill_lines); |
| 3074 | sde_kms_info_add_keyint(info, "linear_prefill_lines", |
| 3075 | catalog->perf.linear_prefill_lines); |
| 3076 | sde_kms_info_add_keyint(info, "downscaling_prefill_lines", |
| 3077 | catalog->perf.downscaling_prefill_lines); |
| 3078 | sde_kms_info_add_keyint(info, "xtra_prefill_lines", |
| 3079 | catalog->perf.xtra_prefill_lines); |
| 3080 | sde_kms_info_add_keyint(info, "amortizable_threshold", |
| 3081 | catalog->perf.amortizable_threshold); |
| 3082 | sde_kms_info_add_keyint(info, "min_prefill_lines", |
| 3083 | catalog->perf.min_prefill_lines); |
| 3084 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3085 | msm_property_set_blob(&sde_crtc->property_info, &sde_crtc->blob_info, |
Narendra Muppalla | 22d1725 | 2017-05-31 15:13:39 -0700 | [diff] [blame] | 3086 | info->data, SDE_KMS_INFO_DATALEN(info), CRTC_PROP_INFO); |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3087 | |
| 3088 | kfree(info); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3089 | } |
| 3090 | |
| 3091 | /** |
| 3092 | * sde_crtc_atomic_set_property - atomically set a crtc drm property |
| 3093 | * @crtc: Pointer to drm crtc structure |
| 3094 | * @state: Pointer to drm crtc state structure |
| 3095 | * @property: Pointer to targeted drm property |
| 3096 | * @val: Updated property value |
| 3097 | * @Returns: Zero on success |
| 3098 | */ |
| 3099 | static int sde_crtc_atomic_set_property(struct drm_crtc *crtc, |
| 3100 | struct drm_crtc_state *state, |
| 3101 | struct drm_property *property, |
| 3102 | uint64_t val) |
| 3103 | { |
| 3104 | struct sde_crtc *sde_crtc; |
| 3105 | struct sde_crtc_state *cstate; |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3106 | int idx, ret = -EINVAL; |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3107 | |
| 3108 | if (!crtc || !state || !property) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3109 | SDE_ERROR("invalid argument(s)\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3110 | } else { |
| 3111 | sde_crtc = to_sde_crtc(crtc); |
| 3112 | cstate = to_sde_crtc_state(state); |
| 3113 | ret = msm_property_atomic_set(&sde_crtc->property_info, |
| 3114 | cstate->property_values, cstate->property_blobs, |
| 3115 | property, val); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3116 | if (!ret) { |
| 3117 | idx = msm_property_index(&sde_crtc->property_info, |
| 3118 | property); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 3119 | switch (idx) { |
| 3120 | case CRTC_PROP_INPUT_FENCE_TIMEOUT: |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3121 | _sde_crtc_set_input_fence_timeout(cstate); |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 3122 | break; |
| 3123 | case CRTC_PROP_DIM_LAYER_V1: |
| 3124 | _sde_crtc_set_dim_layer_v1(cstate, (void *)val); |
| 3125 | break; |
Lloyd Atkinson | 8ba4703 | 2017-03-22 17:13:32 -0400 | [diff] [blame] | 3126 | case CRTC_PROP_ROI_V1: |
| 3127 | ret = _sde_crtc_set_roi_v1(state, (void *)val); |
| 3128 | break; |
Alan Kwong | 8411a911 | 2017-06-06 19:29:01 -0400 | [diff] [blame] | 3129 | case CRTC_PROP_CORE_CLK: |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 3130 | case CRTC_PROP_CORE_AB: |
| 3131 | case CRTC_PROP_CORE_IB: |
Alan Kwong | ff30f4a | 2017-05-23 12:02:00 -0700 | [diff] [blame] | 3132 | cstate->bw_control = true; |
| 3133 | break; |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame^] | 3134 | case CRTC_PROP_LLCC_AB: |
| 3135 | case CRTC_PROP_LLCC_IB: |
| 3136 | case CRTC_PROP_DRAM_AB: |
| 3137 | case CRTC_PROP_DRAM_IB: |
| 3138 | cstate->bw_control = true; |
| 3139 | cstate->bw_split_vote = true; |
| 3140 | break; |
Veera Sundaram Sankaran | 3171ff8 | 2017-01-04 14:34:47 -0800 | [diff] [blame] | 3141 | default: |
| 3142 | /* nothing to do */ |
| 3143 | break; |
| 3144 | } |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 3145 | } else { |
| 3146 | ret = sde_cp_crtc_set_property(crtc, |
| 3147 | property, val); |
Clarence Ip | cae1bb6 | 2016-07-07 12:07:13 -0400 | [diff] [blame] | 3148 | } |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 3149 | if (ret) |
| 3150 | DRM_ERROR("failed to set the property\n"); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 3151 | |
| 3152 | SDE_DEBUG("crtc%d %s[%d] <= 0x%llx ret=%d\n", crtc->base.id, |
| 3153 | property->name, property->base.id, val, ret); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3154 | } |
| 3155 | |
| 3156 | return ret; |
| 3157 | } |
| 3158 | |
| 3159 | /** |
| 3160 | * sde_crtc_set_property - set a crtc drm property |
| 3161 | * @crtc: Pointer to drm crtc structure |
| 3162 | * @property: Pointer to targeted drm property |
| 3163 | * @val: Updated property value |
| 3164 | * @Returns: Zero on success |
| 3165 | */ |
| 3166 | static int sde_crtc_set_property(struct drm_crtc *crtc, |
| 3167 | struct drm_property *property, uint64_t val) |
| 3168 | { |
Lloyd Atkinson | 4f1c869 | 2016-09-14 14:04:25 -0400 | [diff] [blame] | 3169 | SDE_DEBUG("\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3170 | |
| 3171 | return sde_crtc_atomic_set_property(crtc, crtc->state, property, val); |
| 3172 | } |
| 3173 | |
| 3174 | /** |
| 3175 | * sde_crtc_atomic_get_property - retrieve a crtc drm property |
| 3176 | * @crtc: Pointer to drm crtc structure |
| 3177 | * @state: Pointer to drm crtc state structure |
| 3178 | * @property: Pointer to targeted drm property |
| 3179 | * @val: Pointer to variable for receiving property value |
| 3180 | * @Returns: Zero on success |
| 3181 | */ |
| 3182 | static int sde_crtc_atomic_get_property(struct drm_crtc *crtc, |
| 3183 | const struct drm_crtc_state *state, |
| 3184 | struct drm_property *property, |
| 3185 | uint64_t *val) |
| 3186 | { |
| 3187 | struct sde_crtc *sde_crtc; |
| 3188 | struct sde_crtc_state *cstate; |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 3189 | int i, ret = -EINVAL; |
Dhaval Patel | 5cb59be | 2017-04-20 20:00:56 -0700 | [diff] [blame] | 3190 | bool conn_offset = 0; |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3191 | |
| 3192 | if (!crtc || !state) { |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3193 | SDE_ERROR("invalid argument(s)\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3194 | } else { |
| 3195 | sde_crtc = to_sde_crtc(crtc); |
| 3196 | cstate = to_sde_crtc_state(state); |
Dhaval Patel | 5cb59be | 2017-04-20 20:00:56 -0700 | [diff] [blame] | 3197 | |
| 3198 | for (i = 0; i < cstate->num_connectors; ++i) { |
| 3199 | conn_offset = sde_connector_needs_offset( |
| 3200 | cstate->connectors[i]); |
| 3201 | if (conn_offset) |
| 3202 | break; |
| 3203 | } |
| 3204 | |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 3205 | i = msm_property_index(&sde_crtc->property_info, property); |
| 3206 | if (i == CRTC_PROP_OUTPUT_FENCE) { |
Dhaval Patel | 39323d4 | 2017-03-01 23:48:24 -0800 | [diff] [blame] | 3207 | uint32_t offset = sde_crtc_get_property(cstate, |
Clarence Ip | 1d9728b | 2016-09-01 11:10:54 -0400 | [diff] [blame] | 3208 | CRTC_PROP_OUTPUT_FENCE_OFFSET); |
| 3209 | |
Dhaval Patel | 5cb59be | 2017-04-20 20:00:56 -0700 | [diff] [blame] | 3210 | ret = sde_fence_create(&sde_crtc->output_fence, val, |
| 3211 | offset + conn_offset); |
Clarence Ip | 1d9728b | 2016-09-01 11:10:54 -0400 | [diff] [blame] | 3212 | if (ret) |
| 3213 | SDE_ERROR("fence create failed\n"); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 3214 | } else { |
| 3215 | ret = msm_property_atomic_get(&sde_crtc->property_info, |
| 3216 | cstate->property_values, |
| 3217 | cstate->property_blobs, property, val); |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 3218 | if (ret) |
| 3219 | ret = sde_cp_crtc_get_property(crtc, |
| 3220 | property, val); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 3221 | } |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 3222 | if (ret) |
| 3223 | DRM_ERROR("get property failed\n"); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3224 | } |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3225 | return ret; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3226 | } |
| 3227 | |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3228 | #ifdef CONFIG_DEBUG_FS |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3229 | static int _sde_debugfs_status_show(struct seq_file *s, void *data) |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3230 | { |
| 3231 | struct sde_crtc *sde_crtc; |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3232 | struct sde_plane_state *pstate = NULL; |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3233 | struct sde_crtc_mixer *m; |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3234 | |
| 3235 | struct drm_crtc *crtc; |
| 3236 | struct drm_plane *plane; |
| 3237 | struct drm_display_mode *mode; |
| 3238 | struct drm_framebuffer *fb; |
| 3239 | struct drm_plane_state *state; |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 3240 | struct sde_crtc_state *cstate; |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3241 | |
| 3242 | int i, out_width; |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3243 | |
| 3244 | if (!s || !s->private) |
| 3245 | return -EINVAL; |
| 3246 | |
| 3247 | sde_crtc = s->private; |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3248 | crtc = &sde_crtc->base; |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 3249 | cstate = to_sde_crtc_state(crtc->state); |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3250 | |
| 3251 | mutex_lock(&sde_crtc->crtc_lock); |
| 3252 | mode = &crtc->state->adjusted_mode; |
| 3253 | out_width = sde_crtc_mixer_width(sde_crtc, mode); |
| 3254 | |
| 3255 | seq_printf(s, "crtc:%d width:%d height:%d\n", crtc->base.id, |
| 3256 | mode->hdisplay, mode->vdisplay); |
| 3257 | |
| 3258 | seq_puts(s, "\n"); |
| 3259 | |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3260 | for (i = 0; i < sde_crtc->num_mixers; ++i) { |
Lloyd Atkinson | e7bcdd2 | 2016-08-11 10:53:37 -0400 | [diff] [blame] | 3261 | m = &sde_crtc->mixers[i]; |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3262 | if (!m->hw_lm) |
| 3263 | seq_printf(s, "\tmixer[%d] has no lm\n", i); |
| 3264 | else if (!m->hw_ctl) |
| 3265 | seq_printf(s, "\tmixer[%d] has no ctl\n", i); |
| 3266 | else |
| 3267 | seq_printf(s, "\tmixer:%d ctl:%d width:%d height:%d\n", |
| 3268 | m->hw_lm->idx - LM_0, m->hw_ctl->idx - CTL_0, |
| 3269 | out_width, mode->vdisplay); |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3270 | } |
Dhaval Patel | 44f1247 | 2016-08-29 12:19:47 -0700 | [diff] [blame] | 3271 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3272 | seq_puts(s, "\n"); |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 3273 | |
Veera Sundaram Sankaran | 2cb064f | 2017-05-05 14:12:17 -0700 | [diff] [blame] | 3274 | for (i = 0; i < cstate->num_dim_layers; i++) { |
| 3275 | struct sde_hw_dim_layer *dim_layer = &cstate->dim_layer[i]; |
| 3276 | |
| 3277 | seq_printf(s, "\tdim_layer:%d] stage:%d flags:%d\n", |
| 3278 | i, dim_layer->stage, dim_layer->flags); |
| 3279 | seq_printf(s, "\tdst_x:%d dst_y:%d dst_w:%d dst_h:%d\n", |
| 3280 | dim_layer->rect.x, dim_layer->rect.y, |
| 3281 | dim_layer->rect.w, dim_layer->rect.h); |
| 3282 | seq_printf(s, |
| 3283 | "\tcolor_0:%d color_1:%d color_2:%d color_3:%d\n", |
| 3284 | dim_layer->color_fill.color_0, |
| 3285 | dim_layer->color_fill.color_1, |
| 3286 | dim_layer->color_fill.color_2, |
| 3287 | dim_layer->color_fill.color_3); |
| 3288 | seq_puts(s, "\n"); |
| 3289 | } |
| 3290 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3291 | drm_atomic_crtc_for_each_plane(plane, crtc) { |
| 3292 | pstate = to_sde_plane_state(plane->state); |
| 3293 | state = plane->state; |
| 3294 | |
| 3295 | if (!pstate || !state) |
| 3296 | continue; |
| 3297 | |
| 3298 | seq_printf(s, "\tplane:%u stage:%d\n", plane->base.id, |
| 3299 | pstate->stage); |
| 3300 | |
| 3301 | if (plane->state->fb) { |
| 3302 | fb = plane->state->fb; |
| 3303 | |
| 3304 | seq_printf(s, "\tfb:%d image format:%4.4s wxh:%ux%u bpp:%d\n", |
| 3305 | fb->base.id, (char *) &fb->pixel_format, |
| 3306 | fb->width, fb->height, fb->bits_per_pixel); |
| 3307 | |
| 3308 | seq_puts(s, "\t"); |
| 3309 | for (i = 0; i < ARRAY_SIZE(fb->modifier); i++) |
| 3310 | seq_printf(s, "modifier[%d]:%8llu ", i, |
| 3311 | fb->modifier[i]); |
| 3312 | seq_puts(s, "\n"); |
| 3313 | |
| 3314 | seq_puts(s, "\t"); |
| 3315 | for (i = 0; i < ARRAY_SIZE(fb->pitches); i++) |
| 3316 | seq_printf(s, "pitches[%d]:%8u ", i, |
| 3317 | fb->pitches[i]); |
| 3318 | seq_puts(s, "\n"); |
| 3319 | |
| 3320 | seq_puts(s, "\t"); |
| 3321 | for (i = 0; i < ARRAY_SIZE(fb->offsets); i++) |
| 3322 | seq_printf(s, "offsets[%d]:%8u ", i, |
| 3323 | fb->offsets[i]); |
Dhaval Patel | 48c7602 | 2016-09-01 17:51:23 -0700 | [diff] [blame] | 3324 | seq_puts(s, "\n"); |
| 3325 | } |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3326 | |
| 3327 | seq_printf(s, "\tsrc_x:%4d src_y:%4d src_w:%4d src_h:%4d\n", |
| 3328 | state->src_x, state->src_y, state->src_w, state->src_h); |
| 3329 | |
| 3330 | seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", |
| 3331 | state->crtc_x, state->crtc_y, state->crtc_w, |
| 3332 | state->crtc_h); |
Jeykumar Sankaran | e964dc7 | 2017-05-10 19:26:43 -0700 | [diff] [blame] | 3333 | seq_printf(s, "\tmultirect: mode: %d index: %d\n", |
| 3334 | pstate->multirect_mode, pstate->multirect_index); |
Veera Sundaram Sankaran | 58e1281 | 2017-05-05 11:51:09 -0700 | [diff] [blame] | 3335 | |
| 3336 | seq_printf(s, "\texcl_rect: x:%4d y:%4d w:%4d h:%4d\n", |
| 3337 | pstate->excl_rect.x, pstate->excl_rect.y, |
| 3338 | pstate->excl_rect.w, pstate->excl_rect.h); |
| 3339 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3340 | seq_puts(s, "\n"); |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3341 | } |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 3342 | |
| 3343 | if (sde_crtc->vblank_cb_count) { |
| 3344 | ktime_t diff = ktime_sub(ktime_get(), sde_crtc->vblank_cb_time); |
| 3345 | s64 diff_ms = ktime_to_ms(diff); |
| 3346 | s64 fps = diff_ms ? DIV_ROUND_CLOSEST( |
| 3347 | sde_crtc->vblank_cb_count * 1000, diff_ms) : 0; |
| 3348 | |
| 3349 | seq_printf(s, |
Dhaval Patel | d67cf4a | 2017-06-14 18:08:32 -0700 | [diff] [blame] | 3350 | "vblank fps:%lld count:%u total:%llums total_framecount:%llu\n", |
| 3351 | fps, sde_crtc->vblank_cb_count, |
| 3352 | ktime_to_ms(diff), sde_crtc->play_count); |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 3353 | |
| 3354 | /* reset time & count for next measurement */ |
| 3355 | sde_crtc->vblank_cb_count = 0; |
| 3356 | sde_crtc->vblank_cb_time = ktime_set(0, 0); |
| 3357 | } |
| 3358 | |
| 3359 | seq_printf(s, "vblank_refcount:%d\n", |
| 3360 | atomic_read(&sde_crtc->vblank_refcount)); |
| 3361 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3362 | mutex_unlock(&sde_crtc->crtc_lock); |
| 3363 | |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3364 | return 0; |
| 3365 | } |
| 3366 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3367 | static int _sde_debugfs_status_open(struct inode *inode, struct file *file) |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3368 | { |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3369 | return single_open(file, _sde_debugfs_status_show, inode->i_private); |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3370 | } |
| 3371 | |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 3372 | static ssize_t _sde_crtc_misr_setup(struct file *file, |
| 3373 | const char __user *user_buf, size_t count, loff_t *ppos) |
| 3374 | { |
| 3375 | struct sde_crtc *sde_crtc; |
| 3376 | struct sde_crtc_mixer *m; |
| 3377 | int i = 0, rc; |
| 3378 | char buf[MISR_BUFF_SIZE + 1]; |
| 3379 | u32 frame_count, enable; |
| 3380 | size_t buff_copy; |
| 3381 | |
| 3382 | if (!file || !file->private_data) |
| 3383 | return -EINVAL; |
| 3384 | |
| 3385 | sde_crtc = file->private_data; |
| 3386 | buff_copy = min_t(size_t, count, MISR_BUFF_SIZE); |
| 3387 | if (copy_from_user(buf, user_buf, buff_copy)) { |
| 3388 | SDE_ERROR("buffer copy failed\n"); |
| 3389 | return -EINVAL; |
| 3390 | } |
| 3391 | |
| 3392 | buf[buff_copy] = 0; /* end of string */ |
| 3393 | |
| 3394 | if (sscanf(buf, "%u %u", &enable, &frame_count) != 2) |
| 3395 | return -EINVAL; |
| 3396 | |
| 3397 | rc = _sde_crtc_power_enable(sde_crtc, true); |
| 3398 | if (rc) |
| 3399 | return rc; |
| 3400 | |
| 3401 | mutex_lock(&sde_crtc->crtc_lock); |
| 3402 | sde_crtc->misr_enable = enable; |
| 3403 | for (i = 0; i < sde_crtc->num_mixers; ++i) { |
| 3404 | m = &sde_crtc->mixers[i]; |
| 3405 | if (!m->hw_lm) |
| 3406 | continue; |
| 3407 | |
| 3408 | m->hw_lm->ops.setup_misr(m->hw_lm, enable, frame_count); |
| 3409 | } |
| 3410 | mutex_unlock(&sde_crtc->crtc_lock); |
| 3411 | _sde_crtc_power_enable(sde_crtc, false); |
| 3412 | |
| 3413 | return count; |
| 3414 | } |
| 3415 | |
| 3416 | static ssize_t _sde_crtc_misr_read(struct file *file, |
| 3417 | char __user *user_buff, size_t count, loff_t *ppos) |
| 3418 | { |
| 3419 | struct sde_crtc *sde_crtc; |
| 3420 | struct sde_crtc_mixer *m; |
| 3421 | int i = 0, rc; |
| 3422 | ssize_t len = 0; |
| 3423 | char buf[MISR_BUFF_SIZE + 1] = {'\0'}; |
| 3424 | |
| 3425 | if (*ppos) |
| 3426 | return 0; |
| 3427 | |
| 3428 | if (!file || !file->private_data) |
| 3429 | return -EINVAL; |
| 3430 | |
| 3431 | sde_crtc = file->private_data; |
| 3432 | rc = _sde_crtc_power_enable(sde_crtc, true); |
| 3433 | if (rc) |
| 3434 | return rc; |
| 3435 | |
| 3436 | mutex_lock(&sde_crtc->crtc_lock); |
| 3437 | if (!sde_crtc->misr_enable) { |
| 3438 | len += snprintf(buf + len, MISR_BUFF_SIZE - len, |
| 3439 | "disabled\n"); |
| 3440 | goto buff_check; |
| 3441 | } |
| 3442 | |
| 3443 | for (i = 0; i < sde_crtc->num_mixers; ++i) { |
| 3444 | m = &sde_crtc->mixers[i]; |
| 3445 | if (!m->hw_lm) |
| 3446 | continue; |
| 3447 | |
| 3448 | len += snprintf(buf + len, MISR_BUFF_SIZE - len, "lm idx:%d\n", |
| 3449 | m->hw_lm->idx - LM_0); |
| 3450 | len += snprintf(buf + len, MISR_BUFF_SIZE - len, "0x%x\n", |
| 3451 | m->hw_lm->ops.collect_misr(m->hw_lm)); |
| 3452 | } |
| 3453 | |
| 3454 | buff_check: |
| 3455 | if (count <= len) { |
| 3456 | len = 0; |
| 3457 | goto end; |
| 3458 | } |
| 3459 | |
| 3460 | if (copy_to_user(user_buff, buf, len)) { |
| 3461 | len = -EFAULT; |
| 3462 | goto end; |
| 3463 | } |
| 3464 | |
| 3465 | *ppos += len; /* increase offset */ |
| 3466 | |
| 3467 | end: |
| 3468 | mutex_unlock(&sde_crtc->crtc_lock); |
| 3469 | _sde_crtc_power_enable(sde_crtc, false); |
| 3470 | return len; |
| 3471 | } |
| 3472 | |
| 3473 | #define DEFINE_SDE_DEBUGFS_SEQ_FOPS(__prefix) \ |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3474 | static int __prefix ## _open(struct inode *inode, struct file *file) \ |
| 3475 | { \ |
| 3476 | return single_open(file, __prefix ## _show, inode->i_private); \ |
| 3477 | } \ |
| 3478 | static const struct file_operations __prefix ## _fops = { \ |
| 3479 | .owner = THIS_MODULE, \ |
| 3480 | .open = __prefix ## _open, \ |
| 3481 | .release = single_release, \ |
| 3482 | .read = seq_read, \ |
| 3483 | .llseek = seq_lseek, \ |
| 3484 | } |
| 3485 | |
| 3486 | static int sde_crtc_debugfs_state_show(struct seq_file *s, void *v) |
| 3487 | { |
| 3488 | struct drm_crtc *crtc = (struct drm_crtc *) s->private; |
Alan Kwong | 751cf46 | 2017-06-08 10:26:46 -0400 | [diff] [blame] | 3489 | struct sde_crtc *sde_crtc = to_sde_crtc(crtc); |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3490 | struct sde_crtc_state *cstate = to_sde_crtc_state(crtc->state); |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 3491 | struct sde_crtc_res *res; |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame^] | 3492 | int i; |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3493 | |
| 3494 | seq_printf(s, "num_connectors: %d\n", cstate->num_connectors); |
Dhaval Patel | 4d42460 | 2017-02-18 19:40:14 -0800 | [diff] [blame] | 3495 | seq_printf(s, "client type: %d\n", sde_crtc_get_client_type(crtc)); |
Alan Kwong | 3e985f0 | 2017-02-12 15:08:44 -0800 | [diff] [blame] | 3496 | seq_printf(s, "intf_mode: %d\n", sde_crtc_get_intf_mode(crtc)); |
Alan Kwong | 751cf46 | 2017-06-08 10:26:46 -0400 | [diff] [blame] | 3497 | seq_printf(s, "core_clk_rate: %llu\n", |
| 3498 | sde_crtc->cur_perf.core_clk_rate); |
Alan Kwong | 0230a10 | 2017-05-16 11:36:44 -0700 | [diff] [blame^] | 3499 | for (i = SDE_POWER_HANDLE_DBUS_ID_MNOC; |
| 3500 | i < SDE_POWER_HANDLE_DBUS_ID_MAX; i++) { |
| 3501 | seq_printf(s, "bw_ctl[%s]: %llu\n", |
| 3502 | sde_power_handle_get_dbus_name(i), |
| 3503 | sde_crtc->cur_perf.bw_ctl[i]); |
| 3504 | seq_printf(s, "max_per_pipe_ib[%s]: %llu\n", |
| 3505 | sde_power_handle_get_dbus_name(i), |
| 3506 | sde_crtc->cur_perf.max_per_pipe_ib[i]); |
| 3507 | } |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3508 | |
Alan Kwong | cdb2f28 | 2017-03-18 13:42:06 -0700 | [diff] [blame] | 3509 | seq_printf(s, "rp.%d: ", cstate->rp.sequence_id); |
| 3510 | list_for_each_entry(res, &cstate->rp.res_list, list) |
| 3511 | seq_printf(s, "0x%x/0x%llx/%pK/%d ", |
| 3512 | res->type, res->tag, res->val, |
| 3513 | atomic_read(&res->refcount)); |
| 3514 | seq_puts(s, "\n"); |
| 3515 | |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3516 | return 0; |
| 3517 | } |
| 3518 | DEFINE_SDE_DEBUGFS_SEQ_FOPS(sde_crtc_debugfs_state); |
| 3519 | |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3520 | static int _sde_crtc_init_debugfs(struct drm_crtc *crtc) |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3521 | { |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3522 | struct sde_crtc *sde_crtc; |
| 3523 | struct sde_kms *sde_kms; |
| 3524 | |
Dhaval Patel | 3fbe6bf | 2016-10-20 20:00:41 -0700 | [diff] [blame] | 3525 | static const struct file_operations debugfs_status_fops = { |
| 3526 | .open = _sde_debugfs_status_open, |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3527 | .read = seq_read, |
| 3528 | .llseek = seq_lseek, |
| 3529 | .release = single_release, |
| 3530 | }; |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 3531 | static const struct file_operations debugfs_misr_fops = { |
| 3532 | .open = simple_open, |
| 3533 | .read = _sde_crtc_misr_read, |
| 3534 | .write = _sde_crtc_misr_setup, |
| 3535 | }; |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3536 | |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3537 | if (!crtc) |
| 3538 | return -EINVAL; |
| 3539 | sde_crtc = to_sde_crtc(crtc); |
| 3540 | |
| 3541 | sde_kms = _sde_crtc_get_kms(crtc); |
| 3542 | if (!sde_kms) |
| 3543 | return -EINVAL; |
| 3544 | |
| 3545 | sde_crtc->debugfs_root = debugfs_create_dir(sde_crtc->name, |
Lloyd Atkinson | 09e64bf | 2017-04-13 14:09:59 -0700 | [diff] [blame] | 3546 | crtc->dev->primary->debugfs_root); |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3547 | if (!sde_crtc->debugfs_root) |
| 3548 | return -ENOMEM; |
| 3549 | |
| 3550 | /* don't error check these */ |
Lloyd Atkinson | 8de415a | 2017-05-23 11:31:16 -0400 | [diff] [blame] | 3551 | debugfs_create_file("status", 0400, |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3552 | sde_crtc->debugfs_root, |
| 3553 | sde_crtc, &debugfs_status_fops); |
Lloyd Atkinson | 8de415a | 2017-05-23 11:31:16 -0400 | [diff] [blame] | 3554 | debugfs_create_file("state", 0600, |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3555 | sde_crtc->debugfs_root, |
| 3556 | &sde_crtc->base, |
| 3557 | &sde_crtc_debugfs_state_fops); |
Lloyd Atkinson | 8de415a | 2017-05-23 11:31:16 -0400 | [diff] [blame] | 3558 | debugfs_create_file("misr_data", 0600, sde_crtc->debugfs_root, |
Dhaval Patel | f9245d6 | 2017-03-28 16:24:00 -0700 | [diff] [blame] | 3559 | sde_crtc, &debugfs_misr_fops); |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3560 | |
| 3561 | return 0; |
| 3562 | } |
| 3563 | |
| 3564 | static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc) |
| 3565 | { |
| 3566 | struct sde_crtc *sde_crtc; |
| 3567 | |
| 3568 | if (!crtc) |
| 3569 | return; |
| 3570 | sde_crtc = to_sde_crtc(crtc); |
| 3571 | debugfs_remove_recursive(sde_crtc->debugfs_root); |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3572 | } |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3573 | #else |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3574 | static int _sde_crtc_init_debugfs(struct drm_crtc *crtc) |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3575 | { |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3576 | return 0; |
Alan Kwong | 67a3f79 | 2016-11-01 23:16:53 -0400 | [diff] [blame] | 3577 | } |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3578 | |
| 3579 | static void _sde_crtc_destroy_debugfs(struct drm_crtc *crtc) |
| 3580 | { |
Lloyd Atkinson | b020e0f | 2017-03-14 08:05:18 -0700 | [diff] [blame] | 3581 | } |
| 3582 | #endif /* CONFIG_DEBUG_FS */ |
| 3583 | |
| 3584 | static int sde_crtc_late_register(struct drm_crtc *crtc) |
| 3585 | { |
| 3586 | return _sde_crtc_init_debugfs(crtc); |
| 3587 | } |
| 3588 | |
| 3589 | static void sde_crtc_early_unregister(struct drm_crtc *crtc) |
| 3590 | { |
| 3591 | _sde_crtc_destroy_debugfs(crtc); |
| 3592 | } |
| 3593 | |
| 3594 | static const struct drm_crtc_funcs sde_crtc_funcs = { |
| 3595 | .set_config = drm_atomic_helper_set_config, |
| 3596 | .destroy = sde_crtc_destroy, |
| 3597 | .page_flip = drm_atomic_helper_page_flip, |
| 3598 | .set_property = sde_crtc_set_property, |
| 3599 | .atomic_set_property = sde_crtc_atomic_set_property, |
| 3600 | .atomic_get_property = sde_crtc_atomic_get_property, |
| 3601 | .reset = sde_crtc_reset, |
| 3602 | .atomic_duplicate_state = sde_crtc_duplicate_state, |
| 3603 | .atomic_destroy_state = sde_crtc_destroy_state, |
| 3604 | .late_register = sde_crtc_late_register, |
| 3605 | .early_unregister = sde_crtc_early_unregister, |
| 3606 | }; |
| 3607 | |
| 3608 | static const struct drm_crtc_helper_funcs sde_crtc_helper_funcs = { |
| 3609 | .mode_fixup = sde_crtc_mode_fixup, |
| 3610 | .disable = sde_crtc_disable, |
| 3611 | .enable = sde_crtc_enable, |
| 3612 | .atomic_check = sde_crtc_atomic_check, |
| 3613 | .atomic_begin = sde_crtc_atomic_begin, |
| 3614 | .atomic_flush = sde_crtc_atomic_flush, |
| 3615 | }; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3616 | |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3617 | static void _sde_crtc_event_cb(struct kthread_work *work) |
| 3618 | { |
| 3619 | struct sde_crtc_event *event; |
| 3620 | struct sde_crtc *sde_crtc; |
| 3621 | unsigned long irq_flags; |
| 3622 | |
| 3623 | if (!work) { |
| 3624 | SDE_ERROR("invalid work item\n"); |
| 3625 | return; |
| 3626 | } |
| 3627 | |
| 3628 | event = container_of(work, struct sde_crtc_event, kt_work); |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3629 | |
| 3630 | /* set sde_crtc to NULL for static work structures */ |
| 3631 | sde_crtc = event->sde_crtc; |
| 3632 | if (!sde_crtc) |
| 3633 | return; |
| 3634 | |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 3635 | if (event->cb_func) |
| 3636 | event->cb_func(&sde_crtc->base, event->usr); |
| 3637 | |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3638 | spin_lock_irqsave(&sde_crtc->event_lock, irq_flags); |
| 3639 | list_add_tail(&event->list, &sde_crtc->event_free_list); |
| 3640 | spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags); |
| 3641 | } |
| 3642 | |
| 3643 | int sde_crtc_event_queue(struct drm_crtc *crtc, |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 3644 | void (*func)(struct drm_crtc *crtc, void *usr), void *usr) |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3645 | { |
| 3646 | unsigned long irq_flags; |
| 3647 | struct sde_crtc *sde_crtc; |
| 3648 | struct sde_crtc_event *event = NULL; |
| 3649 | |
| 3650 | if (!crtc || !func) |
| 3651 | return -EINVAL; |
| 3652 | sde_crtc = to_sde_crtc(crtc); |
| 3653 | |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 3654 | if (!sde_crtc->event_thread) |
| 3655 | return -EINVAL; |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3656 | /* |
| 3657 | * Obtain an event struct from the private cache. This event |
| 3658 | * queue may be called from ISR contexts, so use a private |
| 3659 | * cache to avoid calling any memory allocation functions. |
| 3660 | */ |
| 3661 | spin_lock_irqsave(&sde_crtc->event_lock, irq_flags); |
| 3662 | if (!list_empty(&sde_crtc->event_free_list)) { |
| 3663 | event = list_first_entry(&sde_crtc->event_free_list, |
| 3664 | struct sde_crtc_event, list); |
| 3665 | list_del_init(&event->list); |
| 3666 | } |
| 3667 | spin_unlock_irqrestore(&sde_crtc->event_lock, irq_flags); |
| 3668 | |
| 3669 | if (!event) |
| 3670 | return -ENOMEM; |
| 3671 | |
| 3672 | /* populate event node */ |
| 3673 | event->sde_crtc = sde_crtc; |
| 3674 | event->cb_func = func; |
| 3675 | event->usr = usr; |
| 3676 | |
| 3677 | /* queue new event request */ |
| 3678 | kthread_init_work(&event->kt_work, _sde_crtc_event_cb); |
| 3679 | kthread_queue_work(&sde_crtc->event_worker, &event->kt_work); |
| 3680 | |
| 3681 | return 0; |
| 3682 | } |
| 3683 | |
| 3684 | static int _sde_crtc_init_events(struct sde_crtc *sde_crtc) |
| 3685 | { |
| 3686 | int i, rc = 0; |
| 3687 | |
| 3688 | if (!sde_crtc) { |
| 3689 | SDE_ERROR("invalid crtc\n"); |
| 3690 | return -EINVAL; |
| 3691 | } |
| 3692 | |
| 3693 | spin_lock_init(&sde_crtc->event_lock); |
| 3694 | |
| 3695 | INIT_LIST_HEAD(&sde_crtc->event_free_list); |
| 3696 | for (i = 0; i < SDE_CRTC_MAX_EVENT_COUNT; ++i) |
| 3697 | list_add_tail(&sde_crtc->event_cache[i].list, |
| 3698 | &sde_crtc->event_free_list); |
| 3699 | |
| 3700 | kthread_init_worker(&sde_crtc->event_worker); |
| 3701 | sde_crtc->event_thread = kthread_run(kthread_worker_fn, |
| 3702 | &sde_crtc->event_worker, "crtc_event:%d", |
| 3703 | sde_crtc->base.base.id); |
| 3704 | |
| 3705 | if (IS_ERR_OR_NULL(sde_crtc->event_thread)) { |
| 3706 | SDE_ERROR("failed to create event thread\n"); |
| 3707 | rc = PTR_ERR(sde_crtc->event_thread); |
| 3708 | sde_crtc->event_thread = NULL; |
| 3709 | } |
| 3710 | |
| 3711 | return rc; |
| 3712 | } |
| 3713 | |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3714 | /* initialize crtc */ |
Lloyd Atkinson | ac93364 | 2016-09-14 11:52:00 -0400 | [diff] [blame] | 3715 | struct drm_crtc *sde_crtc_init(struct drm_device *dev, struct drm_plane *plane) |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3716 | { |
| 3717 | struct drm_crtc *crtc = NULL; |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3718 | struct sde_crtc *sde_crtc = NULL; |
| 3719 | struct msm_drm_private *priv = NULL; |
| 3720 | struct sde_kms *kms = NULL; |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3721 | int i, rc; |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3722 | |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3723 | priv = dev->dev_private; |
| 3724 | kms = to_sde_kms(priv->kms); |
| 3725 | |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3726 | sde_crtc = kzalloc(sizeof(*sde_crtc), GFP_KERNEL); |
| 3727 | if (!sde_crtc) |
| 3728 | return ERR_PTR(-ENOMEM); |
| 3729 | |
| 3730 | crtc = &sde_crtc->base; |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 3731 | crtc->dev = dev; |
Alan Kwong | 07da098 | 2016-11-04 12:57:45 -0400 | [diff] [blame] | 3732 | atomic_set(&sde_crtc->vblank_refcount, 0); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3733 | |
Clarence Ip | 7f70ce4 | 2017-03-20 06:53:46 -0700 | [diff] [blame] | 3734 | mutex_init(&sde_crtc->crtc_lock); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 3735 | spin_lock_init(&sde_crtc->spin_lock); |
| 3736 | atomic_set(&sde_crtc->frame_pending, 0); |
| 3737 | |
| 3738 | INIT_LIST_HEAD(&sde_crtc->frame_event_list); |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 3739 | INIT_LIST_HEAD(&sde_crtc->user_event_list); |
Alan Kwong | 628d19e | 2016-10-31 13:50:13 -0400 | [diff] [blame] | 3740 | for (i = 0; i < ARRAY_SIZE(sde_crtc->frame_events); i++) { |
| 3741 | INIT_LIST_HEAD(&sde_crtc->frame_events[i].list); |
| 3742 | list_add(&sde_crtc->frame_events[i].list, |
| 3743 | &sde_crtc->frame_event_list); |
| 3744 | kthread_init_work(&sde_crtc->frame_events[i].work, |
| 3745 | sde_crtc_frame_event_work); |
| 3746 | } |
| 3747 | |
Dhaval Patel | 04c7e8e | 2016-09-26 20:14:31 -0700 | [diff] [blame] | 3748 | drm_crtc_init_with_planes(dev, crtc, plane, NULL, &sde_crtc_funcs, |
| 3749 | NULL); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3750 | |
| 3751 | drm_crtc_helper_add(crtc, &sde_crtc_helper_funcs); |
Abhijit Kulkarni | 3e3e0d2 | 2016-06-24 17:56:13 -0400 | [diff] [blame] | 3752 | plane->crtc = crtc; |
| 3753 | |
Clarence Ip | 8f7366c | 2016-07-05 12:15:26 -0400 | [diff] [blame] | 3754 | /* save user friendly CRTC name for later */ |
| 3755 | snprintf(sde_crtc->name, SDE_CRTC_NAME_SIZE, "crtc%u", crtc->base.id); |
| 3756 | |
Clarence Ip | a18d483 | 2017-03-13 12:35:44 -0700 | [diff] [blame] | 3757 | /* initialize event handling */ |
| 3758 | rc = _sde_crtc_init_events(sde_crtc); |
| 3759 | if (rc) { |
| 3760 | drm_crtc_cleanup(crtc); |
| 3761 | kfree(sde_crtc); |
| 3762 | return ERR_PTR(rc); |
| 3763 | } |
| 3764 | |
Clarence Ip | 9a74a44 | 2016-08-25 18:29:03 -0400 | [diff] [blame] | 3765 | /* initialize output fence support */ |
Lloyd Atkinson | 5d40d31 | 2016-09-06 08:34:13 -0400 | [diff] [blame] | 3766 | sde_fence_init(&sde_crtc->output_fence, sde_crtc->name, crtc->base.id); |
Clarence Ip | 24f8066 | 2016-06-13 19:05:32 -0400 | [diff] [blame] | 3767 | |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3768 | /* create CRTC properties */ |
| 3769 | msm_property_init(&sde_crtc->property_info, &crtc->base, dev, |
| 3770 | priv->crtc_property, sde_crtc->property_data, |
| 3771 | CRTC_PROP_COUNT, CRTC_PROP_BLOBCOUNT, |
| 3772 | sizeof(struct sde_crtc_state)); |
| 3773 | |
Dhaval Patel | e4a5dda | 2016-10-13 19:29:30 -0700 | [diff] [blame] | 3774 | sde_crtc_install_properties(crtc, kms->catalog); |
Gopikrishnaiah Anandan | 703eb90 | 2016-10-06 18:43:57 -0700 | [diff] [blame] | 3775 | |
| 3776 | /* Install color processing properties */ |
Gopikrishnaiah Anandan | e0e5e0c | 2016-05-25 11:05:33 -0700 | [diff] [blame] | 3777 | sde_cp_crtc_init(crtc); |
Gopikrishnaiah Anandan | 703eb90 | 2016-10-06 18:43:57 -0700 | [diff] [blame] | 3778 | sde_cp_crtc_install_properties(crtc); |
Clarence Ip | 7a753bb | 2016-07-07 11:47:44 -0400 | [diff] [blame] | 3779 | |
Dhaval Patel | ec10fad | 2016-08-22 14:40:48 -0700 | [diff] [blame] | 3780 | SDE_DEBUG("%s: successfully initialized crtc\n", sde_crtc->name); |
Narendra Muppalla | 1b0b335 | 2015-09-29 10:16:51 -0700 | [diff] [blame] | 3781 | return crtc; |
| 3782 | } |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 3783 | |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 3784 | static int _sde_crtc_event_enable(struct sde_kms *kms, |
| 3785 | struct drm_crtc *crtc_drm, u32 event) |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 3786 | { |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 3787 | struct sde_crtc *crtc = NULL; |
| 3788 | struct sde_crtc_irq_info *node; |
| 3789 | struct msm_drm_private *priv; |
| 3790 | unsigned long flags; |
| 3791 | bool found = false; |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 3792 | int ret, i = 0; |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 3793 | |
| 3794 | crtc = to_sde_crtc(crtc_drm); |
| 3795 | spin_lock_irqsave(&crtc->spin_lock, flags); |
| 3796 | list_for_each_entry(node, &crtc->user_event_list, list) { |
| 3797 | if (node->event == event) { |
| 3798 | found = true; |
| 3799 | break; |
| 3800 | } |
| 3801 | } |
| 3802 | spin_unlock_irqrestore(&crtc->spin_lock, flags); |
| 3803 | |
| 3804 | /* event already enabled */ |
| 3805 | if (found) |
| 3806 | return 0; |
| 3807 | |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 3808 | node = NULL; |
| 3809 | for (i = 0; i < ARRAY_SIZE(custom_events); i++) { |
| 3810 | if (custom_events[i].event == event && |
| 3811 | custom_events[i].func) { |
| 3812 | node = kzalloc(sizeof(*node), GFP_KERNEL); |
| 3813 | if (!node) |
| 3814 | return -ENOMEM; |
| 3815 | node->event = event; |
| 3816 | INIT_LIST_HEAD(&node->list); |
| 3817 | node->func = custom_events[i].func; |
| 3818 | node->event = event; |
| 3819 | break; |
| 3820 | } |
| 3821 | } |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 3822 | |
Gopikrishnaiah Anandan | b6b401f | 2017-03-14 16:39:49 -0700 | [diff] [blame] | 3823 | if (!node) { |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 3824 | SDE_ERROR("unsupported event %x\n", event); |
Gopikrishnaiah Anandan | 5154c71 | 2017-02-27 17:48:24 -0800 | [diff] [blame] | 3825 | return -EINVAL; |
| 3826 | } |
| 3827 | |
| 3828 | priv = kms->dev->dev_private; |
| 3829 | ret = 0; |
| 3830 | if (crtc_drm->enabled) { |
| 3831 | sde_power_resource_enable(&priv->phandle, kms->core_client, |
| 3832 | true); |
| 3833 | ret = node->func(crtc_drm, true, &node->irq); |
| 3834 | sde_power_resource_enable(&priv->phandle, kms->core_client, |
| 3835 | false); |
| 3836 | } |
| 3837 | |
| 3838 | if (!ret) { |
| 3839 | spin_lock_irqsave(&crtc->spin_lock, flags); |
| 3840 | list_add_tail(&node->list, &crtc->user_event_list); |
| 3841 | spin_unlock_irqrestore(&crtc->spin_lock, flags); |
| 3842 | } else { |
| 3843 | kfree(node); |
| 3844 | } |
| 3845 | |
| 3846 | return ret; |
| 3847 | } |
| 3848 | |
| 3849 | static int _sde_crtc_event_disable(struct sde_kms *kms, |
| 3850 | struct drm_crtc *crtc_drm, u32 event) |
| 3851 | { |
| 3852 | struct sde_crtc *crtc = NULL; |
| 3853 | struct sde_crtc_irq_info *node = NULL; |
| 3854 | struct msm_drm_private *priv; |
| 3855 | unsigned long flags; |
| 3856 | bool found = false; |
| 3857 | int ret; |
| 3858 | |
| 3859 | crtc = to_sde_crtc(crtc_drm); |
| 3860 | spin_lock_irqsave(&crtc->spin_lock, flags); |
| 3861 | list_for_each_entry(node, &crtc->user_event_list, list) { |
| 3862 | if (node->event == event) { |
| 3863 | list_del(&node->list); |
| 3864 | found = true; |
| 3865 | break; |
| 3866 | } |
| 3867 | } |
| 3868 | spin_unlock_irqrestore(&crtc->spin_lock, flags); |
| 3869 | |
| 3870 | /* event already disabled */ |
| 3871 | if (!found) |
| 3872 | return 0; |
| 3873 | |
| 3874 | /** |
| 3875 | * crtc is disabled interrupts are cleared remove from the list, |
| 3876 | * no need to disable/de-register. |
| 3877 | */ |
| 3878 | if (!crtc_drm->enabled) { |
| 3879 | kfree(node); |
| 3880 | return 0; |
| 3881 | } |
| 3882 | priv = kms->dev->dev_private; |
| 3883 | sde_power_resource_enable(&priv->phandle, kms->core_client, true); |
| 3884 | ret = node->func(crtc_drm, false, &node->irq); |
| 3885 | sde_power_resource_enable(&priv->phandle, kms->core_client, false); |
| 3886 | return ret; |
| 3887 | } |
| 3888 | |
| 3889 | int sde_crtc_register_custom_event(struct sde_kms *kms, |
| 3890 | struct drm_crtc *crtc_drm, u32 event, bool en) |
| 3891 | { |
| 3892 | struct sde_crtc *crtc = NULL; |
| 3893 | int ret; |
| 3894 | |
| 3895 | crtc = to_sde_crtc(crtc_drm); |
| 3896 | if (!crtc || !kms || !kms->dev) { |
| 3897 | DRM_ERROR("invalid sde_crtc %pK kms %pK dev %pK\n", crtc, |
| 3898 | kms, ((kms) ? (kms->dev) : NULL)); |
| 3899 | return -EINVAL; |
| 3900 | } |
| 3901 | |
| 3902 | if (en) |
| 3903 | ret = _sde_crtc_event_enable(kms, crtc_drm, event); |
| 3904 | else |
| 3905 | ret = _sde_crtc_event_disable(kms, crtc_drm, event); |
| 3906 | |
| 3907 | return ret; |
Gopikrishnaiah Anandan | de2c81b | 2017-03-15 12:41:29 -0700 | [diff] [blame] | 3908 | } |
Gopikrishnaiah Anandan | 84b4f67 | 2017-04-26 10:28:51 -0700 | [diff] [blame] | 3909 | |
| 3910 | static int sde_crtc_power_interrupt_handler(struct drm_crtc *crtc_drm, |
| 3911 | bool en, struct sde_irq_callback *irq) |
| 3912 | { |
| 3913 | return 0; |
| 3914 | } |