Qipeng Zha | fdca4f1 | 2015-12-11 22:45:00 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Driver for the Intel P-Unit Mailbox IPC mechanism |
| 3 | * |
| 4 | * (C) Copyright 2015 Intel Corporation |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * The heart of the P-Unit is the Foxton microcontroller and its firmware, |
| 11 | * which provide mailbox interface for power management usage. |
| 12 | */ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/acpi.h> |
| 16 | #include <linux/delay.h> |
| 17 | #include <linux/bitops.h> |
| 18 | #include <linux/device.h> |
| 19 | #include <linux/interrupt.h> |
Randy Dunlap | 2efb598 | 2018-08-15 09:12:07 -0700 | [diff] [blame] | 20 | #include <linux/io.h> |
Qipeng Zha | fdca4f1 | 2015-12-11 22:45:00 +0800 | [diff] [blame] | 21 | #include <linux/platform_device.h> |
| 22 | #include <asm/intel_punit_ipc.h> |
| 23 | |
| 24 | /* IPC Mailbox registers */ |
| 25 | #define OFFSET_DATA_LOW 0x0 |
| 26 | #define OFFSET_DATA_HIGH 0x4 |
| 27 | /* bit field of interface register */ |
| 28 | #define CMD_RUN BIT(31) |
| 29 | #define CMD_ERRCODE_MASK GENMASK(7, 0) |
| 30 | #define CMD_PARA1_SHIFT 8 |
| 31 | #define CMD_PARA2_SHIFT 16 |
| 32 | |
| 33 | #define CMD_TIMEOUT_SECONDS 1 |
| 34 | |
| 35 | enum { |
| 36 | BASE_DATA = 0, |
| 37 | BASE_IFACE, |
| 38 | BASE_MAX, |
| 39 | }; |
| 40 | |
| 41 | typedef struct { |
| 42 | struct device *dev; |
| 43 | struct mutex lock; |
| 44 | int irq; |
| 45 | struct completion cmd_complete; |
| 46 | /* base of interface and data registers */ |
| 47 | void __iomem *base[RESERVED_IPC][BASE_MAX]; |
| 48 | IPC_TYPE type; |
| 49 | } IPC_DEV; |
| 50 | |
| 51 | static IPC_DEV *punit_ipcdev; |
| 52 | |
| 53 | static inline u32 ipc_read_status(IPC_DEV *ipcdev, IPC_TYPE type) |
| 54 | { |
| 55 | return readl(ipcdev->base[type][BASE_IFACE]); |
| 56 | } |
| 57 | |
| 58 | static inline void ipc_write_cmd(IPC_DEV *ipcdev, IPC_TYPE type, u32 cmd) |
| 59 | { |
| 60 | writel(cmd, ipcdev->base[type][BASE_IFACE]); |
| 61 | } |
| 62 | |
| 63 | static inline u32 ipc_read_data_low(IPC_DEV *ipcdev, IPC_TYPE type) |
| 64 | { |
| 65 | return readl(ipcdev->base[type][BASE_DATA] + OFFSET_DATA_LOW); |
| 66 | } |
| 67 | |
| 68 | static inline u32 ipc_read_data_high(IPC_DEV *ipcdev, IPC_TYPE type) |
| 69 | { |
| 70 | return readl(ipcdev->base[type][BASE_DATA] + OFFSET_DATA_HIGH); |
| 71 | } |
| 72 | |
| 73 | static inline void ipc_write_data_low(IPC_DEV *ipcdev, IPC_TYPE type, u32 data) |
| 74 | { |
| 75 | writel(data, ipcdev->base[type][BASE_DATA] + OFFSET_DATA_LOW); |
| 76 | } |
| 77 | |
| 78 | static inline void ipc_write_data_high(IPC_DEV *ipcdev, IPC_TYPE type, u32 data) |
| 79 | { |
| 80 | writel(data, ipcdev->base[type][BASE_DATA] + OFFSET_DATA_HIGH); |
| 81 | } |
| 82 | |
| 83 | static const char *ipc_err_string(int error) |
| 84 | { |
| 85 | if (error == IPC_PUNIT_ERR_SUCCESS) |
| 86 | return "no error"; |
| 87 | else if (error == IPC_PUNIT_ERR_INVALID_CMD) |
| 88 | return "invalid command"; |
| 89 | else if (error == IPC_PUNIT_ERR_INVALID_PARAMETER) |
| 90 | return "invalid parameter"; |
| 91 | else if (error == IPC_PUNIT_ERR_CMD_TIMEOUT) |
| 92 | return "command timeout"; |
| 93 | else if (error == IPC_PUNIT_ERR_CMD_LOCKED) |
| 94 | return "command locked"; |
| 95 | else if (error == IPC_PUNIT_ERR_INVALID_VR_ID) |
| 96 | return "invalid vr id"; |
| 97 | else if (error == IPC_PUNIT_ERR_VR_ERR) |
| 98 | return "vr error"; |
| 99 | else |
| 100 | return "unknown error"; |
| 101 | } |
| 102 | |
| 103 | static int intel_punit_ipc_check_status(IPC_DEV *ipcdev, IPC_TYPE type) |
| 104 | { |
| 105 | int loops = CMD_TIMEOUT_SECONDS * USEC_PER_SEC; |
| 106 | int errcode; |
| 107 | int status; |
| 108 | |
| 109 | if (ipcdev->irq) { |
| 110 | if (!wait_for_completion_timeout(&ipcdev->cmd_complete, |
| 111 | CMD_TIMEOUT_SECONDS * HZ)) { |
| 112 | dev_err(ipcdev->dev, "IPC timed out\n"); |
| 113 | return -ETIMEDOUT; |
| 114 | } |
| 115 | } else { |
| 116 | while ((ipc_read_status(ipcdev, type) & CMD_RUN) && --loops) |
| 117 | udelay(1); |
| 118 | if (!loops) { |
| 119 | dev_err(ipcdev->dev, "IPC timed out\n"); |
| 120 | return -ETIMEDOUT; |
| 121 | } |
| 122 | } |
| 123 | |
| 124 | status = ipc_read_status(ipcdev, type); |
| 125 | errcode = status & CMD_ERRCODE_MASK; |
| 126 | if (errcode) { |
| 127 | dev_err(ipcdev->dev, "IPC failed: %s, IPC_STS=0x%x\n", |
| 128 | ipc_err_string(errcode), status); |
| 129 | return -EIO; |
| 130 | } |
| 131 | |
| 132 | return 0; |
| 133 | } |
| 134 | |
| 135 | /** |
| 136 | * intel_punit_ipc_simple_command() - Simple IPC command |
| 137 | * @cmd: IPC command code. |
| 138 | * @para1: First 8bit parameter, set 0 if not used. |
| 139 | * @para2: Second 8bit parameter, set 0 if not used. |
| 140 | * |
| 141 | * Send a IPC command to P-Unit when there is no data transaction |
| 142 | * |
| 143 | * Return: IPC error code or 0 on success. |
| 144 | */ |
| 145 | int intel_punit_ipc_simple_command(int cmd, int para1, int para2) |
| 146 | { |
| 147 | IPC_DEV *ipcdev = punit_ipcdev; |
| 148 | IPC_TYPE type; |
| 149 | u32 val; |
| 150 | int ret; |
| 151 | |
| 152 | mutex_lock(&ipcdev->lock); |
| 153 | |
| 154 | reinit_completion(&ipcdev->cmd_complete); |
| 155 | type = (cmd & IPC_PUNIT_CMD_TYPE_MASK) >> IPC_TYPE_OFFSET; |
| 156 | |
| 157 | val = cmd & ~IPC_PUNIT_CMD_TYPE_MASK; |
| 158 | val |= CMD_RUN | para2 << CMD_PARA2_SHIFT | para1 << CMD_PARA1_SHIFT; |
| 159 | ipc_write_cmd(ipcdev, type, val); |
| 160 | ret = intel_punit_ipc_check_status(ipcdev, type); |
| 161 | |
| 162 | mutex_unlock(&ipcdev->lock); |
| 163 | |
| 164 | return ret; |
| 165 | } |
| 166 | EXPORT_SYMBOL(intel_punit_ipc_simple_command); |
| 167 | |
| 168 | /** |
| 169 | * intel_punit_ipc_command() - IPC command with data and pointers |
| 170 | * @cmd: IPC command code. |
| 171 | * @para1: First 8bit parameter, set 0 if not used. |
| 172 | * @para2: Second 8bit parameter, set 0 if not used. |
| 173 | * @in: Input data, 32bit for BIOS cmd, two 32bit for GTD and ISPD. |
| 174 | * @out: Output data. |
| 175 | * |
| 176 | * Send a IPC command to P-Unit with data transaction |
| 177 | * |
| 178 | * Return: IPC error code or 0 on success. |
| 179 | */ |
| 180 | int intel_punit_ipc_command(u32 cmd, u32 para1, u32 para2, u32 *in, u32 *out) |
| 181 | { |
| 182 | IPC_DEV *ipcdev = punit_ipcdev; |
| 183 | IPC_TYPE type; |
| 184 | u32 val; |
| 185 | int ret; |
| 186 | |
| 187 | mutex_lock(&ipcdev->lock); |
| 188 | |
| 189 | reinit_completion(&ipcdev->cmd_complete); |
| 190 | type = (cmd & IPC_PUNIT_CMD_TYPE_MASK) >> IPC_TYPE_OFFSET; |
Qipeng Zha | fdca4f1 | 2015-12-11 22:45:00 +0800 | [diff] [blame] | 191 | |
Qipeng Zha | 3fae757 | 2016-01-08 18:32:27 +0800 | [diff] [blame] | 192 | if (in) { |
| 193 | ipc_write_data_low(ipcdev, type, *in); |
| 194 | if (type == GTDRIVER_IPC || type == ISPDRIVER_IPC) |
| 195 | ipc_write_data_high(ipcdev, type, *++in); |
| 196 | } |
Qipeng Zha | fdca4f1 | 2015-12-11 22:45:00 +0800 | [diff] [blame] | 197 | |
| 198 | val = cmd & ~IPC_PUNIT_CMD_TYPE_MASK; |
| 199 | val |= CMD_RUN | para2 << CMD_PARA2_SHIFT | para1 << CMD_PARA1_SHIFT; |
| 200 | ipc_write_cmd(ipcdev, type, val); |
| 201 | |
| 202 | ret = intel_punit_ipc_check_status(ipcdev, type); |
| 203 | if (ret) |
| 204 | goto out; |
Qipeng Zha | fdca4f1 | 2015-12-11 22:45:00 +0800 | [diff] [blame] | 205 | |
Qipeng Zha | 3fae757 | 2016-01-08 18:32:27 +0800 | [diff] [blame] | 206 | if (out) { |
| 207 | *out = ipc_read_data_low(ipcdev, type); |
| 208 | if (type == GTDRIVER_IPC || type == ISPDRIVER_IPC) |
| 209 | *++out = ipc_read_data_high(ipcdev, type); |
| 210 | } |
Qipeng Zha | fdca4f1 | 2015-12-11 22:45:00 +0800 | [diff] [blame] | 211 | |
| 212 | out: |
| 213 | mutex_unlock(&ipcdev->lock); |
| 214 | return ret; |
| 215 | } |
| 216 | EXPORT_SYMBOL_GPL(intel_punit_ipc_command); |
| 217 | |
| 218 | static irqreturn_t intel_punit_ioc(int irq, void *dev_id) |
| 219 | { |
| 220 | IPC_DEV *ipcdev = dev_id; |
| 221 | |
| 222 | complete(&ipcdev->cmd_complete); |
| 223 | return IRQ_HANDLED; |
| 224 | } |
| 225 | |
| 226 | static int intel_punit_get_bars(struct platform_device *pdev) |
| 227 | { |
| 228 | struct resource *res; |
| 229 | void __iomem *addr; |
| 230 | |
Aubrey Li | 5d07163 | 2016-03-31 14:28:09 -0500 | [diff] [blame] | 231 | /* |
| 232 | * The following resources are required |
| 233 | * - BIOS_IPC BASE_DATA |
| 234 | * - BIOS_IPC BASE_IFACE |
| 235 | */ |
Qipeng Zha | fdca4f1 | 2015-12-11 22:45:00 +0800 | [diff] [blame] | 236 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 237 | addr = devm_ioremap_resource(&pdev->dev, res); |
| 238 | if (IS_ERR(addr)) |
| 239 | return PTR_ERR(addr); |
| 240 | punit_ipcdev->base[BIOS_IPC][BASE_DATA] = addr; |
| 241 | |
| 242 | res = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
| 243 | addr = devm_ioremap_resource(&pdev->dev, res); |
| 244 | if (IS_ERR(addr)) |
| 245 | return PTR_ERR(addr); |
| 246 | punit_ipcdev->base[BIOS_IPC][BASE_IFACE] = addr; |
| 247 | |
Aubrey Li | 5d07163 | 2016-03-31 14:28:09 -0500 | [diff] [blame] | 248 | /* |
| 249 | * The following resources are optional |
| 250 | * - ISPDRIVER_IPC BASE_DATA |
| 251 | * - ISPDRIVER_IPC BASE_IFACE |
| 252 | * - GTDRIVER_IPC BASE_DATA |
| 253 | * - GTDRIVER_IPC BASE_IFACE |
| 254 | */ |
Qipeng Zha | fdca4f1 | 2015-12-11 22:45:00 +0800 | [diff] [blame] | 255 | res = platform_get_resource(pdev, IORESOURCE_MEM, 2); |
Kuppuswamy Sathyanarayanan | abc4b44 | 2017-10-29 02:49:54 -0700 | [diff] [blame] | 256 | if (res && resource_size(res) > 1) { |
Aubrey Li | 5d07163 | 2016-03-31 14:28:09 -0500 | [diff] [blame] | 257 | addr = devm_ioremap_resource(&pdev->dev, res); |
| 258 | if (!IS_ERR(addr)) |
| 259 | punit_ipcdev->base[ISPDRIVER_IPC][BASE_DATA] = addr; |
| 260 | } |
Qipeng Zha | fdca4f1 | 2015-12-11 22:45:00 +0800 | [diff] [blame] | 261 | |
| 262 | res = platform_get_resource(pdev, IORESOURCE_MEM, 3); |
Kuppuswamy Sathyanarayanan | abc4b44 | 2017-10-29 02:49:54 -0700 | [diff] [blame] | 263 | if (res && resource_size(res) > 1) { |
Aubrey Li | 5d07163 | 2016-03-31 14:28:09 -0500 | [diff] [blame] | 264 | addr = devm_ioremap_resource(&pdev->dev, res); |
| 265 | if (!IS_ERR(addr)) |
| 266 | punit_ipcdev->base[ISPDRIVER_IPC][BASE_IFACE] = addr; |
| 267 | } |
Qipeng Zha | fdca4f1 | 2015-12-11 22:45:00 +0800 | [diff] [blame] | 268 | |
| 269 | res = platform_get_resource(pdev, IORESOURCE_MEM, 4); |
Kuppuswamy Sathyanarayanan | abc4b44 | 2017-10-29 02:49:54 -0700 | [diff] [blame] | 270 | if (res && resource_size(res) > 1) { |
Aubrey Li | 5d07163 | 2016-03-31 14:28:09 -0500 | [diff] [blame] | 271 | addr = devm_ioremap_resource(&pdev->dev, res); |
| 272 | if (!IS_ERR(addr)) |
| 273 | punit_ipcdev->base[GTDRIVER_IPC][BASE_DATA] = addr; |
| 274 | } |
Qipeng Zha | fdca4f1 | 2015-12-11 22:45:00 +0800 | [diff] [blame] | 275 | |
| 276 | res = platform_get_resource(pdev, IORESOURCE_MEM, 5); |
Kuppuswamy Sathyanarayanan | abc4b44 | 2017-10-29 02:49:54 -0700 | [diff] [blame] | 277 | if (res && resource_size(res) > 1) { |
Aubrey Li | 5d07163 | 2016-03-31 14:28:09 -0500 | [diff] [blame] | 278 | addr = devm_ioremap_resource(&pdev->dev, res); |
| 279 | if (!IS_ERR(addr)) |
| 280 | punit_ipcdev->base[GTDRIVER_IPC][BASE_IFACE] = addr; |
| 281 | } |
Qipeng Zha | fdca4f1 | 2015-12-11 22:45:00 +0800 | [diff] [blame] | 282 | |
| 283 | return 0; |
| 284 | } |
| 285 | |
| 286 | static int intel_punit_ipc_probe(struct platform_device *pdev) |
| 287 | { |
| 288 | int irq, ret; |
| 289 | |
| 290 | punit_ipcdev = devm_kzalloc(&pdev->dev, |
| 291 | sizeof(*punit_ipcdev), GFP_KERNEL); |
| 292 | if (!punit_ipcdev) |
| 293 | return -ENOMEM; |
| 294 | |
| 295 | platform_set_drvdata(pdev, punit_ipcdev); |
| 296 | |
| 297 | irq = platform_get_irq(pdev, 0); |
| 298 | if (irq < 0) { |
| 299 | punit_ipcdev->irq = 0; |
| 300 | dev_warn(&pdev->dev, "Invalid IRQ, using polling mode\n"); |
| 301 | } else { |
| 302 | ret = devm_request_irq(&pdev->dev, irq, intel_punit_ioc, |
| 303 | IRQF_NO_SUSPEND, "intel_punit_ipc", |
| 304 | &punit_ipcdev); |
| 305 | if (ret) { |
| 306 | dev_err(&pdev->dev, "Failed to request irq: %d\n", irq); |
| 307 | return ret; |
| 308 | } |
| 309 | punit_ipcdev->irq = irq; |
| 310 | } |
| 311 | |
| 312 | ret = intel_punit_get_bars(pdev); |
| 313 | if (ret) |
| 314 | goto out; |
| 315 | |
| 316 | punit_ipcdev->dev = &pdev->dev; |
| 317 | mutex_init(&punit_ipcdev->lock); |
| 318 | init_completion(&punit_ipcdev->cmd_complete); |
| 319 | |
| 320 | out: |
| 321 | return ret; |
| 322 | } |
| 323 | |
| 324 | static int intel_punit_ipc_remove(struct platform_device *pdev) |
| 325 | { |
| 326 | return 0; |
| 327 | } |
| 328 | |
| 329 | static const struct acpi_device_id punit_ipc_acpi_ids[] = { |
| 330 | { "INT34D4", 0 }, |
| 331 | { } |
| 332 | }; |
Andy Shevchenko | 540ff21 | 2021-05-19 13:15:21 +0300 | [diff] [blame] | 333 | MODULE_DEVICE_TABLE(acpi, punit_ipc_acpi_ids); |
Qipeng Zha | fdca4f1 | 2015-12-11 22:45:00 +0800 | [diff] [blame] | 334 | |
| 335 | static struct platform_driver intel_punit_ipc_driver = { |
| 336 | .probe = intel_punit_ipc_probe, |
| 337 | .remove = intel_punit_ipc_remove, |
| 338 | .driver = { |
| 339 | .name = "intel_punit_ipc", |
| 340 | .acpi_match_table = ACPI_PTR(punit_ipc_acpi_ids), |
| 341 | }, |
| 342 | }; |
| 343 | |
| 344 | static int __init intel_punit_ipc_init(void) |
| 345 | { |
| 346 | return platform_driver_register(&intel_punit_ipc_driver); |
| 347 | } |
| 348 | |
| 349 | static void __exit intel_punit_ipc_exit(void) |
| 350 | { |
| 351 | platform_driver_unregister(&intel_punit_ipc_driver); |
| 352 | } |
| 353 | |
| 354 | MODULE_AUTHOR("Zha Qipeng <qipeng.zha@intel.com>"); |
| 355 | MODULE_DESCRIPTION("Intel P-Unit IPC driver"); |
| 356 | MODULE_LICENSE("GPL v2"); |
| 357 | |
| 358 | /* Some modules are dependent on this, so init earlier */ |
| 359 | fs_initcall(intel_punit_ipc_init); |
| 360 | module_exit(intel_punit_ipc_exit); |