Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2013 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #include "i915_drv.h" |
| 25 | #include "intel_drv.h" |
| 26 | |
| 27 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
| 28 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 29 | #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__)) |
| 30 | #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__)) |
| 31 | |
| 32 | #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) |
| 33 | #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__)) |
| 34 | |
| 35 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) |
| 36 | #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__)) |
| 37 | |
| 38 | #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__)) |
| 39 | #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__)) |
| 40 | |
| 41 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) |
| 42 | |
Paulo Zanoni | b2ec142 | 2014-02-21 13:52:25 -0300 | [diff] [blame] | 43 | static void |
| 44 | assert_device_not_suspended(struct drm_i915_private *dev_priv) |
| 45 | { |
| 46 | WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended, |
| 47 | "Device suspended\n"); |
| 48 | } |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 49 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 50 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
| 51 | { |
| 52 | u32 gt_thread_status_mask; |
| 53 | |
| 54 | if (IS_HASWELL(dev_priv->dev)) |
| 55 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; |
| 56 | else |
| 57 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; |
| 58 | |
| 59 | /* w/a for a sporadic read returning 0 by waiting for the GT |
| 60 | * thread to wake up. |
| 61 | */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 62 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 63 | DRM_ERROR("GT thread status wait timed out\n"); |
| 64 | } |
| 65 | |
| 66 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) |
| 67 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 68 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
| 69 | /* something from same cacheline, but !FORCEWAKE */ |
| 70 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 71 | } |
| 72 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 73 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, |
| 74 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 75 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 76 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0, |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 77 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 78 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
| 79 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 80 | __raw_i915_write32(dev_priv, FORCEWAKE, 1); |
| 81 | /* something from same cacheline, but !FORCEWAKE */ |
| 82 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 83 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 84 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1), |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 85 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 86 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
| 87 | |
| 88 | /* WaRsForcewakeWaitTC0:snb */ |
| 89 | __gen6_gt_wait_for_thread_c0(dev_priv); |
| 90 | } |
| 91 | |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 92 | static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 93 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 94 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 95 | /* something from same cacheline, but !FORCEWAKE_MT */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 96 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 97 | } |
| 98 | |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 99 | static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv, |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 100 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 101 | { |
| 102 | u32 forcewake_ack; |
| 103 | |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 104 | if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev)) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 105 | forcewake_ack = FORCEWAKE_ACK_HSW; |
| 106 | else |
| 107 | forcewake_ack = FORCEWAKE_MT_ACK; |
| 108 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 109 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0, |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 110 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 111 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
| 112 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 113 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
| 114 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 115 | /* something from same cacheline, but !FORCEWAKE_MT */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 116 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 117 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 118 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL), |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 119 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 120 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
| 121 | |
| 122 | /* WaRsForcewakeWaitTC0:ivb,hsw */ |
Ben Widawsky | 0f161f7 | 2013-11-02 21:07:50 -0700 | [diff] [blame] | 123 | if (INTEL_INFO(dev_priv->dev)->gen < 8) |
| 124 | __gen6_gt_wait_for_thread_c0(dev_priv); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 125 | } |
| 126 | |
| 127 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
| 128 | { |
| 129 | u32 gtfifodbg; |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 130 | |
| 131 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); |
Ville Syrjälä | 90f256b | 2013-11-14 01:59:59 +0200 | [diff] [blame] | 132 | if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) |
| 133 | __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 134 | } |
| 135 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 136 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, |
| 137 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 138 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 139 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 140 | /* something from same cacheline, but !FORCEWAKE */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 141 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 142 | gen6_gt_check_fifodbg(dev_priv); |
| 143 | } |
| 144 | |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 145 | static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv, |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 146 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 147 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 148 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
| 149 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 150 | /* something from same cacheline, but !FORCEWAKE_MT */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 151 | __raw_posting_read(dev_priv, ECOBUS); |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 152 | |
| 153 | if (IS_GEN7(dev_priv->dev)) |
| 154 | gen6_gt_check_fifodbg(dev_priv); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
| 158 | { |
| 159 | int ret = 0; |
| 160 | |
Deepak S | 5135d64 | 2013-11-29 15:56:30 +0530 | [diff] [blame] | 161 | /* On VLV, FIFO will be shared by both SW and HW. |
| 162 | * So, we need to read the FREE_ENTRIES everytime */ |
| 163 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 164 | dev_priv->uncore.fifo_count = |
| 165 | __raw_i915_read32(dev_priv, GTFIFOCTL) & |
| 166 | GT_FIFO_FREE_ENTRIES_MASK; |
| 167 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 168 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
| 169 | int loop = 500; |
Ville Syrjälä | 46520e2 | 2013-11-14 02:00:00 +0200 | [diff] [blame] | 170 | u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 171 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
| 172 | udelay(10); |
Ville Syrjälä | 46520e2 | 2013-11-14 02:00:00 +0200 | [diff] [blame] | 173 | fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 174 | } |
| 175 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
| 176 | ++ret; |
| 177 | dev_priv->uncore.fifo_count = fifo; |
| 178 | } |
| 179 | dev_priv->uncore.fifo_count--; |
| 180 | |
| 181 | return ret; |
| 182 | } |
| 183 | |
| 184 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) |
| 185 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 186 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 187 | _MASKED_BIT_DISABLE(0xffff)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 188 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 189 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 190 | } |
| 191 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 192 | static void __vlv_force_wake_get(struct drm_i915_private *dev_priv, |
| 193 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 194 | { |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 195 | /* Check for Render Engine */ |
| 196 | if (FORCEWAKE_RENDER & fw_engine) { |
| 197 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 198 | FORCEWAKE_ACK_VLV) & |
| 199 | FORCEWAKE_KERNEL) == 0, |
| 200 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 201 | DRM_ERROR("Timed out: Render forcewake old ack to clear.\n"); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 202 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 203 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 204 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 205 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 206 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 207 | FORCEWAKE_ACK_VLV) & |
| 208 | FORCEWAKE_KERNEL), |
| 209 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 210 | DRM_ERROR("Timed out: waiting for Render to ack.\n"); |
| 211 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 212 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 213 | /* Check for Media Engine */ |
| 214 | if (FORCEWAKE_MEDIA & fw_engine) { |
| 215 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 216 | FORCEWAKE_ACK_MEDIA_VLV) & |
| 217 | FORCEWAKE_KERNEL) == 0, |
| 218 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 219 | DRM_ERROR("Timed out: Media forcewake old ack to clear.\n"); |
| 220 | |
| 221 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
| 222 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 223 | |
| 224 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 225 | FORCEWAKE_ACK_MEDIA_VLV) & |
| 226 | FORCEWAKE_KERNEL), |
| 227 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 228 | DRM_ERROR("Timed out: waiting for media to ack.\n"); |
| 229 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 230 | |
| 231 | /* WaRsForcewakeWaitTC0:vlv */ |
| 232 | __gen6_gt_wait_for_thread_c0(dev_priv); |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 233 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 234 | } |
| 235 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 236 | static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, |
| 237 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 238 | { |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 239 | |
| 240 | /* Check for Render Engine */ |
| 241 | if (FORCEWAKE_RENDER & fw_engine) |
| 242 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 243 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 244 | |
| 245 | |
| 246 | /* Check for Media Engine */ |
| 247 | if (FORCEWAKE_MEDIA & fw_engine) |
| 248 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
| 249 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 250 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 251 | /* The below doubles as a POSTING_READ */ |
| 252 | gen6_gt_check_fifodbg(dev_priv); |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 253 | |
| 254 | } |
| 255 | |
| 256 | void vlv_force_wake_get(struct drm_i915_private *dev_priv, |
| 257 | int fw_engine) |
| 258 | { |
| 259 | unsigned long irqflags; |
| 260 | |
| 261 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Ville Syrjälä | 6fe7286 | 2014-02-27 22:07:21 +0200 | [diff] [blame] | 262 | |
| 263 | if (fw_engine & FORCEWAKE_RENDER && |
| 264 | dev_priv->uncore.fw_rendercount++ != 0) |
| 265 | fw_engine &= ~FORCEWAKE_RENDER; |
| 266 | if (fw_engine & FORCEWAKE_MEDIA && |
| 267 | dev_priv->uncore.fw_mediacount++ != 0) |
| 268 | fw_engine &= ~FORCEWAKE_MEDIA; |
| 269 | |
| 270 | if (fw_engine) |
| 271 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine); |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 272 | |
| 273 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 274 | } |
| 275 | |
| 276 | void vlv_force_wake_put(struct drm_i915_private *dev_priv, |
| 277 | int fw_engine) |
| 278 | { |
| 279 | unsigned long irqflags; |
| 280 | |
| 281 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 282 | |
Ville Syrjälä | 6fe7286 | 2014-02-27 22:07:21 +0200 | [diff] [blame] | 283 | if (fw_engine & FORCEWAKE_RENDER && |
| 284 | --dev_priv->uncore.fw_rendercount != 0) |
| 285 | fw_engine &= ~FORCEWAKE_RENDER; |
| 286 | if (fw_engine & FORCEWAKE_MEDIA && |
| 287 | --dev_priv->uncore.fw_mediacount != 0) |
| 288 | fw_engine &= ~FORCEWAKE_MEDIA; |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 289 | |
Ville Syrjälä | 6fe7286 | 2014-02-27 22:07:21 +0200 | [diff] [blame] | 290 | if (fw_engine) |
| 291 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine); |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 292 | |
| 293 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 294 | } |
| 295 | |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 296 | static void gen6_force_wake_timer(unsigned long arg) |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 297 | { |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 298 | struct drm_i915_private *dev_priv = (void *)arg; |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 299 | unsigned long irqflags; |
| 300 | |
Paulo Zanoni | b2ec142 | 2014-02-21 13:52:25 -0300 | [diff] [blame] | 301 | assert_device_not_suspended(dev_priv); |
| 302 | |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 303 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 304 | if (--dev_priv->uncore.forcewake_count == 0) |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 305 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 306 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Paulo Zanoni | 6d88064 | 2014-02-21 17:58:29 -0300 | [diff] [blame] | 307 | |
| 308 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 309 | } |
| 310 | |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame^] | 311 | static void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 312 | { |
| 313 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame^] | 314 | unsigned long irqflags; |
| 315 | |
| 316 | del_timer_sync(&dev_priv->uncore.force_wake_timer); |
| 317 | |
| 318 | /* Hold uncore.lock across reset to prevent any register access |
| 319 | * with forcewake not set correctly |
| 320 | */ |
| 321 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 322 | |
Mika Kuoppala | 0a089e3 | 2014-02-21 17:32:00 +0200 | [diff] [blame] | 323 | if (IS_VALLEYVIEW(dev)) |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 324 | vlv_force_wake_reset(dev_priv); |
Mika Kuoppala | 0a089e3 | 2014-02-21 17:32:00 +0200 | [diff] [blame] | 325 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 326 | __gen6_gt_force_wake_reset(dev_priv); |
Mika Kuoppala | 0a089e3 | 2014-02-21 17:32:00 +0200 | [diff] [blame] | 327 | |
| 328 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_GEN8(dev)) |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 329 | __gen7_gt_force_wake_mt_reset(dev_priv); |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame^] | 330 | |
| 331 | if (restore) { /* If reset with a user forcewake, try to restore */ |
| 332 | unsigned fw = 0; |
| 333 | |
| 334 | if (IS_VALLEYVIEW(dev)) { |
| 335 | if (dev_priv->uncore.fw_rendercount) |
| 336 | fw |= FORCEWAKE_RENDER; |
| 337 | |
| 338 | if (dev_priv->uncore.fw_mediacount) |
| 339 | fw |= FORCEWAKE_MEDIA; |
| 340 | } else { |
| 341 | if (dev_priv->uncore.forcewake_count) |
| 342 | fw = FORCEWAKE_ALL; |
| 343 | } |
| 344 | |
| 345 | if (fw) |
| 346 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); |
| 347 | |
| 348 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 349 | dev_priv->uncore.fifo_count = |
| 350 | __raw_i915_read32(dev_priv, GTFIFOCTL) & |
| 351 | GT_FIFO_FREE_ENTRIES_MASK; |
| 352 | } else { |
| 353 | dev_priv->uncore.forcewake_count = 0; |
| 354 | dev_priv->uncore.fw_rendercount = 0; |
| 355 | dev_priv->uncore.fw_mediacount = 0; |
| 356 | } |
| 357 | |
| 358 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 359 | } |
| 360 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 361 | void intel_uncore_early_sanitize(struct drm_device *dev) |
| 362 | { |
| 363 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 364 | |
| 365 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 366 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Ben Widawsky | 18ce399 | 2013-10-04 21:22:50 -0700 | [diff] [blame] | 367 | |
| 368 | if (IS_HASWELL(dev) && |
| 369 | (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) { |
| 370 | /* The docs do not explain exactly how the calculation can be |
| 371 | * made. It is somewhat guessable, but for now, it's always |
| 372 | * 128MB. |
| 373 | * NB: We can't write IDICR yet because we do not have gt funcs |
| 374 | * set up */ |
| 375 | dev_priv->ellc_size = 128; |
| 376 | DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); |
| 377 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 378 | |
Ville Syrjälä | 9705887 | 2013-12-03 11:30:09 +0200 | [diff] [blame] | 379 | /* clear out old GT FIFO errors */ |
| 380 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 381 | __raw_i915_write32(dev_priv, GTFIFODBG, |
| 382 | __raw_i915_read32(dev_priv, GTFIFODBG)); |
| 383 | |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame^] | 384 | intel_uncore_forcewake_reset(dev, false); |
Mika Kuoppala | 521198a | 2013-08-23 16:52:30 +0300 | [diff] [blame] | 385 | } |
| 386 | |
| 387 | void intel_uncore_sanitize(struct drm_device *dev) |
| 388 | { |
Chon Ming Lee | 02f4c9e | 2013-10-03 23:16:17 +0800 | [diff] [blame] | 389 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 390 | u32 reg_val; |
| 391 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 392 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
| 393 | intel_disable_gt_powersave(dev); |
Chon Ming Lee | 02f4c9e | 2013-10-03 23:16:17 +0800 | [diff] [blame] | 394 | |
| 395 | /* Turn off power gate, require especially for the BIOS less system */ |
| 396 | if (IS_VALLEYVIEW(dev)) { |
| 397 | |
| 398 | mutex_lock(&dev_priv->rps.hw_lock); |
| 399 | reg_val = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS); |
| 400 | |
Imre Deak | a30180a | 2014-03-04 19:23:02 +0200 | [diff] [blame] | 401 | if (reg_val & (PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_RENDER) | |
| 402 | PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_MEDIA) | |
| 403 | PUNIT_PWRGT_PWR_GATE(PUNIT_POWER_WELL_DISP2D))) |
Chon Ming Lee | 02f4c9e | 2013-10-03 23:16:17 +0800 | [diff] [blame] | 404 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, 0x0); |
| 405 | |
| 406 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 407 | |
| 408 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 409 | } |
| 410 | |
| 411 | /* |
| 412 | * Generally this is called implicitly by the register read function. However, |
| 413 | * if some sequence requires the GT to not power down then this function should |
| 414 | * be called at the beginning of the sequence followed by a call to |
| 415 | * gen6_gt_force_wake_put() at the end of the sequence. |
| 416 | */ |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 417 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 418 | { |
| 419 | unsigned long irqflags; |
| 420 | |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 421 | if (!dev_priv->uncore.funcs.force_wake_get) |
| 422 | return; |
| 423 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 424 | intel_runtime_pm_get(dev_priv); |
| 425 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 426 | /* Redirect to VLV specific routine */ |
| 427 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 428 | return vlv_force_wake_get(dev_priv, fw_engine); |
| 429 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 430 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 431 | if (dev_priv->uncore.forcewake_count++ == 0) |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 432 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 433 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 434 | } |
| 435 | |
| 436 | /* |
| 437 | * see gen6_gt_force_wake_get() |
| 438 | */ |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 439 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 440 | { |
| 441 | unsigned long irqflags; |
Paulo Zanoni | 6d88064 | 2014-02-21 17:58:29 -0300 | [diff] [blame] | 442 | bool delayed = false; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 443 | |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 444 | if (!dev_priv->uncore.funcs.force_wake_put) |
| 445 | return; |
| 446 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 447 | /* Redirect to VLV specific routine */ |
Paulo Zanoni | 6d88064 | 2014-02-21 17:58:29 -0300 | [diff] [blame] | 448 | if (IS_VALLEYVIEW(dev_priv->dev)) { |
| 449 | vlv_force_wake_put(dev_priv, fw_engine); |
| 450 | goto out; |
| 451 | } |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 452 | |
| 453 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 454 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 455 | if (--dev_priv->uncore.forcewake_count == 0) { |
| 456 | dev_priv->uncore.forcewake_count++; |
Paulo Zanoni | 6d88064 | 2014-02-21 17:58:29 -0300 | [diff] [blame] | 457 | delayed = true; |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 458 | mod_timer_pinned(&dev_priv->uncore.force_wake_timer, |
| 459 | jiffies + 1); |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 460 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 461 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 462 | |
Paulo Zanoni | 6d88064 | 2014-02-21 17:58:29 -0300 | [diff] [blame] | 463 | out: |
| 464 | if (!delayed) |
| 465 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 466 | } |
| 467 | |
Paulo Zanoni | e998c40 | 2014-02-21 13:52:26 -0300 | [diff] [blame] | 468 | void assert_force_wake_inactive(struct drm_i915_private *dev_priv) |
| 469 | { |
| 470 | if (!dev_priv->uncore.funcs.force_wake_get) |
| 471 | return; |
| 472 | |
| 473 | WARN_ON(dev_priv->uncore.forcewake_count > 0); |
| 474 | } |
| 475 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 476 | /* We give fast paths for the really cool registers */ |
| 477 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 478 | ((reg) < 0x40000 && (reg) != FORCEWAKE) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 479 | |
| 480 | static void |
| 481 | ilk_dummy_write(struct drm_i915_private *dev_priv) |
| 482 | { |
| 483 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up |
| 484 | * the chip from rc6 before touching it for real. MI_MODE is masked, |
| 485 | * hence harmless to write 0 into. */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 486 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 487 | } |
| 488 | |
| 489 | static void |
| 490 | hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) |
| 491 | { |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 492 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 493 | DRM_ERROR("Unknown unclaimed register before writing to %x\n", |
| 494 | reg); |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 495 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 496 | } |
| 497 | } |
| 498 | |
| 499 | static void |
| 500 | hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg) |
| 501 | { |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 502 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 503 | DRM_ERROR("Unclaimed write to %x\n", reg); |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 504 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 505 | } |
| 506 | } |
| 507 | |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 508 | #define REG_READ_HEADER(x) \ |
| 509 | unsigned long irqflags; \ |
| 510 | u##x val = 0; \ |
Paulo Zanoni | 6f0ea9e | 2014-02-21 13:52:28 -0300 | [diff] [blame] | 511 | assert_device_not_suspended(dev_priv); \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 512 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
| 513 | |
| 514 | #define REG_READ_FOOTER \ |
| 515 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
| 516 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
| 517 | return val |
| 518 | |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 519 | #define __gen4_read(x) \ |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 520 | static u##x \ |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 521 | gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 522 | REG_READ_HEADER(x); \ |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 523 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 524 | REG_READ_FOOTER; \ |
| 525 | } |
| 526 | |
| 527 | #define __gen5_read(x) \ |
| 528 | static u##x \ |
| 529 | gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 530 | REG_READ_HEADER(x); \ |
| 531 | ilk_dummy_write(dev_priv); \ |
| 532 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 533 | REG_READ_FOOTER; \ |
| 534 | } |
| 535 | |
| 536 | #define __gen6_read(x) \ |
| 537 | static u##x \ |
| 538 | gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 539 | REG_READ_HEADER(x); \ |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 540 | if (dev_priv->uncore.forcewake_count == 0 && \ |
| 541 | NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 542 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ |
| 543 | FORCEWAKE_ALL); \ |
| 544 | dev_priv->uncore.forcewake_count++; \ |
| 545 | mod_timer_pinned(&dev_priv->uncore.force_wake_timer, \ |
| 546 | jiffies + 1); \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 547 | } \ |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 548 | val = __raw_i915_read##x(dev_priv, reg); \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 549 | REG_READ_FOOTER; \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 550 | } |
| 551 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 552 | #define __vlv_read(x) \ |
| 553 | static u##x \ |
| 554 | vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 555 | unsigned fwengine = 0; \ |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 556 | REG_READ_HEADER(x); \ |
Ville Syrjälä | 6fe7286 | 2014-02-27 22:07:21 +0200 | [diff] [blame] | 557 | if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \ |
| 558 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 559 | fwengine = FORCEWAKE_RENDER; \ |
| 560 | } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \ |
| 561 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 562 | fwengine = FORCEWAKE_MEDIA; \ |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 563 | } \ |
Ville Syrjälä | 6fe7286 | 2014-02-27 22:07:21 +0200 | [diff] [blame] | 564 | if (fwengine) \ |
| 565 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ |
| 566 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 567 | if (fwengine) \ |
| 568 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 569 | REG_READ_FOOTER; \ |
| 570 | } |
| 571 | |
| 572 | |
| 573 | __vlv_read(8) |
| 574 | __vlv_read(16) |
| 575 | __vlv_read(32) |
| 576 | __vlv_read(64) |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 577 | __gen6_read(8) |
| 578 | __gen6_read(16) |
| 579 | __gen6_read(32) |
| 580 | __gen6_read(64) |
| 581 | __gen5_read(8) |
| 582 | __gen5_read(16) |
| 583 | __gen5_read(32) |
| 584 | __gen5_read(64) |
| 585 | __gen4_read(8) |
| 586 | __gen4_read(16) |
| 587 | __gen4_read(32) |
| 588 | __gen4_read(64) |
| 589 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 590 | #undef __vlv_read |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 591 | #undef __gen6_read |
| 592 | #undef __gen5_read |
| 593 | #undef __gen4_read |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 594 | #undef REG_READ_FOOTER |
| 595 | #undef REG_READ_HEADER |
| 596 | |
| 597 | #define REG_WRITE_HEADER \ |
| 598 | unsigned long irqflags; \ |
| 599 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
Paulo Zanoni | 6f0ea9e | 2014-02-21 13:52:28 -0300 | [diff] [blame] | 600 | assert_device_not_suspended(dev_priv); \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 601 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 602 | |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 603 | #define REG_WRITE_FOOTER \ |
| 604 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) |
| 605 | |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 606 | #define __gen4_write(x) \ |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 607 | static void \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 608 | gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 609 | REG_WRITE_HEADER; \ |
| 610 | __raw_i915_write##x(dev_priv, reg, val); \ |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 611 | REG_WRITE_FOOTER; \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 612 | } |
| 613 | |
| 614 | #define __gen5_write(x) \ |
| 615 | static void \ |
| 616 | gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 617 | REG_WRITE_HEADER; \ |
| 618 | ilk_dummy_write(dev_priv); \ |
| 619 | __raw_i915_write##x(dev_priv, reg, val); \ |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 620 | REG_WRITE_FOOTER; \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 621 | } |
| 622 | |
| 623 | #define __gen6_write(x) \ |
| 624 | static void \ |
| 625 | gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 626 | u32 __fifo_ret = 0; \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 627 | REG_WRITE_HEADER; \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 628 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 629 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
| 630 | } \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 631 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 632 | if (unlikely(__fifo_ret)) { \ |
| 633 | gen6_gt_check_fifodbg(dev_priv); \ |
| 634 | } \ |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 635 | REG_WRITE_FOOTER; \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 636 | } |
| 637 | |
| 638 | #define __hsw_write(x) \ |
| 639 | static void \ |
| 640 | hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 641 | u32 __fifo_ret = 0; \ |
| 642 | REG_WRITE_HEADER; \ |
| 643 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 644 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
| 645 | } \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 646 | hsw_unclaimed_reg_clear(dev_priv, reg); \ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 647 | __raw_i915_write##x(dev_priv, reg, val); \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 648 | if (unlikely(__fifo_ret)) { \ |
| 649 | gen6_gt_check_fifodbg(dev_priv); \ |
| 650 | } \ |
| 651 | hsw_unclaimed_reg_check(dev_priv, reg); \ |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 652 | REG_WRITE_FOOTER; \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 653 | } |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 654 | |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 655 | static const u32 gen8_shadowed_regs[] = { |
| 656 | FORCEWAKE_MT, |
| 657 | GEN6_RPNSWREQ, |
| 658 | GEN6_RC_VIDEO_FREQ, |
| 659 | RING_TAIL(RENDER_RING_BASE), |
| 660 | RING_TAIL(GEN6_BSD_RING_BASE), |
| 661 | RING_TAIL(VEBOX_RING_BASE), |
| 662 | RING_TAIL(BLT_RING_BASE), |
| 663 | /* TODO: Other registers are not yet used */ |
| 664 | }; |
| 665 | |
| 666 | static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg) |
| 667 | { |
| 668 | int i; |
| 669 | for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) |
| 670 | if (reg == gen8_shadowed_regs[i]) |
| 671 | return true; |
| 672 | |
| 673 | return false; |
| 674 | } |
| 675 | |
| 676 | #define __gen8_write(x) \ |
| 677 | static void \ |
| 678 | gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 679 | REG_WRITE_HEADER; \ |
Mika Kuoppala | e9dbd2b | 2014-02-18 19:10:24 +0200 | [diff] [blame] | 680 | if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \ |
| 681 | if (dev_priv->uncore.forcewake_count == 0) \ |
| 682 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ |
| 683 | FORCEWAKE_ALL); \ |
| 684 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 685 | if (dev_priv->uncore.forcewake_count == 0) \ |
| 686 | dev_priv->uncore.funcs.force_wake_put(dev_priv, \ |
| 687 | FORCEWAKE_ALL); \ |
| 688 | } else { \ |
| 689 | __raw_i915_write##x(dev_priv, reg, val); \ |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 690 | } \ |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 691 | REG_WRITE_FOOTER; \ |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 692 | } |
| 693 | |
| 694 | __gen8_write(8) |
| 695 | __gen8_write(16) |
| 696 | __gen8_write(32) |
| 697 | __gen8_write(64) |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 698 | __hsw_write(8) |
| 699 | __hsw_write(16) |
| 700 | __hsw_write(32) |
| 701 | __hsw_write(64) |
| 702 | __gen6_write(8) |
| 703 | __gen6_write(16) |
| 704 | __gen6_write(32) |
| 705 | __gen6_write(64) |
| 706 | __gen5_write(8) |
| 707 | __gen5_write(16) |
| 708 | __gen5_write(32) |
| 709 | __gen5_write(64) |
| 710 | __gen4_write(8) |
| 711 | __gen4_write(16) |
| 712 | __gen4_write(32) |
| 713 | __gen4_write(64) |
| 714 | |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 715 | #undef __gen8_write |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 716 | #undef __hsw_write |
| 717 | #undef __gen6_write |
| 718 | #undef __gen5_write |
| 719 | #undef __gen4_write |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 720 | #undef REG_WRITE_FOOTER |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 721 | #undef REG_WRITE_HEADER |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 722 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 723 | void intel_uncore_init(struct drm_device *dev) |
| 724 | { |
| 725 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 726 | |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 727 | setup_timer(&dev_priv->uncore.force_wake_timer, |
| 728 | gen6_force_wake_timer, (unsigned long)dev_priv); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 729 | |
| 730 | if (IS_VALLEYVIEW(dev)) { |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 731 | dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get; |
| 732 | dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put; |
Ben Widawsky | 43d1b64 | 2013-11-07 16:24:31 -0800 | [diff] [blame] | 733 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 734 | dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get; |
| 735 | dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put; |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 736 | } else if (IS_IVYBRIDGE(dev)) { |
| 737 | u32 ecobus; |
| 738 | |
| 739 | /* IVB configs may use multi-threaded forcewake */ |
| 740 | |
| 741 | /* A small trick here - if the bios hasn't configured |
| 742 | * MT forcewake, and if the device is in RC6, then |
| 743 | * force_wake_mt_get will not wake the device and the |
| 744 | * ECOBUS read will return zero. Which will be |
| 745 | * (correctly) interpreted by the test below as MT |
| 746 | * forcewake being disabled. |
| 747 | */ |
| 748 | mutex_lock(&dev->struct_mutex); |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 749 | __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 750 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 751 | __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 752 | mutex_unlock(&dev->struct_mutex); |
| 753 | |
| 754 | if (ecobus & FORCEWAKE_MT_ENABLE) { |
| 755 | dev_priv->uncore.funcs.force_wake_get = |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 756 | __gen7_gt_force_wake_mt_get; |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 757 | dev_priv->uncore.funcs.force_wake_put = |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 758 | __gen7_gt_force_wake_mt_put; |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 759 | } else { |
| 760 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); |
| 761 | DRM_INFO("when using vblank-synced partial screen updates.\n"); |
| 762 | dev_priv->uncore.funcs.force_wake_get = |
| 763 | __gen6_gt_force_wake_get; |
| 764 | dev_priv->uncore.funcs.force_wake_put = |
| 765 | __gen6_gt_force_wake_put; |
| 766 | } |
| 767 | } else if (IS_GEN6(dev)) { |
| 768 | dev_priv->uncore.funcs.force_wake_get = |
| 769 | __gen6_gt_force_wake_get; |
| 770 | dev_priv->uncore.funcs.force_wake_put = |
| 771 | __gen6_gt_force_wake_put; |
| 772 | } |
| 773 | |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 774 | switch (INTEL_INFO(dev)->gen) { |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 775 | default: |
| 776 | dev_priv->uncore.funcs.mmio_writeb = gen8_write8; |
| 777 | dev_priv->uncore.funcs.mmio_writew = gen8_write16; |
| 778 | dev_priv->uncore.funcs.mmio_writel = gen8_write32; |
| 779 | dev_priv->uncore.funcs.mmio_writeq = gen8_write64; |
| 780 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; |
| 781 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; |
| 782 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; |
| 783 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; |
| 784 | break; |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 785 | case 7: |
| 786 | case 6: |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 787 | if (IS_HASWELL(dev)) { |
| 788 | dev_priv->uncore.funcs.mmio_writeb = hsw_write8; |
| 789 | dev_priv->uncore.funcs.mmio_writew = hsw_write16; |
| 790 | dev_priv->uncore.funcs.mmio_writel = hsw_write32; |
| 791 | dev_priv->uncore.funcs.mmio_writeq = hsw_write64; |
| 792 | } else { |
| 793 | dev_priv->uncore.funcs.mmio_writeb = gen6_write8; |
| 794 | dev_priv->uncore.funcs.mmio_writew = gen6_write16; |
| 795 | dev_priv->uncore.funcs.mmio_writel = gen6_write32; |
| 796 | dev_priv->uncore.funcs.mmio_writeq = gen6_write64; |
| 797 | } |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 798 | |
| 799 | if (IS_VALLEYVIEW(dev)) { |
| 800 | dev_priv->uncore.funcs.mmio_readb = vlv_read8; |
| 801 | dev_priv->uncore.funcs.mmio_readw = vlv_read16; |
| 802 | dev_priv->uncore.funcs.mmio_readl = vlv_read32; |
| 803 | dev_priv->uncore.funcs.mmio_readq = vlv_read64; |
| 804 | } else { |
| 805 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; |
| 806 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; |
| 807 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; |
| 808 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; |
| 809 | } |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 810 | break; |
| 811 | case 5: |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 812 | dev_priv->uncore.funcs.mmio_writeb = gen5_write8; |
| 813 | dev_priv->uncore.funcs.mmio_writew = gen5_write16; |
| 814 | dev_priv->uncore.funcs.mmio_writel = gen5_write32; |
| 815 | dev_priv->uncore.funcs.mmio_writeq = gen5_write64; |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 816 | dev_priv->uncore.funcs.mmio_readb = gen5_read8; |
| 817 | dev_priv->uncore.funcs.mmio_readw = gen5_read16; |
| 818 | dev_priv->uncore.funcs.mmio_readl = gen5_read32; |
| 819 | dev_priv->uncore.funcs.mmio_readq = gen5_read64; |
| 820 | break; |
| 821 | case 4: |
| 822 | case 3: |
| 823 | case 2: |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 824 | dev_priv->uncore.funcs.mmio_writeb = gen4_write8; |
| 825 | dev_priv->uncore.funcs.mmio_writew = gen4_write16; |
| 826 | dev_priv->uncore.funcs.mmio_writel = gen4_write32; |
| 827 | dev_priv->uncore.funcs.mmio_writeq = gen4_write64; |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 828 | dev_priv->uncore.funcs.mmio_readb = gen4_read8; |
| 829 | dev_priv->uncore.funcs.mmio_readw = gen4_read16; |
| 830 | dev_priv->uncore.funcs.mmio_readl = gen4_read32; |
| 831 | dev_priv->uncore.funcs.mmio_readq = gen4_read64; |
| 832 | break; |
| 833 | } |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 834 | } |
| 835 | |
| 836 | void intel_uncore_fini(struct drm_device *dev) |
| 837 | { |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 838 | /* Paranoia: make sure we have disabled everything before we exit. */ |
| 839 | intel_uncore_sanitize(dev); |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame^] | 840 | intel_uncore_forcewake_reset(dev, false); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 841 | } |
| 842 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 843 | static const struct register_whitelist { |
| 844 | uint64_t offset; |
| 845 | uint32_t size; |
| 846 | uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
| 847 | } whitelist[] = { |
Kenneth Graunke | 4318101 | 2014-01-21 14:42:38 -0800 | [diff] [blame] | 848 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0x1F0 }, |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 849 | }; |
| 850 | |
| 851 | int i915_reg_read_ioctl(struct drm_device *dev, |
| 852 | void *data, struct drm_file *file) |
| 853 | { |
| 854 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 855 | struct drm_i915_reg_read *reg = data; |
| 856 | struct register_whitelist const *entry = whitelist; |
| 857 | int i; |
| 858 | |
| 859 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { |
| 860 | if (entry->offset == reg->offset && |
| 861 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) |
| 862 | break; |
| 863 | } |
| 864 | |
| 865 | if (i == ARRAY_SIZE(whitelist)) |
| 866 | return -EINVAL; |
| 867 | |
| 868 | switch (entry->size) { |
| 869 | case 8: |
| 870 | reg->val = I915_READ64(reg->offset); |
| 871 | break; |
| 872 | case 4: |
| 873 | reg->val = I915_READ(reg->offset); |
| 874 | break; |
| 875 | case 2: |
| 876 | reg->val = I915_READ16(reg->offset); |
| 877 | break; |
| 878 | case 1: |
| 879 | reg->val = I915_READ8(reg->offset); |
| 880 | break; |
| 881 | default: |
| 882 | WARN_ON(1); |
| 883 | return -EINVAL; |
| 884 | } |
| 885 | |
| 886 | return 0; |
| 887 | } |
| 888 | |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 889 | int i915_get_reset_stats_ioctl(struct drm_device *dev, |
| 890 | void *data, struct drm_file *file) |
| 891 | { |
| 892 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 893 | struct drm_i915_reset_stats *args = data; |
| 894 | struct i915_ctx_hang_stats *hs; |
Ben Widawsky | 41bde55 | 2013-12-06 14:11:21 -0800 | [diff] [blame] | 895 | struct i915_hw_context *ctx; |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 896 | int ret; |
| 897 | |
Mika Kuoppala | 661df04 | 2013-11-12 19:49:35 +0200 | [diff] [blame] | 898 | if (args->flags || args->pad) |
| 899 | return -EINVAL; |
| 900 | |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 901 | if (args->ctx_id == DEFAULT_CONTEXT_ID && !capable(CAP_SYS_ADMIN)) |
| 902 | return -EPERM; |
| 903 | |
| 904 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 905 | if (ret) |
| 906 | return ret; |
| 907 | |
Ben Widawsky | 41bde55 | 2013-12-06 14:11:21 -0800 | [diff] [blame] | 908 | ctx = i915_gem_context_get(file->driver_priv, args->ctx_id); |
| 909 | if (IS_ERR(ctx)) { |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 910 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | 41bde55 | 2013-12-06 14:11:21 -0800 | [diff] [blame] | 911 | return PTR_ERR(ctx); |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 912 | } |
Ben Widawsky | 41bde55 | 2013-12-06 14:11:21 -0800 | [diff] [blame] | 913 | hs = &ctx->hang_stats; |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 914 | |
| 915 | if (capable(CAP_SYS_ADMIN)) |
| 916 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); |
| 917 | else |
| 918 | args->reset_count = 0; |
| 919 | |
| 920 | args->batch_active = hs->batch_active; |
| 921 | args->batch_pending = hs->batch_pending; |
| 922 | |
| 923 | mutex_unlock(&dev->struct_mutex); |
| 924 | |
| 925 | return 0; |
| 926 | } |
| 927 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 928 | static int i965_reset_complete(struct drm_device *dev) |
| 929 | { |
| 930 | u8 gdrst; |
| 931 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
| 932 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
| 933 | } |
| 934 | |
| 935 | static int i965_do_reset(struct drm_device *dev) |
| 936 | { |
| 937 | int ret; |
| 938 | |
| 939 | /* |
| 940 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as |
| 941 | * well as the reset bit (GR/bit 0). Setting the GR bit |
| 942 | * triggers the reset; when done, the hardware will clear it. |
| 943 | */ |
| 944 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 945 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
| 946 | ret = wait_for(i965_reset_complete(dev), 500); |
| 947 | if (ret) |
| 948 | return ret; |
| 949 | |
| 950 | /* We can't reset render&media without also resetting display ... */ |
| 951 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 952 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
| 953 | |
| 954 | ret = wait_for(i965_reset_complete(dev), 500); |
| 955 | if (ret) |
| 956 | return ret; |
| 957 | |
| 958 | pci_write_config_byte(dev->pdev, I965_GDRST, 0); |
| 959 | |
| 960 | return 0; |
| 961 | } |
| 962 | |
| 963 | static int ironlake_do_reset(struct drm_device *dev) |
| 964 | { |
| 965 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 966 | u32 gdrst; |
| 967 | int ret; |
| 968 | |
| 969 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); |
| 970 | gdrst &= ~GRDOM_MASK; |
| 971 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
| 972 | gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
| 973 | ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
| 974 | if (ret) |
| 975 | return ret; |
| 976 | |
| 977 | /* We can't reset render&media without also resetting display ... */ |
| 978 | gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR); |
| 979 | gdrst &= ~GRDOM_MASK; |
| 980 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
| 981 | gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
| 982 | return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500); |
| 983 | } |
| 984 | |
| 985 | static int gen6_do_reset(struct drm_device *dev) |
| 986 | { |
| 987 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 988 | int ret; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 989 | |
| 990 | /* Reset the chip */ |
| 991 | |
| 992 | /* GEN6_GDRST is not in the gt power well, no need to check |
| 993 | * for fifo space for the write or forcewake the chip for |
| 994 | * the read |
| 995 | */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 996 | __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 997 | |
| 998 | /* Spin waiting for the device to ack the reset request */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 999 | ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1000 | |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame^] | 1001 | intel_uncore_forcewake_reset(dev, true); |
Mika Kuoppala | 521198a | 2013-08-23 16:52:30 +0300 | [diff] [blame] | 1002 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1003 | return ret; |
| 1004 | } |
| 1005 | |
| 1006 | int intel_gpu_reset(struct drm_device *dev) |
| 1007 | { |
| 1008 | switch (INTEL_INFO(dev)->gen) { |
Ben Widawsky | 935e8de | 2013-11-07 21:40:47 -0800 | [diff] [blame] | 1009 | case 8: |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1010 | case 7: |
| 1011 | case 6: return gen6_do_reset(dev); |
| 1012 | case 5: return ironlake_do_reset(dev); |
| 1013 | case 4: return i965_do_reset(dev); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1014 | default: return -ENODEV; |
| 1015 | } |
| 1016 | } |
| 1017 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1018 | void intel_uncore_check_errors(struct drm_device *dev) |
| 1019 | { |
| 1020 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1021 | |
| 1022 | if (HAS_FPGA_DBG_UNCLAIMED(dev) && |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 1023 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1024 | DRM_ERROR("Unclaimed register before interrupt\n"); |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 1025 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1026 | } |
| 1027 | } |