Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 1 | /* |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 2 | * Copyright (C) 2012 Ben Skeggs. |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 3 | * All Rights Reserved. |
| 4 | * |
| 5 | * Permission is hereby granted, free of charge, to any person obtaining |
| 6 | * a copy of this software and associated documentation files (the |
| 7 | * "Software"), to deal in the Software without restriction, including |
| 8 | * without limitation the rights to use, copy, modify, merge, publish, |
| 9 | * distribute, sublicense, and/or sell copies of the Software, and to |
| 10 | * permit persons to whom the Software is furnished to do so, subject to |
| 11 | * the following conditions: |
| 12 | * |
| 13 | * The above copyright notice and this permission notice (including the |
| 14 | * next paragraph) shall be included in all copies or substantial |
| 15 | * portions of the Software. |
| 16 | * |
| 17 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 18 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 19 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
| 20 | * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
| 21 | * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
| 22 | * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
| 23 | * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
| 24 | * |
| 25 | */ |
| 26 | |
| 27 | #include "drmP.h" |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 28 | #include "drm.h" |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 29 | #include "nouveau_drv.h" |
Ben Skeggs | 02a841d | 2012-07-04 23:44:54 +1000 | [diff] [blame^] | 30 | #include <engine/fifo.h> |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 31 | #include "nouveau_util.h" |
Ben Skeggs | 02a841d | 2012-07-04 23:44:54 +1000 | [diff] [blame^] | 32 | #include <core/ramht.h> |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 33 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 34 | static struct ramfc_desc { |
| 35 | unsigned bits:6; |
| 36 | unsigned ctxs:5; |
| 37 | unsigned ctxp:8; |
| 38 | unsigned regs:5; |
| 39 | unsigned regp; |
| 40 | } nv40_ramfc[] = { |
| 41 | { 32, 0, 0x00, 0, NV04_PFIFO_CACHE1_DMA_PUT }, |
| 42 | { 32, 0, 0x04, 0, NV04_PFIFO_CACHE1_DMA_GET }, |
| 43 | { 32, 0, 0x08, 0, NV10_PFIFO_CACHE1_REF_CNT }, |
| 44 | { 32, 0, 0x0c, 0, NV04_PFIFO_CACHE1_DMA_INSTANCE }, |
| 45 | { 32, 0, 0x10, 0, NV04_PFIFO_CACHE1_DMA_DCOUNT }, |
| 46 | { 32, 0, 0x14, 0, NV04_PFIFO_CACHE1_DMA_STATE }, |
| 47 | { 28, 0, 0x18, 0, NV04_PFIFO_CACHE1_DMA_FETCH }, |
| 48 | { 2, 28, 0x18, 28, 0x002058 }, |
| 49 | { 32, 0, 0x1c, 0, NV04_PFIFO_CACHE1_ENGINE }, |
| 50 | { 32, 0, 0x20, 0, NV04_PFIFO_CACHE1_PULL1 }, |
| 51 | { 32, 0, 0x24, 0, NV10_PFIFO_CACHE1_ACQUIRE_VALUE }, |
| 52 | { 32, 0, 0x28, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMESTAMP }, |
| 53 | { 32, 0, 0x2c, 0, NV10_PFIFO_CACHE1_ACQUIRE_TIMEOUT }, |
| 54 | { 32, 0, 0x30, 0, NV10_PFIFO_CACHE1_SEMAPHORE }, |
| 55 | { 32, 0, 0x34, 0, NV10_PFIFO_CACHE1_DMA_SUBROUTINE }, |
| 56 | { 32, 0, 0x38, 0, NV40_PFIFO_GRCTX_INSTANCE }, |
| 57 | { 17, 0, 0x3c, 0, NV04_PFIFO_DMA_TIMESLICE }, |
| 58 | { 32, 0, 0x40, 0, 0x0032e4 }, |
| 59 | { 32, 0, 0x44, 0, 0x0032e8 }, |
| 60 | { 32, 0, 0x4c, 0, 0x002088 }, |
| 61 | { 32, 0, 0x50, 0, 0x003300 }, |
| 62 | { 32, 0, 0x54, 0, 0x00330c }, |
| 63 | {} |
| 64 | }; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 65 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 66 | struct nv40_fifo_priv { |
| 67 | struct nouveau_fifo_priv base; |
| 68 | struct ramfc_desc *ramfc_desc; |
| 69 | }; |
| 70 | |
| 71 | struct nv40_fifo_chan { |
| 72 | struct nouveau_fifo_chan base; |
| 73 | struct nouveau_gpuobj *ramfc; |
| 74 | }; |
| 75 | |
| 76 | static int |
| 77 | nv40_fifo_context_new(struct nouveau_channel *chan, int engine) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 78 | { |
| 79 | struct drm_device *dev = chan->dev; |
| 80 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 81 | struct nv40_fifo_priv *priv = nv_engine(dev, engine); |
| 82 | struct nv40_fifo_chan *fctx; |
Maarten Maathuis | ff9e527 | 2010-02-01 20:58:27 +0100 | [diff] [blame] | 83 | unsigned long flags; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 84 | int ret; |
| 85 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 86 | fctx = chan->engctx[engine] = kzalloc(sizeof(*fctx), GFP_KERNEL); |
| 87 | if (!fctx) |
Ben Skeggs | d908175 | 2010-11-22 16:05:54 +1000 | [diff] [blame] | 88 | return -ENOMEM; |
| 89 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 90 | /* map channel control registers */ |
| 91 | chan->user = ioremap(pci_resource_start(dev->pdev, 0) + |
| 92 | NV03_USER(chan->id), PAGE_SIZE); |
| 93 | if (!chan->user) { |
| 94 | ret = -ENOMEM; |
| 95 | goto error; |
| 96 | } |
Maarten Maathuis | ff9e527 | 2010-02-01 20:58:27 +0100 | [diff] [blame] | 97 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 98 | /* initialise default fifo context */ |
| 99 | ret = nouveau_gpuobj_new_fake(dev, dev_priv->ramfc->pinst + |
| 100 | chan->id * 128, ~0, 128, |
| 101 | NVOBJ_FLAG_ZERO_ALLOC | |
| 102 | NVOBJ_FLAG_ZERO_FREE, &fctx->ramfc); |
| 103 | if (ret) |
| 104 | goto error; |
| 105 | |
| 106 | nv_wo32(fctx->ramfc, 0x00, chan->pushbuf_base); |
| 107 | nv_wo32(fctx->ramfc, 0x04, chan->pushbuf_base); |
| 108 | nv_wo32(fctx->ramfc, 0x0c, chan->pushbuf->pinst >> 4); |
| 109 | nv_wo32(fctx->ramfc, 0x18, 0x30000000 | |
| 110 | NV_PFIFO_CACHE1_DMA_FETCH_TRIG_128_BYTES | |
| 111 | NV_PFIFO_CACHE1_DMA_FETCH_SIZE_128_BYTES | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 112 | #ifdef __BIG_ENDIAN |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 113 | NV_PFIFO_CACHE1_BIG_ENDIAN | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 114 | #endif |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 115 | NV_PFIFO_CACHE1_DMA_FETCH_MAX_REQS_8); |
| 116 | nv_wo32(fctx->ramfc, 0x3c, 0x0001ffff); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 117 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 118 | /* enable dma mode on the channel */ |
| 119 | spin_lock_irqsave(&dev_priv->context_switch_lock, flags); |
| 120 | nv_mask(dev, NV04_PFIFO_MODE, (1 << chan->id), (1 << chan->id)); |
Maarten Maathuis | ff9e527 | 2010-02-01 20:58:27 +0100 | [diff] [blame] | 121 | spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 122 | |
| 123 | /*XXX: remove this later, need fifo engine context commit hook */ |
| 124 | nouveau_gpuobj_ref(fctx->ramfc, &chan->ramfc); |
| 125 | |
| 126 | error: |
| 127 | if (ret) |
| 128 | priv->base.base.context_del(chan, engine); |
| 129 | return ret; |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 130 | } |
| 131 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 132 | static int |
| 133 | nv40_fifo_init(struct drm_device *dev, int engine) |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 134 | { |
| 135 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 136 | struct nv40_fifo_priv *priv = nv_engine(dev, engine); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 137 | int i; |
| 138 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 139 | nv_mask(dev, NV03_PMC_ENABLE, NV_PMC_ENABLE_PFIFO, 0); |
| 140 | nv_mask(dev, NV03_PMC_ENABLE, NV_PMC_ENABLE_PFIFO, NV_PMC_ENABLE_PFIFO); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 141 | |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 142 | nv_wr32(dev, 0x002040, 0x000000ff); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 143 | nv_wr32(dev, 0x002044, 0x2101ffff); |
| 144 | nv_wr32(dev, 0x002058, 0x00000001); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 145 | |
| 146 | nv_wr32(dev, NV03_PFIFO_RAMHT, (0x03 << 24) /* search 128 */ | |
Ben Skeggs | e05c5a3 | 2010-09-01 15:24:35 +1000 | [diff] [blame] | 147 | ((dev_priv->ramht->bits - 9) << 16) | |
| 148 | (dev_priv->ramht->gpuobj->pinst >> 8)); |
| 149 | nv_wr32(dev, NV03_PFIFO_RAMRO, dev_priv->ramro->pinst >> 8); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 150 | |
| 151 | switch (dev_priv->chipset) { |
| 152 | case 0x47: |
| 153 | case 0x49: |
| 154 | case 0x4b: |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 155 | nv_wr32(dev, 0x002230, 0x00000001); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 156 | case 0x40: |
| 157 | case 0x41: |
| 158 | case 0x42: |
| 159 | case 0x43: |
| 160 | case 0x45: |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 161 | case 0x48: |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 162 | nv_wr32(dev, 0x002220, 0x00030002); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 163 | break; |
| 164 | default: |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 165 | nv_wr32(dev, 0x002230, 0x00000000); |
| 166 | nv_wr32(dev, 0x002220, ((dev_priv->vram_size - 512 * 1024 + |
| 167 | dev_priv->ramfc->pinst) >> 16) | |
| 168 | 0x00030000); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 169 | break; |
| 170 | } |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 171 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 172 | nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH1, priv->base.channels); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 173 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 174 | nv_wr32(dev, NV03_PFIFO_INTR_0, 0xffffffff); |
| 175 | nv_wr32(dev, NV03_PFIFO_INTR_EN_0, 0xffffffff); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 176 | |
Ben Skeggs | 67b342e | 2012-05-01 10:14:07 +1000 | [diff] [blame] | 177 | nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0, 1); |
| 178 | nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1); |
| 179 | nv_wr32(dev, NV03_PFIFO_CACHES, 1); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 180 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 181 | for (i = 0; i < priv->base.channels; i++) { |
| 182 | if (dev_priv->channels.ptr[i]) |
| 183 | nv_mask(dev, NV04_PFIFO_MODE, (1 << i), (1 << i)); |
Ben Skeggs | 6ee7386 | 2009-12-11 19:24:15 +1000 | [diff] [blame] | 184 | } |
| 185 | |
| 186 | return 0; |
| 187 | } |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 188 | |
| 189 | int |
| 190 | nv40_fifo_create(struct drm_device *dev) |
| 191 | { |
| 192 | struct drm_nouveau_private *dev_priv = dev->dev_private; |
| 193 | struct nv40_fifo_priv *priv; |
| 194 | |
| 195 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
| 196 | if (!priv) |
| 197 | return -ENOMEM; |
| 198 | |
| 199 | priv->base.base.destroy = nv04_fifo_destroy; |
| 200 | priv->base.base.init = nv40_fifo_init; |
| 201 | priv->base.base.fini = nv04_fifo_fini; |
| 202 | priv->base.base.context_new = nv40_fifo_context_new; |
| 203 | priv->base.base.context_del = nv04_fifo_context_del; |
| 204 | priv->base.channels = 31; |
| 205 | priv->ramfc_desc = nv40_ramfc; |
| 206 | dev_priv->eng[NVOBJ_ENGINE_FIFO] = &priv->base.base; |
| 207 | |
| 208 | nouveau_irq_register(dev, 8, nv04_fifo_isr); |
| 209 | return 0; |
| 210 | } |