blob: 49d36bdd512c1f94075af70aa35b202f227a3826 [file] [log] [blame]
Tim Blechmann02bec492009-03-24 12:24:35 +01001/* -*- linux-c -*- *
2 *
3 * ALSA driver for the digigram lx6464es interface
4 * adapted upstream headers
5 *
6 * Copyright (c) 2009 Tim Blechmann <tim@klingt.org>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, Inc., 59 Temple Place - Suite 330,
21 * Boston, MA 02111-1307, USA.
22 *
23 */
24
25#ifndef LX_DEFS_H
26#define LX_DEFS_H
27
28/* code adapted from ethersound.h */
29#define XES_FREQ_COUNT8_MASK 0x00001FFF /* compteur 25MHz entre 8 ech. */
30#define XES_FREQ_COUNT8_44_MIN 0x00001288 /* 25M /
31 * [ 44k - ( 44.1k + 48k ) / 2 ]
32 * * 8 */
33#define XES_FREQ_COUNT8_44_MAX 0x000010F0 /* 25M / [ ( 44.1k + 48k ) / 2 ]
34 * * 8 */
35#define XES_FREQ_COUNT8_48_MAX 0x00000F08 /* 25M /
36 * [ 48k + ( 44.1k + 48k ) / 2 ]
37 * * 8 */
38
39/* code adapted from LXES_registers.h */
40
41#define IOCR_OUTPUTS_OFFSET 0 /* (rw) offset for the number of OUTs in the
42 * ConfES register. */
43#define IOCR_INPUTS_OFFSET 8 /* (rw) offset for the number of INs in the
44 * ConfES register. */
45#define FREQ_RATIO_OFFSET 19 /* (rw) offset for frequency ratio in the
46 * ConfES register. */
47#define FREQ_RATIO_SINGLE_MODE 0x01 /* value for single mode frequency ratio:
48 * sample rate = frequency rate. */
49
50#define CONFES_READ_PART_MASK 0x00070000
51#define CONFES_WRITE_PART_MASK 0x00F80000
52
53/* code adapted from if_drv_mb.h */
54
55#define MASK_SYS_STATUS_ERROR (1L << 31) /* events that lead to a PCI irq if
56 * not yet pending */
57#define MASK_SYS_STATUS_URUN (1L << 30)
58#define MASK_SYS_STATUS_ORUN (1L << 29)
59#define MASK_SYS_STATUS_EOBO (1L << 28)
60#define MASK_SYS_STATUS_EOBI (1L << 27)
61#define MASK_SYS_STATUS_FREQ (1L << 26)
62#define MASK_SYS_STATUS_ESA (1L << 25) /* reserved, this is set by the
63 * XES */
64#define MASK_SYS_STATUS_TIMER (1L << 24)
65
66#define MASK_SYS_ASYNC_EVENTS (MASK_SYS_STATUS_ERROR | \
67 MASK_SYS_STATUS_URUN | \
68 MASK_SYS_STATUS_ORUN | \
69 MASK_SYS_STATUS_EOBO | \
70 MASK_SYS_STATUS_EOBI | \
71 MASK_SYS_STATUS_FREQ | \
72 MASK_SYS_STATUS_ESA)
73
74#define MASK_SYS_PCI_EVENTS (MASK_SYS_ASYNC_EVENTS | \
75 MASK_SYS_STATUS_TIMER)
76
77#define MASK_SYS_TIMER_COUNT 0x0000FFFF
78
79#define MASK_SYS_STATUS_EOT_PLX (1L << 22) /* event that remains
80 * internal: reserved fo end
81 * of plx dma */
82#define MASK_SYS_STATUS_XES (1L << 21) /* event that remains
83 * internal: pending XES
84 * IRQ */
85#define MASK_SYS_STATUS_CMD_DONE (1L << 20) /* alternate command
86 * management: notify driver
87 * instead of polling */
88
89
90#define MAX_STREAM_BUFFER 5 /* max amount of stream buffers. */
91
92#define MICROBLAZE_IBL_MIN 32
93#define MICROBLAZE_IBL_DEFAULT 128
94#define MICROBLAZE_IBL_MAX 512
95/* #define MASK_GRANULARITY (2*MICROBLAZE_IBL_MAX-1) */
96
97
98
99/* command opcodes, see reference for details */
100
101/*
102 the capture bit position in the object_id field in driver commands
103 depends upon the number of managed channels. For now, 64 IN + 64 OUT are
104 supported. HOwever, the communication protocol forsees 1024 channels, hence
105 bit 10 indicates a capture (input) object).
106*/
107#define ID_IS_CAPTURE (1L << 10)
108#define ID_OFFSET 13 /* object ID is at the 13th bit in the
109 * 1st command word.*/
110#define ID_CH_MASK 0x3F
111#define OPCODE_OFFSET 24 /* offset of the command opcode in the first
112 * command word.*/
113
114enum cmd_mb_opcodes {
115 CMD_00_INFO_DEBUG = 0x00,
116 CMD_01_GET_SYS_CFG = 0x01,
117 CMD_02_SET_GRANULARITY = 0x02,
118 CMD_03_SET_TIMER_IRQ = 0x03,
119 CMD_04_GET_EVENT = 0x04,
120 CMD_05_GET_PIPES = 0x05,
121
122 CMD_06_ALLOCATE_PIPE = 0x06,
123 CMD_07_RELEASE_PIPE = 0x07,
124 CMD_08_ASK_BUFFERS = 0x08,
125 CMD_09_STOP_PIPE = 0x09,
126 CMD_0A_GET_PIPE_SPL_COUNT = 0x0a,
127 CMD_0B_TOGGLE_PIPE_STATE = 0x0b,
128
129 CMD_0C_DEF_STREAM = 0x0c,
130 CMD_0D_SET_MUTE = 0x0d,
131 CMD_0E_GET_STREAM_SPL_COUNT = 0x0e,
132 CMD_0F_UPDATE_BUFFER = 0x0f,
133 CMD_10_GET_BUFFER = 0x10,
134 CMD_11_CANCEL_BUFFER = 0x11,
135 CMD_12_GET_PEAK = 0x12,
136 CMD_13_SET_STREAM_STATE = 0x13,
137 CMD_14_INVALID = 0x14,
138};
139
140/* pipe states */
141enum pipe_state_t {
142 PSTATE_IDLE = 0, /* the pipe is not processed in the XES_IRQ
143 * (free or stopped, or paused). */
144 PSTATE_RUN = 1, /* sustained play/record state. */
145 PSTATE_PURGE = 2, /* the ES channels are now off, render pipes do
146 * not DMA, record pipe do a last DMA. */
147 PSTATE_ACQUIRE = 3, /* the ES channels are now on, render pipes do
148 * not yet increase their sample count, record
149 * pipes do not DMA. */
150 PSTATE_CLOSING = 4, /* the pipe is releasing, and may not yet
151 * receive an "alloc" command. */
152};
153
154/* stream states */
155enum stream_state_t {
156 SSTATE_STOP = 0x00, /* setting to stop resets the stream spl
157 * count.*/
158 SSTATE_RUN = (0x01 << 0), /* start DMA and spl count handling. */
159 SSTATE_PAUSE = (0x01 << 1), /* pause DMA and spl count handling. */
160};
161
162/* buffer flags */
163enum buffer_flags {
164 BF_VALID = 0x80, /* set if the buffer is valid, clear if free.*/
165 BF_CURRENT = 0x40, /* set if this is the current buffer (there is
166 * always a current buffer).*/
167 BF_NOTIFY_EOB = 0x20, /* set if this buffer must cause a PCI event
168 * when finished.*/
169 BF_CIRCULAR = 0x10, /* set if buffer[1] must be copied to buffer[0]
170 * by the end of this buffer.*/
171 BF_64BITS_ADR = 0x08, /* set if the hi part of the address is valid.*/
172 BF_xx = 0x04, /* future extension.*/
173 BF_EOB = 0x02, /* set if finished, but not yet free.*/
174 BF_PAUSE = 0x01, /* pause stream at buffer end.*/
175 BF_ZERO = 0x00, /* no flags (init).*/
176};
177
178/**
179* Stream Flags definitions
180*/
181enum stream_flags {
182 SF_ZERO = 0x00000000, /* no flags (stream invalid). */
183 SF_VALID = 0x10000000, /* the stream has a valid DMA_conf
184 * info (setstreamformat). */
185 SF_XRUN = 0x20000000, /* the stream is un x-run state. */
186 SF_START = 0x40000000, /* the DMA is running.*/
187 SF_ASIO = 0x80000000, /* ASIO.*/
188};
189
190
191#define MASK_SPL_COUNT_HI 0x00FFFFFF /* 4 MSBits are status bits */
192#define PSTATE_OFFSET 28 /* 4 MSBits are status bits */
193
194
195#define MASK_STREAM_HAS_MAPPING (1L << 12)
196#define MASK_STREAM_IS_ASIO (1L << 9)
197#define STREAM_FMT_OFFSET 10 /* the stream fmt bits start at the 10th
198 * bit in the command word. */
199
200#define STREAM_FMT_16b 0x02
201#define STREAM_FMT_intel 0x01
202
203#define FREQ_FIELD_OFFSET 15 /* offset of the freq field in the response
204 * word */
205
206#define BUFF_FLAGS_OFFSET 24 /* offset of the buffer flags in the
207 * response word. */
208#define MASK_DATA_SIZE 0x00FFFFFF /* this must match the field size of
209 * datasize in the buffer_t structure. */
210
211#define MASK_BUFFER_ID 0xFF /* the cancel command awaits a buffer ID,
212 * may be 0xFF for "current". */
213
214
215/* code adapted from PcxErr_e.h */
216
217/* Bits masks */
218
219#define ERROR_MASK 0x8000
220
221#define SOURCE_MASK 0x7800
222
223#define E_SOURCE_BOARD 0x4000 /* 8 >> 1 */
224#define E_SOURCE_DRV 0x2000 /* 4 >> 1 */
225#define E_SOURCE_API 0x1000 /* 2 >> 1 */
226/* Error tools */
227#define E_SOURCE_TOOLS 0x0800 /* 1 >> 1 */
228/* Error pcxaudio */
229#define E_SOURCE_AUDIO 0x1800 /* 3 >> 1 */
230/* Error virtual pcx */
231#define E_SOURCE_VPCX 0x2800 /* 5 >> 1 */
232/* Error dispatcher */
233#define E_SOURCE_DISPATCHER 0x3000 /* 6 >> 1 */
234/* Error from CobraNet firmware */
235#define E_SOURCE_COBRANET 0x3800 /* 7 >> 1 */
236
237#define E_SOURCE_USER 0x7800
238
239#define CLASS_MASK 0x0700
240
241#define CODE_MASK 0x00FF
242
243/* Bits values */
244
245/* Values for the error/warning bit */
246#define ERROR_VALUE 0x8000
247#define WARNING_VALUE 0x0000
248
249/* Class values */
250#define E_CLASS_GENERAL 0x0000
251#define E_CLASS_INVALID_CMD 0x0100
252#define E_CLASS_INVALID_STD_OBJECT 0x0200
253#define E_CLASS_RSRC_IMPOSSIBLE 0x0300
254#define E_CLASS_WRONG_CONTEXT 0x0400
255#define E_CLASS_BAD_SPECIFIC_PARAMETER 0x0500
256#define E_CLASS_REAL_TIME_ERROR 0x0600
257#define E_CLASS_DIRECTSHOW 0x0700
258#define E_CLASS_FREE 0x0700
259
260
261/* Complete DRV error code for the general class */
262#define ED_GN (ERROR_VALUE | E_SOURCE_DRV | E_CLASS_GENERAL)
263#define ED_CONCURRENCY (ED_GN | 0x01)
264#define ED_DSP_CRASHED (ED_GN | 0x02)
265#define ED_UNKNOWN_BOARD (ED_GN | 0x03)
266#define ED_NOT_INSTALLED (ED_GN | 0x04)
267#define ED_CANNOT_OPEN_SVC_MANAGER (ED_GN | 0x05)
268#define ED_CANNOT_READ_REGISTRY (ED_GN | 0x06)
269#define ED_DSP_VERSION_MISMATCH (ED_GN | 0x07)
270#define ED_UNAVAILABLE_FEATURE (ED_GN | 0x08)
271#define ED_CANCELLED (ED_GN | 0x09)
272#define ED_NO_RESPONSE_AT_IRQA (ED_GN | 0x10)
273#define ED_INVALID_ADDRESS (ED_GN | 0x11)
274#define ED_DSP_CORRUPTED (ED_GN | 0x12)
275#define ED_PENDING_OPERATION (ED_GN | 0x13)
276#define ED_NET_ALLOCATE_MEMORY_IMPOSSIBLE (ED_GN | 0x14)
277#define ED_NET_REGISTER_ERROR (ED_GN | 0x15)
278#define ED_NET_THREAD_ERROR (ED_GN | 0x16)
279#define ED_NET_OPEN_ERROR (ED_GN | 0x17)
280#define ED_NET_CLOSE_ERROR (ED_GN | 0x18)
281#define ED_NET_NO_MORE_PACKET (ED_GN | 0x19)
282#define ED_NET_NO_MORE_BUFFER (ED_GN | 0x1A)
283#define ED_NET_SEND_ERROR (ED_GN | 0x1B)
284#define ED_NET_RECEIVE_ERROR (ED_GN | 0x1C)
285#define ED_NET_WRONG_MSG_SIZE (ED_GN | 0x1D)
286#define ED_NET_WAIT_ERROR (ED_GN | 0x1E)
287#define ED_NET_EEPROM_ERROR (ED_GN | 0x1F)
288#define ED_INVALID_RS232_COM_NUMBER (ED_GN | 0x20)
289#define ED_INVALID_RS232_INIT (ED_GN | 0x21)
290#define ED_FILE_ERROR (ED_GN | 0x22)
291#define ED_INVALID_GPIO_CMD (ED_GN | 0x23)
292#define ED_RS232_ALREADY_OPENED (ED_GN | 0x24)
293#define ED_RS232_NOT_OPENED (ED_GN | 0x25)
294#define ED_GPIO_ALREADY_OPENED (ED_GN | 0x26)
295#define ED_GPIO_NOT_OPENED (ED_GN | 0x27)
296#define ED_REGISTRY_ERROR (ED_GN | 0x28) /* <- NCX */
297#define ED_INVALID_SERVICE (ED_GN | 0x29) /* <- NCX */
298
299#define ED_READ_FILE_ALREADY_OPENED (ED_GN | 0x2a) /* <- Decalage
300 * pour RCX
301 * (old 0x28)
302 * */
303#define ED_READ_FILE_INVALID_COMMAND (ED_GN | 0x2b) /* ~ */
304#define ED_READ_FILE_INVALID_PARAMETER (ED_GN | 0x2c) /* ~ */
305#define ED_READ_FILE_ALREADY_CLOSED (ED_GN | 0x2d) /* ~ */
306#define ED_READ_FILE_NO_INFORMATION (ED_GN | 0x2e) /* ~ */
307#define ED_READ_FILE_INVALID_HANDLE (ED_GN | 0x2f) /* ~ */
308#define ED_READ_FILE_END_OF_FILE (ED_GN | 0x30) /* ~ */
309#define ED_READ_FILE_ERROR (ED_GN | 0x31) /* ~ */
310
311#define ED_DSP_CRASHED_EXC_DSPSTACK_OVERFLOW (ED_GN | 0x32) /* <- Decalage pour
312 * PCX (old 0x14) */
313#define ED_DSP_CRASHED_EXC_SYSSTACK_OVERFLOW (ED_GN | 0x33) /* ~ */
314#define ED_DSP_CRASHED_EXC_ILLEGAL (ED_GN | 0x34) /* ~ */
315#define ED_DSP_CRASHED_EXC_TIMER_REENTRY (ED_GN | 0x35) /* ~ */
316#define ED_DSP_CRASHED_EXC_FATAL_ERROR (ED_GN | 0x36) /* ~ */
317
318#define ED_FLASH_PCCARD_NOT_PRESENT (ED_GN | 0x37)
319
320#define ED_NO_CURRENT_CLOCK (ED_GN | 0x38)
321
322/* Complete DRV error code for real time class */
323#define ED_RT (ERROR_VALUE | E_SOURCE_DRV | E_CLASS_REAL_TIME_ERROR)
324#define ED_DSP_TIMED_OUT (ED_RT | 0x01)
325#define ED_DSP_CHK_TIMED_OUT (ED_RT | 0x02)
326#define ED_STREAM_OVERRUN (ED_RT | 0x03)
327#define ED_DSP_BUSY (ED_RT | 0x04)
328#define ED_DSP_SEMAPHORE_TIME_OUT (ED_RT | 0x05)
329#define ED_BOARD_TIME_OUT (ED_RT | 0x06)
330#define ED_XILINX_ERROR (ED_RT | 0x07)
331#define ED_COBRANET_ITF_NOT_RESPONDING (ED_RT | 0x08)
332
333/* Complete BOARD error code for the invaid standard object class */
334#define EB_ISO (ERROR_VALUE | E_SOURCE_BOARD | \
335 E_CLASS_INVALID_STD_OBJECT)
336#define EB_INVALID_EFFECT (EB_ISO | 0x00)
337#define EB_INVALID_PIPE (EB_ISO | 0x40)
338#define EB_INVALID_STREAM (EB_ISO | 0x80)
339#define EB_INVALID_AUDIO (EB_ISO | 0xC0)
340
341/* Complete BOARD error code for impossible resource allocation class */
342#define EB_RI (ERROR_VALUE | E_SOURCE_BOARD | E_CLASS_RSRC_IMPOSSIBLE)
343#define EB_ALLOCATE_ALL_STREAM_TRANSFERT_BUFFERS_IMPOSSIBLE (EB_RI | 0x01)
344#define EB_ALLOCATE_PIPE_SAMPLE_BUFFER_IMPOSSIBLE (EB_RI | 0x02)
345
346#define EB_ALLOCATE_MEM_STREAM_IMPOSSIBLE \
347 EB_ALLOCATE_ALL_STREAM_TRANSFERT_BUFFERS_IMPOSSIBLE
348#define EB_ALLOCATE_MEM_PIPE_IMPOSSIBLE \
349 EB_ALLOCATE_PIPE_SAMPLE_BUFFER_IMPOSSIBLE
350
351#define EB_ALLOCATE_DIFFERED_CMD_IMPOSSIBLE (EB_RI | 0x03)
352#define EB_TOO_MANY_DIFFERED_CMD (EB_RI | 0x04)
353#define EB_RBUFFERS_TABLE_OVERFLOW (EB_RI | 0x05)
354#define EB_ALLOCATE_EFFECTS_IMPOSSIBLE (EB_RI | 0x08)
355#define EB_ALLOCATE_EFFECT_POS_IMPOSSIBLE (EB_RI | 0x09)
356#define EB_RBUFFER_NOT_AVAILABLE (EB_RI | 0x0A)
357#define EB_ALLOCATE_CONTEXT_LIII_IMPOSSIBLE (EB_RI | 0x0B)
358#define EB_STATUS_DIALOG_IMPOSSIBLE (EB_RI | 0x1D)
359#define EB_CONTROL_CMD_IMPOSSIBLE (EB_RI | 0x1E)
360#define EB_STATUS_SEND_IMPOSSIBLE (EB_RI | 0x1F)
361#define EB_ALLOCATE_PIPE_IMPOSSIBLE (EB_RI | 0x40)
362#define EB_ALLOCATE_STREAM_IMPOSSIBLE (EB_RI | 0x80)
363#define EB_ALLOCATE_AUDIO_IMPOSSIBLE (EB_RI | 0xC0)
364
365/* Complete BOARD error code for wrong call context class */
366#define EB_WCC (ERROR_VALUE | E_SOURCE_BOARD | E_CLASS_WRONG_CONTEXT)
367#define EB_CMD_REFUSED (EB_WCC | 0x00)
368#define EB_START_STREAM_REFUSED (EB_WCC | 0xFC)
369#define EB_SPC_REFUSED (EB_WCC | 0xFD)
370#define EB_CSN_REFUSED (EB_WCC | 0xFE)
371#define EB_CSE_REFUSED (EB_WCC | 0xFF)
372
373
374
375
376#endif /* LX_DEFS_H */