| Maxime Hadjinlian | e38cd3a | 2013-12-24 13:53:18 +0100 | [diff] [blame] | 1 | / { |
| Andrew Lunn | 5d7fd65 | 2016-04-03 04:03:49 +0200 | [diff] [blame] | 2 | mbus@f1000000 { |
| Andrew Lunn | eb13cf8 | 2016-04-03 04:03:47 +0200 | [diff] [blame] | 3 | pciec: pcie-controller@82000000 { |
| Maxime Hadjinlian | e38cd3a | 2013-12-24 13:53:18 +0100 | [diff] [blame] | 4 | compatible = "marvell,kirkwood-pcie"; |
| 5 | status = "disabled"; |
| 6 | device_type = "pci"; |
| 7 | |
| 8 | #address-cells = <3>; |
| 9 | #size-cells = <2>; |
| 10 | |
| 11 | bus-range = <0x00 0xff>; |
| 12 | |
| 13 | ranges = |
| 14 | <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000 |
| 15 | 0x82000000 0x1 0 MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0.0 MEM */ |
| 16 | 0x81000000 0x1 0 MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0.0 IO */>; |
| 17 | |
| Sebastian Hesselbarth | 7b36efd | 2014-04-30 14:56:29 +0200 | [diff] [blame] | 18 | pcie0: pcie@1,0 { |
| Maxime Hadjinlian | e38cd3a | 2013-12-24 13:53:18 +0100 | [diff] [blame] | 19 | device_type = "pci"; |
| 20 | assigned-addresses = <0x82000800 0 0x00040000 0 0x2000>; |
| 21 | reg = <0x0800 0 0 0 0>; |
| 22 | #address-cells = <3>; |
| 23 | #size-cells = <2>; |
| 24 | #interrupt-cells = <1>; |
| 25 | ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0 |
| 26 | 0x81000000 0 0 0x81000000 0x1 0 1 0>; |
| 27 | interrupt-map-mask = <0 0 0 0>; |
| 28 | interrupt-map = <0 0 0 0 &intc 9>; |
| 29 | marvell,pcie-port = <0>; |
| 30 | marvell,pcie-lane = <0>; |
| 31 | clocks = <&gate_clk 2>; |
| 32 | status = "disabled"; |
| 33 | }; |
| 34 | }; |
| 35 | }; |
| 36 | |
| 37 | ocp@f1000000 { |
| Sebastian Hesselbarth | a948396 | 2014-04-30 14:56:32 +0200 | [diff] [blame] | 38 | pinctrl: pin-controller@10000 { |
| Maxime Hadjinlian | e38cd3a | 2013-12-24 13:53:18 +0100 | [diff] [blame] | 39 | compatible = "marvell,88f6192-pinctrl"; |
| Maxime Hadjinlian | e38cd3a | 2013-12-24 13:53:18 +0100 | [diff] [blame] | 40 | |
| Maxime Hadjinlian | e38cd3a | 2013-12-24 13:53:18 +0100 | [diff] [blame] | 41 | pmx_sata0: pmx-sata0 { |
| 42 | marvell,pins = "mpp5", "mpp21", "mpp23"; |
| 43 | marvell,function = "sata0"; |
| 44 | }; |
| 45 | pmx_sata1: pmx-sata1 { |
| 46 | marvell,pins = "mpp4", "mpp20", "mpp22"; |
| 47 | marvell,function = "sata1"; |
| 48 | }; |
| Maxime Hadjinlian | e38cd3a | 2013-12-24 13:53:18 +0100 | [diff] [blame] | 49 | pmx_sdio: pmx-sdio { |
| 50 | marvell,pins = "mpp12", "mpp13", "mpp14", |
| 51 | "mpp15", "mpp16", "mpp17"; |
| 52 | marvell,function = "sdio"; |
| 53 | }; |
| 54 | }; |
| 55 | |
| Sebastian Hesselbarth | 7b36efd | 2014-04-30 14:56:29 +0200 | [diff] [blame] | 56 | rtc: rtc@10300 { |
| Maxime Hadjinlian | e38cd3a | 2013-12-24 13:53:18 +0100 | [diff] [blame] | 57 | compatible = "marvell,kirkwood-rtc", "marvell,orion-rtc"; |
| 58 | reg = <0x10300 0x20>; |
| 59 | interrupts = <53>; |
| 60 | clocks = <&gate_clk 7>; |
| 61 | }; |
| 62 | |
| Sebastian Hesselbarth | 7b36efd | 2014-04-30 14:56:29 +0200 | [diff] [blame] | 63 | sata: sata@80000 { |
| Maxime Hadjinlian | e38cd3a | 2013-12-24 13:53:18 +0100 | [diff] [blame] | 64 | compatible = "marvell,orion-sata"; |
| 65 | reg = <0x80000 0x5000>; |
| 66 | interrupts = <21>; |
| 67 | clocks = <&gate_clk 14>, <&gate_clk 15>; |
| 68 | clock-names = "0", "1"; |
| Evgeni Dobrev | 9c569b3 | 2014-12-16 19:22:18 +0100 | [diff] [blame] | 69 | phys = <&sata_phy0>, <&sata_phy1>; |
| 70 | phy-names = "port0", "port1"; |
| Maxime Hadjinlian | e38cd3a | 2013-12-24 13:53:18 +0100 | [diff] [blame] | 71 | status = "disabled"; |
| 72 | }; |
| 73 | |
| Sebastian Hesselbarth | 7b36efd | 2014-04-30 14:56:29 +0200 | [diff] [blame] | 74 | sdio: mvsdio@90000 { |
| Maxime Hadjinlian | e38cd3a | 2013-12-24 13:53:18 +0100 | [diff] [blame] | 75 | compatible = "marvell,orion-sdio"; |
| 76 | reg = <0x90000 0x200>; |
| 77 | interrupts = <28>; |
| 78 | clocks = <&gate_clk 4>; |
| 79 | bus-width = <4>; |
| 80 | cap-sdio-irq; |
| 81 | cap-sd-highspeed; |
| 82 | cap-mmc-highspeed; |
| 83 | status = "disabled"; |
| 84 | }; |
| 85 | }; |
| 86 | }; |