Sudeep Holla | e6d7f6d | 2015-12-22 17:45:29 +0000 | [diff] [blame] | 1 | /* |
| 2 | * ARM Ltd. Juno Platform |
| 3 | * |
| 4 | * Copyright (c) 2015 ARM Ltd. |
| 5 | * |
| 6 | * This file is licensed under a dual GPLv2 or BSD license. |
| 7 | */ |
| 8 | |
| 9 | /dts-v1/; |
| 10 | |
| 11 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 12 | |
| 13 | / { |
| 14 | model = "ARM Juno development board (r2)"; |
| 15 | compatible = "arm,juno-r2", "arm,juno", "arm,vexpress"; |
| 16 | interrupt-parent = <&gic>; |
| 17 | #address-cells = <2>; |
| 18 | #size-cells = <2>; |
| 19 | |
| 20 | aliases { |
| 21 | serial0 = &soc_uart0; |
| 22 | }; |
| 23 | |
| 24 | chosen { |
| 25 | stdout-path = "serial0:115200n8"; |
| 26 | }; |
| 27 | |
| 28 | psci { |
| 29 | compatible = "arm,psci-0.2"; |
| 30 | method = "smc"; |
| 31 | }; |
| 32 | |
| 33 | cpus { |
| 34 | #address-cells = <2>; |
| 35 | #size-cells = <0>; |
| 36 | |
| 37 | cpu-map { |
| 38 | cluster0 { |
| 39 | core0 { |
| 40 | cpu = <&A72_0>; |
| 41 | }; |
| 42 | core1 { |
| 43 | cpu = <&A72_1>; |
| 44 | }; |
| 45 | }; |
| 46 | |
| 47 | cluster1 { |
| 48 | core0 { |
| 49 | cpu = <&A53_0>; |
| 50 | }; |
| 51 | core1 { |
| 52 | cpu = <&A53_1>; |
| 53 | }; |
| 54 | core2 { |
| 55 | cpu = <&A53_2>; |
| 56 | }; |
| 57 | core3 { |
| 58 | cpu = <&A53_3>; |
| 59 | }; |
| 60 | }; |
| 61 | }; |
| 62 | |
| 63 | idle-states { |
| 64 | entry-method = "arm,psci"; |
| 65 | |
| 66 | CPU_SLEEP_0: cpu-sleep-0 { |
| 67 | compatible = "arm,idle-state"; |
| 68 | arm,psci-suspend-param = <0x0010000>; |
| 69 | local-timer-stop; |
| 70 | entry-latency-us = <300>; |
| 71 | exit-latency-us = <1200>; |
| 72 | min-residency-us = <2000>; |
| 73 | }; |
| 74 | |
| 75 | CLUSTER_SLEEP_0: cluster-sleep-0 { |
| 76 | compatible = "arm,idle-state"; |
| 77 | arm,psci-suspend-param = <0x1010000>; |
| 78 | local-timer-stop; |
Sudeep Holla | 909e481 | 2016-11-16 17:31:31 +0000 | [diff] [blame] | 79 | entry-latency-us = <400>; |
Sudeep Holla | e6d7f6d | 2015-12-22 17:45:29 +0000 | [diff] [blame] | 80 | exit-latency-us = <1200>; |
| 81 | min-residency-us = <2500>; |
| 82 | }; |
| 83 | }; |
| 84 | |
| 85 | A72_0: cpu@0 { |
| 86 | compatible = "arm,cortex-a72","arm,armv8"; |
| 87 | reg = <0x0 0x0>; |
| 88 | device_type = "cpu"; |
| 89 | enable-method = "psci"; |
| 90 | next-level-cache = <&A72_L2>; |
| 91 | clocks = <&scpi_dvfs 0>; |
| 92 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
| 93 | }; |
| 94 | |
| 95 | A72_1: cpu@1 { |
| 96 | compatible = "arm,cortex-a72","arm,armv8"; |
| 97 | reg = <0x0 0x1>; |
| 98 | device_type = "cpu"; |
| 99 | enable-method = "psci"; |
| 100 | next-level-cache = <&A72_L2>; |
| 101 | clocks = <&scpi_dvfs 0>; |
| 102 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
| 103 | }; |
| 104 | |
| 105 | A53_0: cpu@100 { |
| 106 | compatible = "arm,cortex-a53","arm,armv8"; |
| 107 | reg = <0x0 0x100>; |
| 108 | device_type = "cpu"; |
| 109 | enable-method = "psci"; |
| 110 | next-level-cache = <&A53_L2>; |
| 111 | clocks = <&scpi_dvfs 1>; |
| 112 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
| 113 | }; |
| 114 | |
| 115 | A53_1: cpu@101 { |
| 116 | compatible = "arm,cortex-a53","arm,armv8"; |
| 117 | reg = <0x0 0x101>; |
| 118 | device_type = "cpu"; |
| 119 | enable-method = "psci"; |
| 120 | next-level-cache = <&A53_L2>; |
| 121 | clocks = <&scpi_dvfs 1>; |
| 122 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
| 123 | }; |
| 124 | |
| 125 | A53_2: cpu@102 { |
| 126 | compatible = "arm,cortex-a53","arm,armv8"; |
| 127 | reg = <0x0 0x102>; |
| 128 | device_type = "cpu"; |
| 129 | enable-method = "psci"; |
| 130 | next-level-cache = <&A53_L2>; |
| 131 | clocks = <&scpi_dvfs 1>; |
| 132 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
| 133 | }; |
| 134 | |
| 135 | A53_3: cpu@103 { |
| 136 | compatible = "arm,cortex-a53","arm,armv8"; |
| 137 | reg = <0x0 0x103>; |
| 138 | device_type = "cpu"; |
| 139 | enable-method = "psci"; |
| 140 | next-level-cache = <&A53_L2>; |
| 141 | clocks = <&scpi_dvfs 1>; |
| 142 | cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; |
| 143 | }; |
| 144 | |
| 145 | A72_L2: l2-cache0 { |
| 146 | compatible = "cache"; |
| 147 | }; |
| 148 | |
| 149 | A53_L2: l2-cache1 { |
| 150 | compatible = "cache"; |
| 151 | }; |
| 152 | }; |
| 153 | |
| 154 | pmu_a72 { |
| 155 | compatible = "arm,cortex-a72-pmu"; |
| 156 | interrupts = <GIC_SPI 02 IRQ_TYPE_LEVEL_HIGH>, |
| 157 | <GIC_SPI 06 IRQ_TYPE_LEVEL_HIGH>; |
| 158 | interrupt-affinity = <&A72_0>, |
| 159 | <&A72_1>; |
| 160 | }; |
| 161 | |
| 162 | pmu_a53 { |
| 163 | compatible = "arm,cortex-a53-pmu"; |
| 164 | interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>, |
| 165 | <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>, |
| 166 | <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>, |
| 167 | <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| 168 | interrupt-affinity = <&A53_0>, |
| 169 | <&A53_1>, |
| 170 | <&A53_2>, |
| 171 | <&A53_3>; |
| 172 | }; |
| 173 | |
| 174 | #include "juno-base.dtsi" |
| 175 | }; |
| 176 | |
| 177 | &memtimer { |
| 178 | status = "okay"; |
| 179 | }; |
| 180 | |
| 181 | &pcie_ctlr { |
| 182 | status = "okay"; |
| 183 | }; |
Sudeep Holla | 3e287cf | 2016-06-02 10:18:41 +0100 | [diff] [blame] | 184 | |
| 185 | &etm0 { |
| 186 | cpu = <&A72_0>; |
| 187 | }; |
| 188 | |
| 189 | &etm1 { |
| 190 | cpu = <&A72_1>; |
| 191 | }; |
| 192 | |
| 193 | &etm2 { |
| 194 | cpu = <&A53_0>; |
| 195 | }; |
| 196 | |
| 197 | &etm3 { |
| 198 | cpu = <&A53_1>; |
| 199 | }; |
| 200 | |
| 201 | &etm4 { |
| 202 | cpu = <&A53_2>; |
| 203 | }; |
| 204 | |
| 205 | &etm5 { |
| 206 | cpu = <&A53_3>; |
| 207 | }; |
Javi Merino | f7b636a | 2016-06-13 16:15:15 +0100 | [diff] [blame] | 208 | |
| 209 | &big_cluster_thermal_zone { |
| 210 | status = "okay"; |
| 211 | }; |
| 212 | |
| 213 | &little_cluster_thermal_zone { |
| 214 | status = "okay"; |
| 215 | }; |
| 216 | |
| 217 | &gpu0_thermal_zone { |
| 218 | status = "okay"; |
| 219 | }; |
| 220 | |
| 221 | &gpu1_thermal_zone { |
| 222 | status = "okay"; |
| 223 | }; |