blob: e3c373082bbee355c736d6f784717f02277df2ca [file] [log] [blame]
Tomasz Figad710aa32014-03-18 07:28:27 +09001/*
2 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
3 * http://www.samsung.com
4 *
5 * Exynos low-level resume code
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/linkage.h>
Tomasz Figa2b9d9c32014-09-24 01:24:39 +090019#include "smc.h"
Tomasz Figad710aa32014-03-18 07:28:27 +090020
21#define CPU_MASK 0xff0ffff0
22#define CPU_CORTEX_A9 0x410fc090
23
24 /*
25 * The following code is located into the .data section. This is to
26 * allow l2x0_regs_phys to be accessed with a relative load while we
27 * can't rely on any MMU translation. We could have put l2x0_regs_phys
28 * in the .text section as well, but some setups might insist on it to
29 * be truly read-only. (Reference from: arch/arm/kernel/sleep.S)
30 */
31 .data
32 .align
33
34 /*
35 * sleep magic, to allow the bootloader to check for an valid
36 * image to resume to. Must be the first word before the
37 * exynos_cpu_resume entry.
38 */
39
40 .word 0x2bedf00d
41
42 /*
43 * exynos_cpu_resume
44 *
45 * resume code entry for bootloader to call
46 */
47
48ENTRY(exynos_cpu_resume)
49#ifdef CONFIG_CACHE_L2X0
50 mrc p15, 0, r0, c0, c0, 0
51 ldr r1, =CPU_MASK
52 and r0, r0, r1
53 ldr r1, =CPU_CORTEX_A9
54 cmp r0, r1
Russell King25a9ef62014-04-05 11:45:34 +010055 bleq l2c310_early_resume
Tomasz Figad710aa32014-03-18 07:28:27 +090056#endif
57 b cpu_resume
58ENDPROC(exynos_cpu_resume)
Tomasz Figa2b9d9c32014-09-24 01:24:39 +090059
60 .align
61
62ENTRY(exynos_cpu_resume_ns)
63 mrc p15, 0, r0, c0, c0, 0
64 ldr r1, =CPU_MASK
65 and r0, r0, r1
66 ldr r1, =CPU_CORTEX_A9
67 cmp r0, r1
68 bne skip_cp15
69
70 adr r0, cp15_save_power
71 ldr r1, [r0]
72 adr r0, cp15_save_diag
73 ldr r2, [r0]
74 mov r0, #SMC_CMD_C15RESUME
75 dsb
76 smc #0
77skip_cp15:
78 b cpu_resume
79ENDPROC(exynos_cpu_resume_ns)
80 .globl cp15_save_diag
81cp15_save_diag:
82 .long 0 @ cp15 diagnostic
83 .globl cp15_save_power
84cp15_save_power:
85 .long 0 @ cp15 power control