Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 1 | /* linux/arch/arm/mach-exynos4/mct.c |
| 2 | * |
| 3 | * Copyright (c) 2011 Samsung Electronics Co., Ltd. |
| 4 | * http://www.samsung.com |
| 5 | * |
| 6 | * EXYNOS4 MCT(Multi-Core Timer) support |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | */ |
| 12 | |
| 13 | #include <linux/sched.h> |
| 14 | #include <linux/interrupt.h> |
| 15 | #include <linux/irq.h> |
| 16 | #include <linux/err.h> |
| 17 | #include <linux/clk.h> |
| 18 | #include <linux/clockchips.h> |
| 19 | #include <linux/platform_device.h> |
| 20 | #include <linux/delay.h> |
| 21 | #include <linux/percpu.h> |
Kukjin Kim | 2edb36c | 2012-11-15 15:48:56 +0900 | [diff] [blame] | 22 | #include <linux/of.h> |
Thomas Abraham | 36ba5d5 | 2013-03-09 16:01:52 +0900 | [diff] [blame] | 23 | #include <linux/of_irq.h> |
| 24 | #include <linux/of_address.h> |
Thomas Abraham | 9fbf0c8 | 2013-03-09 16:10:03 +0900 | [diff] [blame] | 25 | #include <linux/clocksource.h> |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 26 | |
Kukjin Kim | 2edb36c | 2012-11-15 15:48:56 +0900 | [diff] [blame] | 27 | #include <asm/arch_timer.h> |
Marc Zyngier | a8cb604 | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 28 | #include <asm/localtimer.h> |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 29 | #include <asm/mach/time.h> |
| 30 | |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 31 | #define EXYNOS4_MCTREG(x) (x) |
| 32 | #define EXYNOS4_MCT_G_CNT_L EXYNOS4_MCTREG(0x100) |
| 33 | #define EXYNOS4_MCT_G_CNT_U EXYNOS4_MCTREG(0x104) |
| 34 | #define EXYNOS4_MCT_G_CNT_WSTAT EXYNOS4_MCTREG(0x110) |
| 35 | #define EXYNOS4_MCT_G_COMP0_L EXYNOS4_MCTREG(0x200) |
| 36 | #define EXYNOS4_MCT_G_COMP0_U EXYNOS4_MCTREG(0x204) |
| 37 | #define EXYNOS4_MCT_G_COMP0_ADD_INCR EXYNOS4_MCTREG(0x208) |
| 38 | #define EXYNOS4_MCT_G_TCON EXYNOS4_MCTREG(0x240) |
| 39 | #define EXYNOS4_MCT_G_INT_CSTAT EXYNOS4_MCTREG(0x244) |
| 40 | #define EXYNOS4_MCT_G_INT_ENB EXYNOS4_MCTREG(0x248) |
| 41 | #define EXYNOS4_MCT_G_WSTAT EXYNOS4_MCTREG(0x24C) |
| 42 | #define _EXYNOS4_MCT_L_BASE EXYNOS4_MCTREG(0x300) |
| 43 | #define EXYNOS4_MCT_L_BASE(x) (_EXYNOS4_MCT_L_BASE + (0x100 * x)) |
| 44 | #define EXYNOS4_MCT_L_MASK (0xffffff00) |
| 45 | |
| 46 | #define MCT_L_TCNTB_OFFSET (0x00) |
| 47 | #define MCT_L_ICNTB_OFFSET (0x08) |
| 48 | #define MCT_L_TCON_OFFSET (0x20) |
| 49 | #define MCT_L_INT_CSTAT_OFFSET (0x30) |
| 50 | #define MCT_L_INT_ENB_OFFSET (0x34) |
| 51 | #define MCT_L_WSTAT_OFFSET (0x40) |
| 52 | #define MCT_G_TCON_START (1 << 8) |
| 53 | #define MCT_G_TCON_COMP0_AUTO_INC (1 << 1) |
| 54 | #define MCT_G_TCON_COMP0_ENABLE (1 << 0) |
| 55 | #define MCT_L_TCON_INTERVAL_MODE (1 << 2) |
| 56 | #define MCT_L_TCON_INT_START (1 << 1) |
| 57 | #define MCT_L_TCON_TIMER_START (1 << 0) |
| 58 | |
Changhwan Youn | 4d2e4d7 | 2012-03-09 15:09:21 -0800 | [diff] [blame] | 59 | #define TICK_BASE_CNT 1 |
| 60 | |
Changhwan Youn | 3a06228 | 2011-10-04 17:02:58 +0900 | [diff] [blame] | 61 | enum { |
| 62 | MCT_INT_SPI, |
| 63 | MCT_INT_PPI |
| 64 | }; |
| 65 | |
Thomas Abraham | c371dc6 | 2013-03-09 16:01:50 +0900 | [diff] [blame] | 66 | enum { |
| 67 | MCT_G0_IRQ, |
| 68 | MCT_G1_IRQ, |
| 69 | MCT_G2_IRQ, |
| 70 | MCT_G3_IRQ, |
| 71 | MCT_L0_IRQ, |
| 72 | MCT_L1_IRQ, |
| 73 | MCT_L2_IRQ, |
| 74 | MCT_L3_IRQ, |
| 75 | MCT_NR_IRQS, |
| 76 | }; |
| 77 | |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 78 | static void __iomem *reg_base; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 79 | static unsigned long clk_rate; |
Changhwan Youn | 3a06228 | 2011-10-04 17:02:58 +0900 | [diff] [blame] | 80 | static unsigned int mct_int_type; |
Thomas Abraham | c371dc6 | 2013-03-09 16:01:50 +0900 | [diff] [blame] | 81 | static int mct_irqs[MCT_NR_IRQS]; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 82 | |
| 83 | struct mct_clock_event_device { |
| 84 | struct clock_event_device *evt; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 85 | unsigned long base; |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 86 | char name[10]; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 87 | }; |
| 88 | |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 89 | static void exynos4_mct_write(unsigned int value, unsigned long offset) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 90 | { |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 91 | unsigned long stat_addr; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 92 | u32 mask; |
| 93 | u32 i; |
| 94 | |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 95 | __raw_writel(value, reg_base + offset); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 96 | |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 97 | if (likely(offset >= EXYNOS4_MCT_L_BASE(0))) { |
| 98 | stat_addr = (offset & ~EXYNOS4_MCT_L_MASK) + MCT_L_WSTAT_OFFSET; |
| 99 | switch (offset & EXYNOS4_MCT_L_MASK) { |
| 100 | case MCT_L_TCON_OFFSET: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 101 | mask = 1 << 3; /* L_TCON write status */ |
| 102 | break; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 103 | case MCT_L_ICNTB_OFFSET: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 104 | mask = 1 << 1; /* L_ICNTB write status */ |
| 105 | break; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 106 | case MCT_L_TCNTB_OFFSET: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 107 | mask = 1 << 0; /* L_TCNTB write status */ |
| 108 | break; |
| 109 | default: |
| 110 | return; |
| 111 | } |
| 112 | } else { |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 113 | switch (offset) { |
| 114 | case EXYNOS4_MCT_G_TCON: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 115 | stat_addr = EXYNOS4_MCT_G_WSTAT; |
| 116 | mask = 1 << 16; /* G_TCON write status */ |
| 117 | break; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 118 | case EXYNOS4_MCT_G_COMP0_L: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 119 | stat_addr = EXYNOS4_MCT_G_WSTAT; |
| 120 | mask = 1 << 0; /* G_COMP0_L write status */ |
| 121 | break; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 122 | case EXYNOS4_MCT_G_COMP0_U: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 123 | stat_addr = EXYNOS4_MCT_G_WSTAT; |
| 124 | mask = 1 << 1; /* G_COMP0_U write status */ |
| 125 | break; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 126 | case EXYNOS4_MCT_G_COMP0_ADD_INCR: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 127 | stat_addr = EXYNOS4_MCT_G_WSTAT; |
| 128 | mask = 1 << 2; /* G_COMP0_ADD_INCR w status */ |
| 129 | break; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 130 | case EXYNOS4_MCT_G_CNT_L: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 131 | stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; |
| 132 | mask = 1 << 0; /* G_CNT_L write status */ |
| 133 | break; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 134 | case EXYNOS4_MCT_G_CNT_U: |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 135 | stat_addr = EXYNOS4_MCT_G_CNT_WSTAT; |
| 136 | mask = 1 << 1; /* G_CNT_U write status */ |
| 137 | break; |
| 138 | default: |
| 139 | return; |
| 140 | } |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 141 | } |
| 142 | |
| 143 | /* Wait maximum 1 ms until written values are applied */ |
| 144 | for (i = 0; i < loops_per_jiffy / 1000 * HZ; i++) |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 145 | if (__raw_readl(reg_base + stat_addr) & mask) { |
| 146 | __raw_writel(mask, reg_base + stat_addr); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 147 | return; |
| 148 | } |
| 149 | |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 150 | panic("MCT hangs after writing %d (offset:0x%lx)\n", value, offset); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 151 | } |
| 152 | |
| 153 | /* Clocksource handling */ |
| 154 | static void exynos4_mct_frc_start(u32 hi, u32 lo) |
| 155 | { |
| 156 | u32 reg; |
| 157 | |
| 158 | exynos4_mct_write(lo, EXYNOS4_MCT_G_CNT_L); |
| 159 | exynos4_mct_write(hi, EXYNOS4_MCT_G_CNT_U); |
| 160 | |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 161 | reg = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 162 | reg |= MCT_G_TCON_START; |
| 163 | exynos4_mct_write(reg, EXYNOS4_MCT_G_TCON); |
| 164 | } |
| 165 | |
| 166 | static cycle_t exynos4_frc_read(struct clocksource *cs) |
| 167 | { |
| 168 | unsigned int lo, hi; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 169 | u32 hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 170 | |
| 171 | do { |
| 172 | hi = hi2; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 173 | lo = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_L); |
| 174 | hi2 = __raw_readl(reg_base + EXYNOS4_MCT_G_CNT_U); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 175 | } while (hi != hi2); |
| 176 | |
| 177 | return ((cycle_t)hi << 32) | lo; |
| 178 | } |
| 179 | |
Changhwan Youn | aa421c1 | 2011-09-02 14:10:52 +0900 | [diff] [blame] | 180 | static void exynos4_frc_resume(struct clocksource *cs) |
| 181 | { |
| 182 | exynos4_mct_frc_start(0, 0); |
| 183 | } |
| 184 | |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 185 | struct clocksource mct_frc = { |
| 186 | .name = "mct-frc", |
| 187 | .rating = 400, |
| 188 | .read = exynos4_frc_read, |
| 189 | .mask = CLOCKSOURCE_MASK(64), |
| 190 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
Changhwan Youn | aa421c1 | 2011-09-02 14:10:52 +0900 | [diff] [blame] | 191 | .resume = exynos4_frc_resume, |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 192 | }; |
| 193 | |
| 194 | static void __init exynos4_clocksource_init(void) |
| 195 | { |
| 196 | exynos4_mct_frc_start(0, 0); |
| 197 | |
| 198 | if (clocksource_register_hz(&mct_frc, clk_rate)) |
| 199 | panic("%s: can't register clocksource\n", mct_frc.name); |
| 200 | } |
| 201 | |
| 202 | static void exynos4_mct_comp0_stop(void) |
| 203 | { |
| 204 | unsigned int tcon; |
| 205 | |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 206 | tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 207 | tcon &= ~(MCT_G_TCON_COMP0_ENABLE | MCT_G_TCON_COMP0_AUTO_INC); |
| 208 | |
| 209 | exynos4_mct_write(tcon, EXYNOS4_MCT_G_TCON); |
| 210 | exynos4_mct_write(0, EXYNOS4_MCT_G_INT_ENB); |
| 211 | } |
| 212 | |
| 213 | static void exynos4_mct_comp0_start(enum clock_event_mode mode, |
| 214 | unsigned long cycles) |
| 215 | { |
| 216 | unsigned int tcon; |
| 217 | cycle_t comp_cycle; |
| 218 | |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 219 | tcon = __raw_readl(reg_base + EXYNOS4_MCT_G_TCON); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 220 | |
| 221 | if (mode == CLOCK_EVT_MODE_PERIODIC) { |
| 222 | tcon |= MCT_G_TCON_COMP0_AUTO_INC; |
| 223 | exynos4_mct_write(cycles, EXYNOS4_MCT_G_COMP0_ADD_INCR); |
| 224 | } |
| 225 | |
| 226 | comp_cycle = exynos4_frc_read(&mct_frc) + cycles; |
| 227 | exynos4_mct_write((u32)comp_cycle, EXYNOS4_MCT_G_COMP0_L); |
| 228 | exynos4_mct_write((u32)(comp_cycle >> 32), EXYNOS4_MCT_G_COMP0_U); |
| 229 | |
| 230 | exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_ENB); |
| 231 | |
| 232 | tcon |= MCT_G_TCON_COMP0_ENABLE; |
| 233 | exynos4_mct_write(tcon , EXYNOS4_MCT_G_TCON); |
| 234 | } |
| 235 | |
| 236 | static int exynos4_comp_set_next_event(unsigned long cycles, |
| 237 | struct clock_event_device *evt) |
| 238 | { |
| 239 | exynos4_mct_comp0_start(evt->mode, cycles); |
| 240 | |
| 241 | return 0; |
| 242 | } |
| 243 | |
| 244 | static void exynos4_comp_set_mode(enum clock_event_mode mode, |
| 245 | struct clock_event_device *evt) |
| 246 | { |
Changhwan Youn | 4d2e4d7 | 2012-03-09 15:09:21 -0800 | [diff] [blame] | 247 | unsigned long cycles_per_jiffy; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 248 | exynos4_mct_comp0_stop(); |
| 249 | |
| 250 | switch (mode) { |
| 251 | case CLOCK_EVT_MODE_PERIODIC: |
Changhwan Youn | 4d2e4d7 | 2012-03-09 15:09:21 -0800 | [diff] [blame] | 252 | cycles_per_jiffy = |
| 253 | (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift); |
| 254 | exynos4_mct_comp0_start(mode, cycles_per_jiffy); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 255 | break; |
| 256 | |
| 257 | case CLOCK_EVT_MODE_ONESHOT: |
| 258 | case CLOCK_EVT_MODE_UNUSED: |
| 259 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 260 | case CLOCK_EVT_MODE_RESUME: |
| 261 | break; |
| 262 | } |
| 263 | } |
| 264 | |
| 265 | static struct clock_event_device mct_comp_device = { |
| 266 | .name = "mct-comp", |
| 267 | .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, |
| 268 | .rating = 250, |
| 269 | .set_next_event = exynos4_comp_set_next_event, |
| 270 | .set_mode = exynos4_comp_set_mode, |
| 271 | }; |
| 272 | |
| 273 | static irqreturn_t exynos4_mct_comp_isr(int irq, void *dev_id) |
| 274 | { |
| 275 | struct clock_event_device *evt = dev_id; |
| 276 | |
| 277 | exynos4_mct_write(0x1, EXYNOS4_MCT_G_INT_CSTAT); |
| 278 | |
| 279 | evt->event_handler(evt); |
| 280 | |
| 281 | return IRQ_HANDLED; |
| 282 | } |
| 283 | |
| 284 | static struct irqaction mct_comp_event_irq = { |
| 285 | .name = "mct_comp_irq", |
| 286 | .flags = IRQF_TIMER | IRQF_IRQPOLL, |
| 287 | .handler = exynos4_mct_comp_isr, |
| 288 | .dev_id = &mct_comp_device, |
| 289 | }; |
| 290 | |
| 291 | static void exynos4_clockevent_init(void) |
| 292 | { |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 293 | mct_comp_device.cpumask = cpumask_of(0); |
Shawn Guo | 838a2ae | 2013-01-12 11:50:05 +0000 | [diff] [blame] | 294 | clockevents_config_and_register(&mct_comp_device, clk_rate, |
| 295 | 0xf, 0xffffffff); |
Thomas Abraham | c371dc6 | 2013-03-09 16:01:50 +0900 | [diff] [blame] | 296 | setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 297 | } |
| 298 | |
| 299 | #ifdef CONFIG_LOCAL_TIMERS |
Kukjin Kim | 991a6c7 | 2011-12-08 10:04:49 +0900 | [diff] [blame] | 300 | |
| 301 | static DEFINE_PER_CPU(struct mct_clock_event_device, percpu_mct_tick); |
| 302 | |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 303 | /* Clock event handling */ |
| 304 | static void exynos4_mct_tick_stop(struct mct_clock_event_device *mevt) |
| 305 | { |
| 306 | unsigned long tmp; |
| 307 | unsigned long mask = MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 308 | unsigned long offset = mevt->base + MCT_L_TCON_OFFSET; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 309 | |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 310 | tmp = __raw_readl(reg_base + offset); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 311 | if (tmp & mask) { |
| 312 | tmp &= ~mask; |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 313 | exynos4_mct_write(tmp, offset); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 314 | } |
| 315 | } |
| 316 | |
| 317 | static void exynos4_mct_tick_start(unsigned long cycles, |
| 318 | struct mct_clock_event_device *mevt) |
| 319 | { |
| 320 | unsigned long tmp; |
| 321 | |
| 322 | exynos4_mct_tick_stop(mevt); |
| 323 | |
| 324 | tmp = (1 << 31) | cycles; /* MCT_L_UPDATE_ICNTB */ |
| 325 | |
| 326 | /* update interrupt count buffer */ |
| 327 | exynos4_mct_write(tmp, mevt->base + MCT_L_ICNTB_OFFSET); |
| 328 | |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 329 | /* enable MCT tick interrupt */ |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 330 | exynos4_mct_write(0x1, mevt->base + MCT_L_INT_ENB_OFFSET); |
| 331 | |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 332 | tmp = __raw_readl(reg_base + mevt->base + MCT_L_TCON_OFFSET); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 333 | tmp |= MCT_L_TCON_INT_START | MCT_L_TCON_TIMER_START | |
| 334 | MCT_L_TCON_INTERVAL_MODE; |
| 335 | exynos4_mct_write(tmp, mevt->base + MCT_L_TCON_OFFSET); |
| 336 | } |
| 337 | |
| 338 | static int exynos4_tick_set_next_event(unsigned long cycles, |
| 339 | struct clock_event_device *evt) |
| 340 | { |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 341 | struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 342 | |
| 343 | exynos4_mct_tick_start(cycles, mevt); |
| 344 | |
| 345 | return 0; |
| 346 | } |
| 347 | |
| 348 | static inline void exynos4_tick_set_mode(enum clock_event_mode mode, |
| 349 | struct clock_event_device *evt) |
| 350 | { |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 351 | struct mct_clock_event_device *mevt = this_cpu_ptr(&percpu_mct_tick); |
Changhwan Youn | 4d2e4d7 | 2012-03-09 15:09:21 -0800 | [diff] [blame] | 352 | unsigned long cycles_per_jiffy; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 353 | |
| 354 | exynos4_mct_tick_stop(mevt); |
| 355 | |
| 356 | switch (mode) { |
| 357 | case CLOCK_EVT_MODE_PERIODIC: |
Changhwan Youn | 4d2e4d7 | 2012-03-09 15:09:21 -0800 | [diff] [blame] | 358 | cycles_per_jiffy = |
| 359 | (((unsigned long long) NSEC_PER_SEC / HZ * evt->mult) >> evt->shift); |
| 360 | exynos4_mct_tick_start(cycles_per_jiffy, mevt); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 361 | break; |
| 362 | |
| 363 | case CLOCK_EVT_MODE_ONESHOT: |
| 364 | case CLOCK_EVT_MODE_UNUSED: |
| 365 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 366 | case CLOCK_EVT_MODE_RESUME: |
| 367 | break; |
| 368 | } |
| 369 | } |
| 370 | |
Changhwan Youn | c898747 | 2011-10-04 17:09:26 +0900 | [diff] [blame] | 371 | static int exynos4_mct_tick_clear(struct mct_clock_event_device *mevt) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 372 | { |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 373 | struct clock_event_device *evt = mevt->evt; |
| 374 | |
| 375 | /* |
| 376 | * This is for supporting oneshot mode. |
| 377 | * Mct would generate interrupt periodically |
| 378 | * without explicit stopping. |
| 379 | */ |
| 380 | if (evt->mode != CLOCK_EVT_MODE_PERIODIC) |
| 381 | exynos4_mct_tick_stop(mevt); |
| 382 | |
| 383 | /* Clear the MCT tick interrupt */ |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 384 | if (__raw_readl(reg_base + mevt->base + MCT_L_INT_CSTAT_OFFSET) & 1) { |
Changhwan Youn | 3a06228 | 2011-10-04 17:02:58 +0900 | [diff] [blame] | 385 | exynos4_mct_write(0x1, mevt->base + MCT_L_INT_CSTAT_OFFSET); |
| 386 | return 1; |
| 387 | } else { |
| 388 | return 0; |
| 389 | } |
| 390 | } |
| 391 | |
| 392 | static irqreturn_t exynos4_mct_tick_isr(int irq, void *dev_id) |
| 393 | { |
| 394 | struct mct_clock_event_device *mevt = dev_id; |
| 395 | struct clock_event_device *evt = mevt->evt; |
| 396 | |
| 397 | exynos4_mct_tick_clear(mevt); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 398 | |
| 399 | evt->event_handler(evt); |
| 400 | |
| 401 | return IRQ_HANDLED; |
| 402 | } |
| 403 | |
| 404 | static struct irqaction mct_tick0_event_irq = { |
| 405 | .name = "mct_tick0_irq", |
| 406 | .flags = IRQF_TIMER | IRQF_NOBALANCING, |
| 407 | .handler = exynos4_mct_tick_isr, |
| 408 | }; |
| 409 | |
| 410 | static struct irqaction mct_tick1_event_irq = { |
| 411 | .name = "mct_tick1_irq", |
| 412 | .flags = IRQF_TIMER | IRQF_NOBALANCING, |
| 413 | .handler = exynos4_mct_tick_isr, |
| 414 | }; |
| 415 | |
Marc Zyngier | a8cb604 | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 416 | static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 417 | { |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 418 | struct mct_clock_event_device *mevt; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 419 | unsigned int cpu = smp_processor_id(); |
| 420 | |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 421 | mevt = this_cpu_ptr(&percpu_mct_tick); |
| 422 | mevt->evt = evt; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 423 | |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 424 | mevt->base = EXYNOS4_MCT_L_BASE(cpu); |
| 425 | sprintf(mevt->name, "mct_tick%d", cpu); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 426 | |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 427 | evt->name = mevt->name; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 428 | evt->cpumask = cpumask_of(cpu); |
| 429 | evt->set_next_event = exynos4_tick_set_next_event; |
| 430 | evt->set_mode = exynos4_tick_set_mode; |
| 431 | evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; |
| 432 | evt->rating = 450; |
Shawn Guo | 838a2ae | 2013-01-12 11:50:05 +0000 | [diff] [blame] | 433 | clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1), |
| 434 | 0xf, 0x7fffffff); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 435 | |
Changhwan Youn | 4d2e4d7 | 2012-03-09 15:09:21 -0800 | [diff] [blame] | 436 | exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 437 | |
Changhwan Youn | 3a06228 | 2011-10-04 17:02:58 +0900 | [diff] [blame] | 438 | if (mct_int_type == MCT_INT_SPI) { |
| 439 | if (cpu == 0) { |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 440 | mct_tick0_event_irq.dev_id = mevt; |
Thomas Abraham | c371dc6 | 2013-03-09 16:01:50 +0900 | [diff] [blame] | 441 | evt->irq = mct_irqs[MCT_L0_IRQ]; |
| 442 | setup_irq(evt->irq, &mct_tick0_event_irq); |
Changhwan Youn | 3a06228 | 2011-10-04 17:02:58 +0900 | [diff] [blame] | 443 | } else { |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 444 | mct_tick1_event_irq.dev_id = mevt; |
Thomas Abraham | c371dc6 | 2013-03-09 16:01:50 +0900 | [diff] [blame] | 445 | evt->irq = mct_irqs[MCT_L1_IRQ]; |
| 446 | setup_irq(evt->irq, &mct_tick1_event_irq); |
| 447 | irq_set_affinity(evt->irq, cpumask_of(1)); |
Changhwan Youn | 3a06228 | 2011-10-04 17:02:58 +0900 | [diff] [blame] | 448 | } |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 449 | } else { |
Thomas Abraham | c371dc6 | 2013-03-09 16:01:50 +0900 | [diff] [blame] | 450 | enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 451 | } |
Kukjin Kim | 4d487d7 | 2011-08-24 16:07:39 +0900 | [diff] [blame] | 452 | |
| 453 | return 0; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 454 | } |
| 455 | |
Marc Zyngier | a8cb604 | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 456 | static void exynos4_local_timer_stop(struct clock_event_device *evt) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 457 | { |
Amit Daniel Kachhap | e248cd5 | 2011-12-08 10:07:08 +0900 | [diff] [blame] | 458 | unsigned int cpu = smp_processor_id(); |
Marc Zyngier | 28af690 | 2011-07-22 12:52:37 +0100 | [diff] [blame] | 459 | evt->set_mode(CLOCK_EVT_MODE_UNUSED, evt); |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 460 | if (mct_int_type == MCT_INT_SPI) |
Amit Daniel Kachhap | e248cd5 | 2011-12-08 10:07:08 +0900 | [diff] [blame] | 461 | if (cpu == 0) |
| 462 | remove_irq(evt->irq, &mct_tick0_event_irq); |
| 463 | else |
| 464 | remove_irq(evt->irq, &mct_tick1_event_irq); |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 465 | else |
Thomas Abraham | c371dc6 | 2013-03-09 16:01:50 +0900 | [diff] [blame] | 466 | disable_percpu_irq(mct_irqs[MCT_L0_IRQ]); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 467 | } |
Marc Zyngier | a8cb604 | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 468 | |
| 469 | static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = { |
| 470 | .setup = exynos4_local_timer_setup, |
| 471 | .stop = exynos4_local_timer_stop, |
| 472 | }; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 473 | #endif /* CONFIG_LOCAL_TIMERS */ |
| 474 | |
Arnd Bergmann | 19ce4f4 | 2013-04-09 22:24:06 +0200 | [diff] [blame] | 475 | static void __init exynos4_timer_resources(struct device_node *np, void __iomem *base) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 476 | { |
Thomas Abraham | ca9048e | 2013-03-09 17:10:37 +0900 | [diff] [blame] | 477 | struct clk *mct_clk, *tick_clk; |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 478 | |
Thomas Abraham | 415ac2e | 2013-03-09 17:10:31 +0900 | [diff] [blame] | 479 | tick_clk = np ? of_clk_get_by_name(np, "fin_pll") : |
| 480 | clk_get(NULL, "fin_pll"); |
| 481 | if (IS_ERR(tick_clk)) |
| 482 | panic("%s: unable to determine tick clock rate\n", __func__); |
| 483 | clk_rate = clk_get_rate(tick_clk); |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 484 | |
Thomas Abraham | ca9048e | 2013-03-09 17:10:37 +0900 | [diff] [blame] | 485 | mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct"); |
| 486 | if (IS_ERR(mct_clk)) |
| 487 | panic("%s: unable to retrieve mct clock instance\n", __func__); |
| 488 | clk_prepare_enable(mct_clk); |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 489 | |
Arnd Bergmann | 228e302 | 2013-04-09 22:07:37 +0200 | [diff] [blame] | 490 | reg_base = base; |
Thomas Abraham | 36ba5d5 | 2013-03-09 16:01:52 +0900 | [diff] [blame] | 491 | if (!reg_base) |
| 492 | panic("%s: unable to ioremap mct address space\n", __func__); |
Thomas Abraham | a1ba7a7 | 2013-03-09 16:01:47 +0900 | [diff] [blame] | 493 | |
Kukjin Kim | 991a6c7 | 2011-12-08 10:04:49 +0900 | [diff] [blame] | 494 | #ifdef CONFIG_LOCAL_TIMERS |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 495 | if (mct_int_type == MCT_INT_PPI) { |
| 496 | int err; |
| 497 | |
Thomas Abraham | c371dc6 | 2013-03-09 16:01:50 +0900 | [diff] [blame] | 498 | err = request_percpu_irq(mct_irqs[MCT_L0_IRQ], |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 499 | exynos4_mct_tick_isr, "MCT", |
| 500 | &percpu_mct_tick); |
| 501 | WARN(err, "MCT: can't request IRQ %d (%d)\n", |
Thomas Abraham | c371dc6 | 2013-03-09 16:01:50 +0900 | [diff] [blame] | 502 | mct_irqs[MCT_L0_IRQ], err); |
Marc Zyngier | e700e41 | 2011-11-03 11:13:12 +0900 | [diff] [blame] | 503 | } |
Marc Zyngier | a8cb604 | 2012-01-10 19:44:19 +0000 | [diff] [blame] | 504 | |
| 505 | local_timer_register(&exynos4_mct_tick_ops); |
Kukjin Kim | 991a6c7 | 2011-12-08 10:04:49 +0900 | [diff] [blame] | 506 | #endif /* CONFIG_LOCAL_TIMERS */ |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 507 | } |
| 508 | |
Arnd Bergmann | 034c097 | 2013-04-10 11:35:29 +0200 | [diff] [blame^] | 509 | void __init mct_init(void __iomem *base, int irq_g0, int irq_l0, int irq_l1) |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 510 | { |
Arnd Bergmann | 034c097 | 2013-04-10 11:35:29 +0200 | [diff] [blame^] | 511 | mct_irqs[MCT_G0_IRQ] = irq_g0; |
| 512 | mct_irqs[MCT_L0_IRQ] = irq_l0; |
| 513 | mct_irqs[MCT_L1_IRQ] = irq_l1; |
| 514 | mct_int_type = MCT_INT_SPI; |
Kukjin Kim | 2edb36c | 2012-11-15 15:48:56 +0900 | [diff] [blame] | 515 | |
Arnd Bergmann | 034c097 | 2013-04-10 11:35:29 +0200 | [diff] [blame^] | 516 | exynos4_timer_resources(NULL, base); |
Changhwan Youn | 30d8bea | 2011-03-11 10:39:57 +0900 | [diff] [blame] | 517 | exynos4_clocksource_init(); |
| 518 | exynos4_clockevent_init(); |
| 519 | } |
Arnd Bergmann | 228e302 | 2013-04-09 22:07:37 +0200 | [diff] [blame] | 520 | |
| 521 | static void __init mct_init_dt(struct device_node *np, unsigned int int_type) |
| 522 | { |
| 523 | u32 nr_irqs, i; |
| 524 | |
| 525 | mct_int_type = int_type; |
| 526 | |
| 527 | /* This driver uses only one global timer interrupt */ |
| 528 | mct_irqs[MCT_G0_IRQ] = irq_of_parse_and_map(np, MCT_G0_IRQ); |
| 529 | |
| 530 | /* |
| 531 | * Find out the number of local irqs specified. The local |
| 532 | * timer irqs are specified after the four global timer |
| 533 | * irqs are specified. |
| 534 | */ |
Arnd Bergmann | f4636d0 | 2013-04-19 22:00:04 +0200 | [diff] [blame] | 535 | #ifdef CONFIG_OF |
Arnd Bergmann | 228e302 | 2013-04-09 22:07:37 +0200 | [diff] [blame] | 536 | nr_irqs = of_irq_count(np); |
Arnd Bergmann | f4636d0 | 2013-04-19 22:00:04 +0200 | [diff] [blame] | 537 | #else |
| 538 | nr_irqs = 0; |
| 539 | #endif |
Arnd Bergmann | 228e302 | 2013-04-09 22:07:37 +0200 | [diff] [blame] | 540 | for (i = MCT_L0_IRQ; i < nr_irqs; i++) |
| 541 | mct_irqs[i] = irq_of_parse_and_map(np, i); |
| 542 | |
Arnd Bergmann | 19ce4f4 | 2013-04-09 22:24:06 +0200 | [diff] [blame] | 543 | exynos4_timer_resources(np, of_iomap(np, 0)); |
Arnd Bergmann | 228e302 | 2013-04-09 22:07:37 +0200 | [diff] [blame] | 544 | exynos4_clocksource_init(); |
| 545 | exynos4_clockevent_init(); |
| 546 | } |
| 547 | |
| 548 | |
| 549 | static void __init mct_init_spi(struct device_node *np) |
| 550 | { |
| 551 | return mct_init_dt(np, MCT_INT_SPI); |
| 552 | } |
| 553 | |
| 554 | static void __init mct_init_ppi(struct device_node *np) |
| 555 | { |
| 556 | return mct_init_dt(np, MCT_INT_PPI); |
| 557 | } |
| 558 | CLOCKSOURCE_OF_DECLARE(exynos4210, "samsung,exynos4210-mct", mct_init_spi); |
| 559 | CLOCKSOURCE_OF_DECLARE(exynos4412, "samsung,exynos4412-mct", mct_init_ppi); |