Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Samsung Electronics Co.Ltd |
| 3 | * Authors: |
| 4 | * Eunchul Kim <chulspro.kim@samsung.com> |
| 5 | * Jinyoung Jeon <jy0.jeon@samsung.com> |
| 6 | * Sangmin Lee <lsmin.lee@samsung.com> |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify it |
| 9 | * under the terms of the GNU General Public License as published by the |
| 10 | * Free Software Foundation; either version 2 of the License, or (at your |
| 11 | * option) any later version. |
| 12 | * |
| 13 | */ |
| 14 | #include <linux/kernel.h> |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 15 | #include <linux/platform_device.h> |
| 16 | #include <linux/clk.h> |
| 17 | #include <linux/pm_runtime.h> |
| 18 | #include <plat/map-base.h> |
| 19 | |
| 20 | #include <drm/drmP.h> |
| 21 | #include <drm/exynos_drm.h> |
| 22 | #include "regs-gsc.h" |
Mark Brown | e30655d | 2013-08-13 00:46:40 +0100 | [diff] [blame] | 23 | #include "exynos_drm_drv.h" |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 24 | #include "exynos_drm_ipp.h" |
| 25 | #include "exynos_drm_gsc.h" |
| 26 | |
| 27 | /* |
Eunchul Kim | 6fe891f | 2012-12-22 17:49:26 +0900 | [diff] [blame] | 28 | * GSC stands for General SCaler and |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 29 | * supports image scaler/rotator and input/output DMA operations. |
| 30 | * input DMA reads image data from the memory. |
| 31 | * output DMA writes image data to memory. |
| 32 | * GSC supports image rotation and image effect functions. |
| 33 | * |
| 34 | * M2M operation : supports crop/scale/rotation/csc so on. |
| 35 | * Memory ----> GSC H/W ----> Memory. |
| 36 | * Writeback operation : supports cloned screen with FIMD. |
| 37 | * FIMD ----> GSC H/W ----> Memory. |
| 38 | * Output operation : supports direct display using local path. |
| 39 | * Memory ----> GSC H/W ----> FIMD, Mixer. |
| 40 | */ |
| 41 | |
| 42 | /* |
| 43 | * TODO |
| 44 | * 1. check suspend/resume api if needed. |
| 45 | * 2. need to check use case platform_device_id. |
| 46 | * 3. check src/dst size with, height. |
| 47 | * 4. added check_prepare api for right register. |
| 48 | * 5. need to add supported list in prop_list. |
| 49 | * 6. check prescaler/scaler optimization. |
| 50 | */ |
| 51 | |
| 52 | #define GSC_MAX_DEVS 4 |
| 53 | #define GSC_MAX_SRC 4 |
| 54 | #define GSC_MAX_DST 16 |
| 55 | #define GSC_RESET_TIMEOUT 50 |
| 56 | #define GSC_BUF_STOP 1 |
| 57 | #define GSC_BUF_START 2 |
| 58 | #define GSC_REG_SZ 16 |
| 59 | #define GSC_WIDTH_ITU_709 1280 |
| 60 | #define GSC_SC_UP_MAX_RATIO 65536 |
| 61 | #define GSC_SC_DOWN_RATIO_7_8 74898 |
| 62 | #define GSC_SC_DOWN_RATIO_6_8 87381 |
| 63 | #define GSC_SC_DOWN_RATIO_5_8 104857 |
| 64 | #define GSC_SC_DOWN_RATIO_4_8 131072 |
| 65 | #define GSC_SC_DOWN_RATIO_3_8 174762 |
| 66 | #define GSC_SC_DOWN_RATIO_2_8 262144 |
| 67 | #define GSC_REFRESH_MIN 12 |
| 68 | #define GSC_REFRESH_MAX 60 |
| 69 | #define GSC_CROP_MAX 8192 |
| 70 | #define GSC_CROP_MIN 32 |
| 71 | #define GSC_SCALE_MAX 4224 |
| 72 | #define GSC_SCALE_MIN 32 |
| 73 | #define GSC_COEF_RATIO 7 |
| 74 | #define GSC_COEF_PHASE 9 |
| 75 | #define GSC_COEF_ATTR 16 |
| 76 | #define GSC_COEF_H_8T 8 |
| 77 | #define GSC_COEF_V_4T 4 |
| 78 | #define GSC_COEF_DEPTH 3 |
| 79 | |
| 80 | #define get_gsc_context(dev) platform_get_drvdata(to_platform_device(dev)) |
| 81 | #define get_ctx_from_ippdrv(ippdrv) container_of(ippdrv,\ |
| 82 | struct gsc_context, ippdrv); |
| 83 | #define gsc_read(offset) readl(ctx->regs + (offset)) |
| 84 | #define gsc_write(cfg, offset) writel(cfg, ctx->regs + (offset)) |
| 85 | |
| 86 | /* |
| 87 | * A structure of scaler. |
| 88 | * |
| 89 | * @range: narrow, wide. |
| 90 | * @pre_shfactor: pre sclaer shift factor. |
| 91 | * @pre_hratio: horizontal ratio of the prescaler. |
| 92 | * @pre_vratio: vertical ratio of the prescaler. |
| 93 | * @main_hratio: the main scaler's horizontal ratio. |
| 94 | * @main_vratio: the main scaler's vertical ratio. |
| 95 | */ |
| 96 | struct gsc_scaler { |
| 97 | bool range; |
| 98 | u32 pre_shfactor; |
| 99 | u32 pre_hratio; |
| 100 | u32 pre_vratio; |
| 101 | unsigned long main_hratio; |
| 102 | unsigned long main_vratio; |
| 103 | }; |
| 104 | |
| 105 | /* |
| 106 | * A structure of scaler capability. |
| 107 | * |
| 108 | * find user manual 49.2 features. |
| 109 | * @tile_w: tile mode or rotation width. |
| 110 | * @tile_h: tile mode or rotation height. |
| 111 | * @w: other cases width. |
| 112 | * @h: other cases height. |
| 113 | */ |
| 114 | struct gsc_capability { |
| 115 | /* tile or rotation */ |
| 116 | u32 tile_w; |
| 117 | u32 tile_h; |
| 118 | /* other cases */ |
| 119 | u32 w; |
| 120 | u32 h; |
| 121 | }; |
| 122 | |
| 123 | /* |
| 124 | * A structure of gsc context. |
| 125 | * |
| 126 | * @ippdrv: prepare initialization using ippdrv. |
| 127 | * @regs_res: register resources. |
| 128 | * @regs: memory mapped io registers. |
| 129 | * @lock: locking of operations. |
| 130 | * @gsc_clk: gsc gate clock. |
| 131 | * @sc: scaler infomations. |
| 132 | * @id: gsc id. |
| 133 | * @irq: irq number. |
| 134 | * @rotation: supports rotation of src. |
| 135 | * @suspended: qos operations. |
| 136 | */ |
| 137 | struct gsc_context { |
| 138 | struct exynos_drm_ippdrv ippdrv; |
| 139 | struct resource *regs_res; |
| 140 | void __iomem *regs; |
| 141 | struct mutex lock; |
| 142 | struct clk *gsc_clk; |
| 143 | struct gsc_scaler sc; |
| 144 | int id; |
| 145 | int irq; |
| 146 | bool rotation; |
| 147 | bool suspended; |
| 148 | }; |
| 149 | |
| 150 | /* 8-tap Filter Coefficient */ |
| 151 | static const int h_coef_8t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_H_8T] = { |
| 152 | { /* Ratio <= 65536 (~8:8) */ |
| 153 | { 0, 0, 0, 128, 0, 0, 0, 0 }, |
| 154 | { -1, 2, -6, 127, 7, -2, 1, 0 }, |
| 155 | { -1, 4, -12, 125, 16, -5, 1, 0 }, |
| 156 | { -1, 5, -15, 120, 25, -8, 2, 0 }, |
| 157 | { -1, 6, -18, 114, 35, -10, 3, -1 }, |
| 158 | { -1, 6, -20, 107, 46, -13, 4, -1 }, |
| 159 | { -2, 7, -21, 99, 57, -16, 5, -1 }, |
| 160 | { -1, 6, -20, 89, 68, -18, 5, -1 }, |
| 161 | { -1, 6, -20, 79, 79, -20, 6, -1 }, |
| 162 | { -1, 5, -18, 68, 89, -20, 6, -1 }, |
| 163 | { -1, 5, -16, 57, 99, -21, 7, -2 }, |
| 164 | { -1, 4, -13, 46, 107, -20, 6, -1 }, |
| 165 | { -1, 3, -10, 35, 114, -18, 6, -1 }, |
| 166 | { 0, 2, -8, 25, 120, -15, 5, -1 }, |
| 167 | { 0, 1, -5, 16, 125, -12, 4, -1 }, |
| 168 | { 0, 1, -2, 7, 127, -6, 2, -1 } |
| 169 | }, { /* 65536 < Ratio <= 74898 (~8:7) */ |
| 170 | { 3, -8, 14, 111, 13, -8, 3, 0 }, |
| 171 | { 2, -6, 7, 112, 21, -10, 3, -1 }, |
| 172 | { 2, -4, 1, 110, 28, -12, 4, -1 }, |
| 173 | { 1, -2, -3, 106, 36, -13, 4, -1 }, |
| 174 | { 1, -1, -7, 103, 44, -15, 4, -1 }, |
| 175 | { 1, 1, -11, 97, 53, -16, 4, -1 }, |
| 176 | { 0, 2, -13, 91, 61, -16, 4, -1 }, |
| 177 | { 0, 3, -15, 85, 69, -17, 4, -1 }, |
| 178 | { 0, 3, -16, 77, 77, -16, 3, 0 }, |
| 179 | { -1, 4, -17, 69, 85, -15, 3, 0 }, |
| 180 | { -1, 4, -16, 61, 91, -13, 2, 0 }, |
| 181 | { -1, 4, -16, 53, 97, -11, 1, 1 }, |
| 182 | { -1, 4, -15, 44, 103, -7, -1, 1 }, |
| 183 | { -1, 4, -13, 36, 106, -3, -2, 1 }, |
| 184 | { -1, 4, -12, 28, 110, 1, -4, 2 }, |
| 185 | { -1, 3, -10, 21, 112, 7, -6, 2 } |
| 186 | }, { /* 74898 < Ratio <= 87381 (~8:6) */ |
| 187 | { 2, -11, 25, 96, 25, -11, 2, 0 }, |
| 188 | { 2, -10, 19, 96, 31, -12, 2, 0 }, |
| 189 | { 2, -9, 14, 94, 37, -12, 2, 0 }, |
| 190 | { 2, -8, 10, 92, 43, -12, 1, 0 }, |
| 191 | { 2, -7, 5, 90, 49, -12, 1, 0 }, |
| 192 | { 2, -5, 1, 86, 55, -12, 0, 1 }, |
| 193 | { 2, -4, -2, 82, 61, -11, -1, 1 }, |
| 194 | { 1, -3, -5, 77, 67, -9, -1, 1 }, |
| 195 | { 1, -2, -7, 72, 72, -7, -2, 1 }, |
| 196 | { 1, -1, -9, 67, 77, -5, -3, 1 }, |
| 197 | { 1, -1, -11, 61, 82, -2, -4, 2 }, |
| 198 | { 1, 0, -12, 55, 86, 1, -5, 2 }, |
| 199 | { 0, 1, -12, 49, 90, 5, -7, 2 }, |
| 200 | { 0, 1, -12, 43, 92, 10, -8, 2 }, |
| 201 | { 0, 2, -12, 37, 94, 14, -9, 2 }, |
| 202 | { 0, 2, -12, 31, 96, 19, -10, 2 } |
| 203 | }, { /* 87381 < Ratio <= 104857 (~8:5) */ |
| 204 | { -1, -8, 33, 80, 33, -8, -1, 0 }, |
| 205 | { -1, -8, 28, 80, 37, -7, -2, 1 }, |
| 206 | { 0, -8, 24, 79, 41, -7, -2, 1 }, |
| 207 | { 0, -8, 20, 78, 46, -6, -3, 1 }, |
| 208 | { 0, -8, 16, 76, 50, -4, -3, 1 }, |
| 209 | { 0, -7, 13, 74, 54, -3, -4, 1 }, |
| 210 | { 1, -7, 10, 71, 58, -1, -5, 1 }, |
| 211 | { 1, -6, 6, 68, 62, 1, -5, 1 }, |
| 212 | { 1, -6, 4, 65, 65, 4, -6, 1 }, |
| 213 | { 1, -5, 1, 62, 68, 6, -6, 1 }, |
| 214 | { 1, -5, -1, 58, 71, 10, -7, 1 }, |
| 215 | { 1, -4, -3, 54, 74, 13, -7, 0 }, |
| 216 | { 1, -3, -4, 50, 76, 16, -8, 0 }, |
| 217 | { 1, -3, -6, 46, 78, 20, -8, 0 }, |
| 218 | { 1, -2, -7, 41, 79, 24, -8, 0 }, |
| 219 | { 1, -2, -7, 37, 80, 28, -8, -1 } |
| 220 | }, { /* 104857 < Ratio <= 131072 (~8:4) */ |
| 221 | { -3, 0, 35, 64, 35, 0, -3, 0 }, |
| 222 | { -3, -1, 32, 64, 38, 1, -3, 0 }, |
| 223 | { -2, -2, 29, 63, 41, 2, -3, 0 }, |
| 224 | { -2, -3, 27, 63, 43, 4, -4, 0 }, |
| 225 | { -2, -3, 24, 61, 46, 6, -4, 0 }, |
| 226 | { -2, -3, 21, 60, 49, 7, -4, 0 }, |
| 227 | { -1, -4, 19, 59, 51, 9, -4, -1 }, |
| 228 | { -1, -4, 16, 57, 53, 12, -4, -1 }, |
| 229 | { -1, -4, 14, 55, 55, 14, -4, -1 }, |
| 230 | { -1, -4, 12, 53, 57, 16, -4, -1 }, |
| 231 | { -1, -4, 9, 51, 59, 19, -4, -1 }, |
| 232 | { 0, -4, 7, 49, 60, 21, -3, -2 }, |
| 233 | { 0, -4, 6, 46, 61, 24, -3, -2 }, |
| 234 | { 0, -4, 4, 43, 63, 27, -3, -2 }, |
| 235 | { 0, -3, 2, 41, 63, 29, -2, -2 }, |
| 236 | { 0, -3, 1, 38, 64, 32, -1, -3 } |
| 237 | }, { /* 131072 < Ratio <= 174762 (~8:3) */ |
| 238 | { -1, 8, 33, 48, 33, 8, -1, 0 }, |
| 239 | { -1, 7, 31, 49, 35, 9, -1, -1 }, |
| 240 | { -1, 6, 30, 49, 36, 10, -1, -1 }, |
| 241 | { -1, 5, 28, 48, 38, 12, -1, -1 }, |
| 242 | { -1, 4, 26, 48, 39, 13, 0, -1 }, |
| 243 | { -1, 3, 24, 47, 41, 15, 0, -1 }, |
| 244 | { -1, 2, 23, 47, 42, 16, 0, -1 }, |
| 245 | { -1, 2, 21, 45, 43, 18, 1, -1 }, |
| 246 | { -1, 1, 19, 45, 45, 19, 1, -1 }, |
| 247 | { -1, 1, 18, 43, 45, 21, 2, -1 }, |
| 248 | { -1, 0, 16, 42, 47, 23, 2, -1 }, |
| 249 | { -1, 0, 15, 41, 47, 24, 3, -1 }, |
| 250 | { -1, 0, 13, 39, 48, 26, 4, -1 }, |
| 251 | { -1, -1, 12, 38, 48, 28, 5, -1 }, |
| 252 | { -1, -1, 10, 36, 49, 30, 6, -1 }, |
| 253 | { -1, -1, 9, 35, 49, 31, 7, -1 } |
| 254 | }, { /* 174762 < Ratio <= 262144 (~8:2) */ |
| 255 | { 2, 13, 30, 38, 30, 13, 2, 0 }, |
| 256 | { 2, 12, 29, 38, 30, 14, 3, 0 }, |
| 257 | { 2, 11, 28, 38, 31, 15, 3, 0 }, |
| 258 | { 2, 10, 26, 38, 32, 16, 4, 0 }, |
| 259 | { 1, 10, 26, 37, 33, 17, 4, 0 }, |
| 260 | { 1, 9, 24, 37, 34, 18, 5, 0 }, |
| 261 | { 1, 8, 24, 37, 34, 19, 5, 0 }, |
| 262 | { 1, 7, 22, 36, 35, 20, 6, 1 }, |
| 263 | { 1, 6, 21, 36, 36, 21, 6, 1 }, |
| 264 | { 1, 6, 20, 35, 36, 22, 7, 1 }, |
| 265 | { 0, 5, 19, 34, 37, 24, 8, 1 }, |
| 266 | { 0, 5, 18, 34, 37, 24, 9, 1 }, |
| 267 | { 0, 4, 17, 33, 37, 26, 10, 1 }, |
| 268 | { 0, 4, 16, 32, 38, 26, 10, 2 }, |
| 269 | { 0, 3, 15, 31, 38, 28, 11, 2 }, |
| 270 | { 0, 3, 14, 30, 38, 29, 12, 2 } |
| 271 | } |
| 272 | }; |
| 273 | |
| 274 | /* 4-tap Filter Coefficient */ |
| 275 | static const int v_coef_4t[GSC_COEF_RATIO][GSC_COEF_ATTR][GSC_COEF_V_4T] = { |
| 276 | { /* Ratio <= 65536 (~8:8) */ |
| 277 | { 0, 128, 0, 0 }, |
| 278 | { -4, 127, 5, 0 }, |
| 279 | { -6, 124, 11, -1 }, |
| 280 | { -8, 118, 19, -1 }, |
| 281 | { -8, 111, 27, -2 }, |
| 282 | { -8, 102, 37, -3 }, |
| 283 | { -8, 92, 48, -4 }, |
| 284 | { -7, 81, 59, -5 }, |
| 285 | { -6, 70, 70, -6 }, |
| 286 | { -5, 59, 81, -7 }, |
| 287 | { -4, 48, 92, -8 }, |
| 288 | { -3, 37, 102, -8 }, |
| 289 | { -2, 27, 111, -8 }, |
| 290 | { -1, 19, 118, -8 }, |
| 291 | { -1, 11, 124, -6 }, |
| 292 | { 0, 5, 127, -4 } |
| 293 | }, { /* 65536 < Ratio <= 74898 (~8:7) */ |
| 294 | { 8, 112, 8, 0 }, |
| 295 | { 4, 111, 14, -1 }, |
| 296 | { 1, 109, 20, -2 }, |
| 297 | { -2, 105, 27, -2 }, |
| 298 | { -3, 100, 34, -3 }, |
| 299 | { -5, 93, 43, -3 }, |
| 300 | { -5, 86, 51, -4 }, |
| 301 | { -5, 77, 60, -4 }, |
| 302 | { -5, 69, 69, -5 }, |
| 303 | { -4, 60, 77, -5 }, |
| 304 | { -4, 51, 86, -5 }, |
| 305 | { -3, 43, 93, -5 }, |
| 306 | { -3, 34, 100, -3 }, |
| 307 | { -2, 27, 105, -2 }, |
| 308 | { -2, 20, 109, 1 }, |
| 309 | { -1, 14, 111, 4 } |
| 310 | }, { /* 74898 < Ratio <= 87381 (~8:6) */ |
| 311 | { 16, 96, 16, 0 }, |
| 312 | { 12, 97, 21, -2 }, |
| 313 | { 8, 96, 26, -2 }, |
| 314 | { 5, 93, 32, -2 }, |
| 315 | { 2, 89, 39, -2 }, |
| 316 | { 0, 84, 46, -2 }, |
| 317 | { -1, 79, 53, -3 }, |
| 318 | { -2, 73, 59, -2 }, |
| 319 | { -2, 66, 66, -2 }, |
| 320 | { -2, 59, 73, -2 }, |
| 321 | { -3, 53, 79, -1 }, |
| 322 | { -2, 46, 84, 0 }, |
| 323 | { -2, 39, 89, 2 }, |
| 324 | { -2, 32, 93, 5 }, |
| 325 | { -2, 26, 96, 8 }, |
| 326 | { -2, 21, 97, 12 } |
| 327 | }, { /* 87381 < Ratio <= 104857 (~8:5) */ |
| 328 | { 22, 84, 22, 0 }, |
| 329 | { 18, 85, 26, -1 }, |
| 330 | { 14, 84, 31, -1 }, |
| 331 | { 11, 82, 36, -1 }, |
| 332 | { 8, 79, 42, -1 }, |
| 333 | { 6, 76, 47, -1 }, |
| 334 | { 4, 72, 52, 0 }, |
| 335 | { 2, 68, 58, 0 }, |
| 336 | { 1, 63, 63, 1 }, |
| 337 | { 0, 58, 68, 2 }, |
| 338 | { 0, 52, 72, 4 }, |
| 339 | { -1, 47, 76, 6 }, |
| 340 | { -1, 42, 79, 8 }, |
| 341 | { -1, 36, 82, 11 }, |
| 342 | { -1, 31, 84, 14 }, |
| 343 | { -1, 26, 85, 18 } |
| 344 | }, { /* 104857 < Ratio <= 131072 (~8:4) */ |
| 345 | { 26, 76, 26, 0 }, |
| 346 | { 22, 76, 30, 0 }, |
| 347 | { 19, 75, 34, 0 }, |
| 348 | { 16, 73, 38, 1 }, |
| 349 | { 13, 71, 43, 1 }, |
| 350 | { 10, 69, 47, 2 }, |
| 351 | { 8, 66, 51, 3 }, |
| 352 | { 6, 63, 55, 4 }, |
| 353 | { 5, 59, 59, 5 }, |
| 354 | { 4, 55, 63, 6 }, |
| 355 | { 3, 51, 66, 8 }, |
| 356 | { 2, 47, 69, 10 }, |
| 357 | { 1, 43, 71, 13 }, |
| 358 | { 1, 38, 73, 16 }, |
| 359 | { 0, 34, 75, 19 }, |
| 360 | { 0, 30, 76, 22 } |
| 361 | }, { /* 131072 < Ratio <= 174762 (~8:3) */ |
| 362 | { 29, 70, 29, 0 }, |
| 363 | { 26, 68, 32, 2 }, |
| 364 | { 23, 67, 36, 2 }, |
| 365 | { 20, 66, 39, 3 }, |
| 366 | { 17, 65, 43, 3 }, |
| 367 | { 15, 63, 46, 4 }, |
| 368 | { 12, 61, 50, 5 }, |
| 369 | { 10, 58, 53, 7 }, |
| 370 | { 8, 56, 56, 8 }, |
| 371 | { 7, 53, 58, 10 }, |
| 372 | { 5, 50, 61, 12 }, |
| 373 | { 4, 46, 63, 15 }, |
| 374 | { 3, 43, 65, 17 }, |
| 375 | { 3, 39, 66, 20 }, |
| 376 | { 2, 36, 67, 23 }, |
| 377 | { 2, 32, 68, 26 } |
| 378 | }, { /* 174762 < Ratio <= 262144 (~8:2) */ |
| 379 | { 32, 64, 32, 0 }, |
| 380 | { 28, 63, 34, 3 }, |
| 381 | { 25, 62, 37, 4 }, |
| 382 | { 22, 62, 40, 4 }, |
| 383 | { 19, 61, 43, 5 }, |
| 384 | { 17, 59, 46, 6 }, |
| 385 | { 15, 58, 48, 7 }, |
| 386 | { 13, 55, 51, 9 }, |
| 387 | { 11, 53, 53, 11 }, |
| 388 | { 9, 51, 55, 13 }, |
| 389 | { 7, 48, 58, 15 }, |
| 390 | { 6, 46, 59, 17 }, |
| 391 | { 5, 43, 61, 19 }, |
| 392 | { 4, 40, 62, 22 }, |
| 393 | { 4, 37, 62, 25 }, |
| 394 | { 3, 34, 63, 28 } |
| 395 | } |
| 396 | }; |
| 397 | |
| 398 | static int gsc_sw_reset(struct gsc_context *ctx) |
| 399 | { |
| 400 | u32 cfg; |
| 401 | int count = GSC_RESET_TIMEOUT; |
| 402 | |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 403 | /* s/w reset */ |
| 404 | cfg = (GSC_SW_RESET_SRESET); |
| 405 | gsc_write(cfg, GSC_SW_RESET); |
| 406 | |
| 407 | /* wait s/w reset complete */ |
| 408 | while (count--) { |
| 409 | cfg = gsc_read(GSC_SW_RESET); |
| 410 | if (!cfg) |
| 411 | break; |
| 412 | usleep_range(1000, 2000); |
| 413 | } |
| 414 | |
| 415 | if (cfg) { |
| 416 | DRM_ERROR("failed to reset gsc h/w.\n"); |
| 417 | return -EBUSY; |
| 418 | } |
| 419 | |
| 420 | /* reset sequence */ |
| 421 | cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); |
| 422 | cfg |= (GSC_IN_BASE_ADDR_MASK | |
| 423 | GSC_IN_BASE_ADDR_PINGPONG(0)); |
| 424 | gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK); |
| 425 | gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK); |
| 426 | gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK); |
| 427 | |
| 428 | cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK); |
| 429 | cfg |= (GSC_OUT_BASE_ADDR_MASK | |
| 430 | GSC_OUT_BASE_ADDR_PINGPONG(0)); |
| 431 | gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK); |
| 432 | gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK); |
| 433 | gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK); |
| 434 | |
| 435 | return 0; |
| 436 | } |
| 437 | |
| 438 | static void gsc_set_gscblk_fimd_wb(struct gsc_context *ctx, bool enable) |
| 439 | { |
| 440 | u32 gscblk_cfg; |
| 441 | |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 442 | gscblk_cfg = readl(SYSREG_GSCBLK_CFG1); |
| 443 | |
| 444 | if (enable) |
| 445 | gscblk_cfg |= GSC_BLK_DISP1WB_DEST(ctx->id) | |
| 446 | GSC_BLK_GSCL_WB_IN_SRC_SEL(ctx->id) | |
| 447 | GSC_BLK_SW_RESET_WB_DEST(ctx->id); |
| 448 | else |
| 449 | gscblk_cfg |= GSC_BLK_PXLASYNC_LO_MASK_WB(ctx->id); |
| 450 | |
| 451 | writel(gscblk_cfg, SYSREG_GSCBLK_CFG1); |
| 452 | } |
| 453 | |
| 454 | static void gsc_handle_irq(struct gsc_context *ctx, bool enable, |
| 455 | bool overflow, bool done) |
| 456 | { |
| 457 | u32 cfg; |
| 458 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 459 | DRM_DEBUG_KMS("enable[%d]overflow[%d]level[%d]\n", |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 460 | enable, overflow, done); |
| 461 | |
| 462 | cfg = gsc_read(GSC_IRQ); |
| 463 | cfg |= (GSC_IRQ_OR_MASK | GSC_IRQ_FRMDONE_MASK); |
| 464 | |
| 465 | if (enable) |
| 466 | cfg |= GSC_IRQ_ENABLE; |
| 467 | else |
| 468 | cfg &= ~GSC_IRQ_ENABLE; |
| 469 | |
| 470 | if (overflow) |
| 471 | cfg &= ~GSC_IRQ_OR_MASK; |
| 472 | else |
| 473 | cfg |= GSC_IRQ_OR_MASK; |
| 474 | |
| 475 | if (done) |
| 476 | cfg &= ~GSC_IRQ_FRMDONE_MASK; |
| 477 | else |
| 478 | cfg |= GSC_IRQ_FRMDONE_MASK; |
| 479 | |
| 480 | gsc_write(cfg, GSC_IRQ); |
| 481 | } |
| 482 | |
| 483 | |
| 484 | static int gsc_src_set_fmt(struct device *dev, u32 fmt) |
| 485 | { |
| 486 | struct gsc_context *ctx = get_gsc_context(dev); |
| 487 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; |
| 488 | u32 cfg; |
| 489 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 490 | DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 491 | |
| 492 | cfg = gsc_read(GSC_IN_CON); |
| 493 | cfg &= ~(GSC_IN_RGB_TYPE_MASK | GSC_IN_YUV422_1P_ORDER_MASK | |
| 494 | GSC_IN_CHROMA_ORDER_MASK | GSC_IN_FORMAT_MASK | |
| 495 | GSC_IN_TILE_TYPE_MASK | GSC_IN_TILE_MODE | |
| 496 | GSC_IN_CHROM_STRIDE_SEL_MASK | GSC_IN_RB_SWAP_MASK); |
| 497 | |
| 498 | switch (fmt) { |
| 499 | case DRM_FORMAT_RGB565: |
| 500 | cfg |= GSC_IN_RGB565; |
| 501 | break; |
| 502 | case DRM_FORMAT_XRGB8888: |
| 503 | cfg |= GSC_IN_XRGB8888; |
| 504 | break; |
| 505 | case DRM_FORMAT_BGRX8888: |
| 506 | cfg |= (GSC_IN_XRGB8888 | GSC_IN_RB_SWAP); |
| 507 | break; |
| 508 | case DRM_FORMAT_YUYV: |
| 509 | cfg |= (GSC_IN_YUV422_1P | |
| 510 | GSC_IN_YUV422_1P_ORDER_LSB_Y | |
| 511 | GSC_IN_CHROMA_ORDER_CBCR); |
| 512 | break; |
| 513 | case DRM_FORMAT_YVYU: |
| 514 | cfg |= (GSC_IN_YUV422_1P | |
| 515 | GSC_IN_YUV422_1P_ORDER_LSB_Y | |
| 516 | GSC_IN_CHROMA_ORDER_CRCB); |
| 517 | break; |
| 518 | case DRM_FORMAT_UYVY: |
| 519 | cfg |= (GSC_IN_YUV422_1P | |
| 520 | GSC_IN_YUV422_1P_OEDER_LSB_C | |
| 521 | GSC_IN_CHROMA_ORDER_CBCR); |
| 522 | break; |
| 523 | case DRM_FORMAT_VYUY: |
| 524 | cfg |= (GSC_IN_YUV422_1P | |
| 525 | GSC_IN_YUV422_1P_OEDER_LSB_C | |
| 526 | GSC_IN_CHROMA_ORDER_CRCB); |
| 527 | break; |
| 528 | case DRM_FORMAT_NV21: |
| 529 | case DRM_FORMAT_NV61: |
| 530 | cfg |= (GSC_IN_CHROMA_ORDER_CRCB | |
| 531 | GSC_IN_YUV420_2P); |
| 532 | break; |
| 533 | case DRM_FORMAT_YUV422: |
| 534 | cfg |= GSC_IN_YUV422_3P; |
| 535 | break; |
| 536 | case DRM_FORMAT_YUV420: |
| 537 | case DRM_FORMAT_YVU420: |
| 538 | cfg |= GSC_IN_YUV420_3P; |
| 539 | break; |
| 540 | case DRM_FORMAT_NV12: |
| 541 | case DRM_FORMAT_NV16: |
| 542 | cfg |= (GSC_IN_CHROMA_ORDER_CBCR | |
| 543 | GSC_IN_YUV420_2P); |
| 544 | break; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 545 | default: |
Ingi Kim | c691349 | 2015-10-02 17:59:26 +0900 | [diff] [blame] | 546 | dev_err(ippdrv->dev, "invalid target yuv order 0x%x.\n", fmt); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 547 | return -EINVAL; |
| 548 | } |
| 549 | |
| 550 | gsc_write(cfg, GSC_IN_CON); |
| 551 | |
| 552 | return 0; |
| 553 | } |
| 554 | |
| 555 | static int gsc_src_set_transf(struct device *dev, |
| 556 | enum drm_exynos_degree degree, |
| 557 | enum drm_exynos_flip flip, bool *swap) |
| 558 | { |
| 559 | struct gsc_context *ctx = get_gsc_context(dev); |
| 560 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; |
| 561 | u32 cfg; |
| 562 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 563 | DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 564 | |
| 565 | cfg = gsc_read(GSC_IN_CON); |
| 566 | cfg &= ~GSC_IN_ROT_MASK; |
| 567 | |
| 568 | switch (degree) { |
| 569 | case EXYNOS_DRM_DEGREE_0: |
| 570 | if (flip & EXYNOS_DRM_FLIP_VERTICAL) |
| 571 | cfg |= GSC_IN_ROT_XFLIP; |
| 572 | if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) |
| 573 | cfg |= GSC_IN_ROT_YFLIP; |
| 574 | break; |
| 575 | case EXYNOS_DRM_DEGREE_90: |
| 576 | if (flip & EXYNOS_DRM_FLIP_VERTICAL) |
| 577 | cfg |= GSC_IN_ROT_90_XFLIP; |
| 578 | else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) |
| 579 | cfg |= GSC_IN_ROT_90_YFLIP; |
| 580 | else |
| 581 | cfg |= GSC_IN_ROT_90; |
| 582 | break; |
| 583 | case EXYNOS_DRM_DEGREE_180: |
| 584 | cfg |= GSC_IN_ROT_180; |
Hyungwon Hwang | 5149705 | 2015-07-01 19:09:25 +0900 | [diff] [blame] | 585 | if (flip & EXYNOS_DRM_FLIP_VERTICAL) |
| 586 | cfg &= ~GSC_IN_ROT_XFLIP; |
| 587 | if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) |
| 588 | cfg &= ~GSC_IN_ROT_YFLIP; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 589 | break; |
| 590 | case EXYNOS_DRM_DEGREE_270: |
| 591 | cfg |= GSC_IN_ROT_270; |
Hyungwon Hwang | 5149705 | 2015-07-01 19:09:25 +0900 | [diff] [blame] | 592 | if (flip & EXYNOS_DRM_FLIP_VERTICAL) |
| 593 | cfg &= ~GSC_IN_ROT_XFLIP; |
| 594 | if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) |
| 595 | cfg &= ~GSC_IN_ROT_YFLIP; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 596 | break; |
| 597 | default: |
Ingi Kim | c691349 | 2015-10-02 17:59:26 +0900 | [diff] [blame] | 598 | dev_err(ippdrv->dev, "invalid degree value %d.\n", degree); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 599 | return -EINVAL; |
| 600 | } |
| 601 | |
| 602 | gsc_write(cfg, GSC_IN_CON); |
| 603 | |
Hyungwon Hwang | 988a473 | 2015-07-01 19:09:24 +0900 | [diff] [blame] | 604 | ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 605 | *swap = ctx->rotation; |
| 606 | |
| 607 | return 0; |
| 608 | } |
| 609 | |
| 610 | static int gsc_src_set_size(struct device *dev, int swap, |
| 611 | struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) |
| 612 | { |
| 613 | struct gsc_context *ctx = get_gsc_context(dev); |
| 614 | struct drm_exynos_pos img_pos = *pos; |
| 615 | struct gsc_scaler *sc = &ctx->sc; |
| 616 | u32 cfg; |
| 617 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 618 | DRM_DEBUG_KMS("swap[%d]x[%d]y[%d]w[%d]h[%d]\n", |
| 619 | swap, pos->x, pos->y, pos->w, pos->h); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 620 | |
| 621 | if (swap) { |
| 622 | img_pos.w = pos->h; |
| 623 | img_pos.h = pos->w; |
| 624 | } |
| 625 | |
| 626 | /* pixel offset */ |
| 627 | cfg = (GSC_SRCIMG_OFFSET_X(img_pos.x) | |
| 628 | GSC_SRCIMG_OFFSET_Y(img_pos.y)); |
| 629 | gsc_write(cfg, GSC_SRCIMG_OFFSET); |
| 630 | |
| 631 | /* cropped size */ |
| 632 | cfg = (GSC_CROPPED_WIDTH(img_pos.w) | |
| 633 | GSC_CROPPED_HEIGHT(img_pos.h)); |
| 634 | gsc_write(cfg, GSC_CROPPED_SIZE); |
| 635 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 636 | DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", sz->hsize, sz->vsize); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 637 | |
| 638 | /* original size */ |
| 639 | cfg = gsc_read(GSC_SRCIMG_SIZE); |
| 640 | cfg &= ~(GSC_SRCIMG_HEIGHT_MASK | |
| 641 | GSC_SRCIMG_WIDTH_MASK); |
| 642 | |
| 643 | cfg |= (GSC_SRCIMG_WIDTH(sz->hsize) | |
| 644 | GSC_SRCIMG_HEIGHT(sz->vsize)); |
| 645 | |
| 646 | gsc_write(cfg, GSC_SRCIMG_SIZE); |
| 647 | |
| 648 | cfg = gsc_read(GSC_IN_CON); |
| 649 | cfg &= ~GSC_IN_RGB_TYPE_MASK; |
| 650 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 651 | DRM_DEBUG_KMS("width[%d]range[%d]\n", pos->w, sc->range); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 652 | |
| 653 | if (pos->w >= GSC_WIDTH_ITU_709) |
| 654 | if (sc->range) |
| 655 | cfg |= GSC_IN_RGB_HD_WIDE; |
| 656 | else |
| 657 | cfg |= GSC_IN_RGB_HD_NARROW; |
| 658 | else |
| 659 | if (sc->range) |
| 660 | cfg |= GSC_IN_RGB_SD_WIDE; |
| 661 | else |
| 662 | cfg |= GSC_IN_RGB_SD_NARROW; |
| 663 | |
| 664 | gsc_write(cfg, GSC_IN_CON); |
| 665 | |
| 666 | return 0; |
| 667 | } |
| 668 | |
| 669 | static int gsc_src_set_buf_seq(struct gsc_context *ctx, u32 buf_id, |
| 670 | enum drm_exynos_ipp_buf_type buf_type) |
| 671 | { |
| 672 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; |
| 673 | bool masked; |
| 674 | u32 cfg; |
| 675 | u32 mask = 0x00000001 << buf_id; |
| 676 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 677 | DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 678 | |
| 679 | /* mask register set */ |
| 680 | cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); |
| 681 | |
| 682 | switch (buf_type) { |
| 683 | case IPP_BUF_ENQUEUE: |
| 684 | masked = false; |
| 685 | break; |
| 686 | case IPP_BUF_DEQUEUE: |
| 687 | masked = true; |
| 688 | break; |
| 689 | default: |
| 690 | dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n"); |
| 691 | return -EINVAL; |
| 692 | } |
| 693 | |
| 694 | /* sequence id */ |
| 695 | cfg &= ~mask; |
| 696 | cfg |= masked << buf_id; |
| 697 | gsc_write(cfg, GSC_IN_BASE_ADDR_Y_MASK); |
| 698 | gsc_write(cfg, GSC_IN_BASE_ADDR_CB_MASK); |
| 699 | gsc_write(cfg, GSC_IN_BASE_ADDR_CR_MASK); |
| 700 | |
| 701 | return 0; |
| 702 | } |
| 703 | |
| 704 | static int gsc_src_set_addr(struct device *dev, |
| 705 | struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id, |
| 706 | enum drm_exynos_ipp_buf_type buf_type) |
| 707 | { |
| 708 | struct gsc_context *ctx = get_gsc_context(dev); |
| 709 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; |
Eunchul Kim | 7259c3d | 2012-12-22 17:49:22 +0900 | [diff] [blame] | 710 | struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 711 | struct drm_exynos_ipp_property *property; |
| 712 | |
| 713 | if (!c_node) { |
| 714 | DRM_ERROR("failed to get c_node.\n"); |
| 715 | return -EFAULT; |
| 716 | } |
| 717 | |
| 718 | property = &c_node->property; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 719 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 720 | DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n", |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 721 | property->prop_id, buf_id, buf_type); |
| 722 | |
| 723 | if (buf_id > GSC_MAX_SRC) { |
Ingi Kim | c691349 | 2015-10-02 17:59:26 +0900 | [diff] [blame] | 724 | dev_info(ippdrv->dev, "invalid buf_id %d.\n", buf_id); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 725 | return -EINVAL; |
| 726 | } |
| 727 | |
| 728 | /* address register set */ |
| 729 | switch (buf_type) { |
| 730 | case IPP_BUF_ENQUEUE: |
| 731 | gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y], |
| 732 | GSC_IN_BASE_ADDR_Y(buf_id)); |
| 733 | gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], |
| 734 | GSC_IN_BASE_ADDR_CB(buf_id)); |
| 735 | gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], |
| 736 | GSC_IN_BASE_ADDR_CR(buf_id)); |
| 737 | break; |
| 738 | case IPP_BUF_DEQUEUE: |
| 739 | gsc_write(0x0, GSC_IN_BASE_ADDR_Y(buf_id)); |
| 740 | gsc_write(0x0, GSC_IN_BASE_ADDR_CB(buf_id)); |
| 741 | gsc_write(0x0, GSC_IN_BASE_ADDR_CR(buf_id)); |
| 742 | break; |
| 743 | default: |
| 744 | /* bypass */ |
| 745 | break; |
| 746 | } |
| 747 | |
| 748 | return gsc_src_set_buf_seq(ctx, buf_id, buf_type); |
| 749 | } |
| 750 | |
| 751 | static struct exynos_drm_ipp_ops gsc_src_ops = { |
| 752 | .set_fmt = gsc_src_set_fmt, |
| 753 | .set_transf = gsc_src_set_transf, |
| 754 | .set_size = gsc_src_set_size, |
| 755 | .set_addr = gsc_src_set_addr, |
| 756 | }; |
| 757 | |
| 758 | static int gsc_dst_set_fmt(struct device *dev, u32 fmt) |
| 759 | { |
| 760 | struct gsc_context *ctx = get_gsc_context(dev); |
| 761 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; |
| 762 | u32 cfg; |
| 763 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 764 | DRM_DEBUG_KMS("fmt[0x%x]\n", fmt); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 765 | |
| 766 | cfg = gsc_read(GSC_OUT_CON); |
| 767 | cfg &= ~(GSC_OUT_RGB_TYPE_MASK | GSC_OUT_YUV422_1P_ORDER_MASK | |
| 768 | GSC_OUT_CHROMA_ORDER_MASK | GSC_OUT_FORMAT_MASK | |
| 769 | GSC_OUT_CHROM_STRIDE_SEL_MASK | GSC_OUT_RB_SWAP_MASK | |
| 770 | GSC_OUT_GLOBAL_ALPHA_MASK); |
| 771 | |
| 772 | switch (fmt) { |
| 773 | case DRM_FORMAT_RGB565: |
| 774 | cfg |= GSC_OUT_RGB565; |
| 775 | break; |
| 776 | case DRM_FORMAT_XRGB8888: |
| 777 | cfg |= GSC_OUT_XRGB8888; |
| 778 | break; |
| 779 | case DRM_FORMAT_BGRX8888: |
| 780 | cfg |= (GSC_OUT_XRGB8888 | GSC_OUT_RB_SWAP); |
| 781 | break; |
| 782 | case DRM_FORMAT_YUYV: |
| 783 | cfg |= (GSC_OUT_YUV422_1P | |
| 784 | GSC_OUT_YUV422_1P_ORDER_LSB_Y | |
| 785 | GSC_OUT_CHROMA_ORDER_CBCR); |
| 786 | break; |
| 787 | case DRM_FORMAT_YVYU: |
| 788 | cfg |= (GSC_OUT_YUV422_1P | |
| 789 | GSC_OUT_YUV422_1P_ORDER_LSB_Y | |
| 790 | GSC_OUT_CHROMA_ORDER_CRCB); |
| 791 | break; |
| 792 | case DRM_FORMAT_UYVY: |
| 793 | cfg |= (GSC_OUT_YUV422_1P | |
| 794 | GSC_OUT_YUV422_1P_OEDER_LSB_C | |
| 795 | GSC_OUT_CHROMA_ORDER_CBCR); |
| 796 | break; |
| 797 | case DRM_FORMAT_VYUY: |
| 798 | cfg |= (GSC_OUT_YUV422_1P | |
| 799 | GSC_OUT_YUV422_1P_OEDER_LSB_C | |
| 800 | GSC_OUT_CHROMA_ORDER_CRCB); |
| 801 | break; |
| 802 | case DRM_FORMAT_NV21: |
| 803 | case DRM_FORMAT_NV61: |
| 804 | cfg |= (GSC_OUT_CHROMA_ORDER_CRCB | GSC_OUT_YUV420_2P); |
| 805 | break; |
| 806 | case DRM_FORMAT_YUV422: |
| 807 | case DRM_FORMAT_YUV420: |
| 808 | case DRM_FORMAT_YVU420: |
| 809 | cfg |= GSC_OUT_YUV420_3P; |
| 810 | break; |
| 811 | case DRM_FORMAT_NV12: |
| 812 | case DRM_FORMAT_NV16: |
| 813 | cfg |= (GSC_OUT_CHROMA_ORDER_CBCR | |
| 814 | GSC_OUT_YUV420_2P); |
| 815 | break; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 816 | default: |
Ingi Kim | c691349 | 2015-10-02 17:59:26 +0900 | [diff] [blame] | 817 | dev_err(ippdrv->dev, "invalid target yuv order 0x%x.\n", fmt); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 818 | return -EINVAL; |
| 819 | } |
| 820 | |
| 821 | gsc_write(cfg, GSC_OUT_CON); |
| 822 | |
| 823 | return 0; |
| 824 | } |
| 825 | |
| 826 | static int gsc_dst_set_transf(struct device *dev, |
| 827 | enum drm_exynos_degree degree, |
| 828 | enum drm_exynos_flip flip, bool *swap) |
| 829 | { |
| 830 | struct gsc_context *ctx = get_gsc_context(dev); |
| 831 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; |
| 832 | u32 cfg; |
| 833 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 834 | DRM_DEBUG_KMS("degree[%d]flip[0x%x]\n", degree, flip); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 835 | |
| 836 | cfg = gsc_read(GSC_IN_CON); |
| 837 | cfg &= ~GSC_IN_ROT_MASK; |
| 838 | |
| 839 | switch (degree) { |
| 840 | case EXYNOS_DRM_DEGREE_0: |
| 841 | if (flip & EXYNOS_DRM_FLIP_VERTICAL) |
| 842 | cfg |= GSC_IN_ROT_XFLIP; |
| 843 | if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) |
| 844 | cfg |= GSC_IN_ROT_YFLIP; |
| 845 | break; |
| 846 | case EXYNOS_DRM_DEGREE_90: |
| 847 | if (flip & EXYNOS_DRM_FLIP_VERTICAL) |
| 848 | cfg |= GSC_IN_ROT_90_XFLIP; |
| 849 | else if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) |
| 850 | cfg |= GSC_IN_ROT_90_YFLIP; |
| 851 | else |
| 852 | cfg |= GSC_IN_ROT_90; |
| 853 | break; |
| 854 | case EXYNOS_DRM_DEGREE_180: |
| 855 | cfg |= GSC_IN_ROT_180; |
Hyungwon Hwang | 5149705 | 2015-07-01 19:09:25 +0900 | [diff] [blame] | 856 | if (flip & EXYNOS_DRM_FLIP_VERTICAL) |
| 857 | cfg &= ~GSC_IN_ROT_XFLIP; |
| 858 | if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) |
| 859 | cfg &= ~GSC_IN_ROT_YFLIP; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 860 | break; |
| 861 | case EXYNOS_DRM_DEGREE_270: |
| 862 | cfg |= GSC_IN_ROT_270; |
Hyungwon Hwang | 5149705 | 2015-07-01 19:09:25 +0900 | [diff] [blame] | 863 | if (flip & EXYNOS_DRM_FLIP_VERTICAL) |
| 864 | cfg &= ~GSC_IN_ROT_XFLIP; |
| 865 | if (flip & EXYNOS_DRM_FLIP_HORIZONTAL) |
| 866 | cfg &= ~GSC_IN_ROT_YFLIP; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 867 | break; |
| 868 | default: |
Ingi Kim | c691349 | 2015-10-02 17:59:26 +0900 | [diff] [blame] | 869 | dev_err(ippdrv->dev, "invalid degree value %d.\n", degree); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 870 | return -EINVAL; |
| 871 | } |
| 872 | |
| 873 | gsc_write(cfg, GSC_IN_CON); |
| 874 | |
Hyungwon Hwang | 988a473 | 2015-07-01 19:09:24 +0900 | [diff] [blame] | 875 | ctx->rotation = (cfg & GSC_IN_ROT_90) ? 1 : 0; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 876 | *swap = ctx->rotation; |
| 877 | |
| 878 | return 0; |
| 879 | } |
| 880 | |
| 881 | static int gsc_get_ratio_shift(u32 src, u32 dst, u32 *ratio) |
| 882 | { |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 883 | DRM_DEBUG_KMS("src[%d]dst[%d]\n", src, dst); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 884 | |
| 885 | if (src >= dst * 8) { |
| 886 | DRM_ERROR("failed to make ratio and shift.\n"); |
| 887 | return -EINVAL; |
| 888 | } else if (src >= dst * 4) |
| 889 | *ratio = 4; |
| 890 | else if (src >= dst * 2) |
| 891 | *ratio = 2; |
| 892 | else |
| 893 | *ratio = 1; |
| 894 | |
| 895 | return 0; |
| 896 | } |
| 897 | |
| 898 | static void gsc_get_prescaler_shfactor(u32 hratio, u32 vratio, u32 *shfactor) |
| 899 | { |
| 900 | if (hratio == 4 && vratio == 4) |
| 901 | *shfactor = 4; |
| 902 | else if ((hratio == 4 && vratio == 2) || |
| 903 | (hratio == 2 && vratio == 4)) |
| 904 | *shfactor = 3; |
| 905 | else if ((hratio == 4 && vratio == 1) || |
| 906 | (hratio == 1 && vratio == 4) || |
| 907 | (hratio == 2 && vratio == 2)) |
| 908 | *shfactor = 2; |
| 909 | else if (hratio == 1 && vratio == 1) |
| 910 | *shfactor = 0; |
| 911 | else |
| 912 | *shfactor = 1; |
| 913 | } |
| 914 | |
| 915 | static int gsc_set_prescaler(struct gsc_context *ctx, struct gsc_scaler *sc, |
| 916 | struct drm_exynos_pos *src, struct drm_exynos_pos *dst) |
| 917 | { |
| 918 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; |
| 919 | u32 cfg; |
| 920 | u32 src_w, src_h, dst_w, dst_h; |
| 921 | int ret = 0; |
| 922 | |
| 923 | src_w = src->w; |
| 924 | src_h = src->h; |
| 925 | |
| 926 | if (ctx->rotation) { |
| 927 | dst_w = dst->h; |
| 928 | dst_h = dst->w; |
| 929 | } else { |
| 930 | dst_w = dst->w; |
| 931 | dst_h = dst->h; |
| 932 | } |
| 933 | |
| 934 | ret = gsc_get_ratio_shift(src_w, dst_w, &sc->pre_hratio); |
| 935 | if (ret) { |
| 936 | dev_err(ippdrv->dev, "failed to get ratio horizontal.\n"); |
| 937 | return ret; |
| 938 | } |
| 939 | |
| 940 | ret = gsc_get_ratio_shift(src_h, dst_h, &sc->pre_vratio); |
| 941 | if (ret) { |
| 942 | dev_err(ippdrv->dev, "failed to get ratio vertical.\n"); |
| 943 | return ret; |
| 944 | } |
| 945 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 946 | DRM_DEBUG_KMS("pre_hratio[%d]pre_vratio[%d]\n", |
| 947 | sc->pre_hratio, sc->pre_vratio); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 948 | |
| 949 | sc->main_hratio = (src_w << 16) / dst_w; |
| 950 | sc->main_vratio = (src_h << 16) / dst_h; |
| 951 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 952 | DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n", |
| 953 | sc->main_hratio, sc->main_vratio); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 954 | |
| 955 | gsc_get_prescaler_shfactor(sc->pre_hratio, sc->pre_vratio, |
| 956 | &sc->pre_shfactor); |
| 957 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 958 | DRM_DEBUG_KMS("pre_shfactor[%d]\n", sc->pre_shfactor); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 959 | |
| 960 | cfg = (GSC_PRESC_SHFACTOR(sc->pre_shfactor) | |
| 961 | GSC_PRESC_H_RATIO(sc->pre_hratio) | |
| 962 | GSC_PRESC_V_RATIO(sc->pre_vratio)); |
| 963 | gsc_write(cfg, GSC_PRE_SCALE_RATIO); |
| 964 | |
| 965 | return ret; |
| 966 | } |
| 967 | |
| 968 | static void gsc_set_h_coef(struct gsc_context *ctx, unsigned long main_hratio) |
| 969 | { |
| 970 | int i, j, k, sc_ratio; |
| 971 | |
| 972 | if (main_hratio <= GSC_SC_UP_MAX_RATIO) |
| 973 | sc_ratio = 0; |
| 974 | else if (main_hratio <= GSC_SC_DOWN_RATIO_7_8) |
| 975 | sc_ratio = 1; |
| 976 | else if (main_hratio <= GSC_SC_DOWN_RATIO_6_8) |
| 977 | sc_ratio = 2; |
| 978 | else if (main_hratio <= GSC_SC_DOWN_RATIO_5_8) |
| 979 | sc_ratio = 3; |
| 980 | else if (main_hratio <= GSC_SC_DOWN_RATIO_4_8) |
| 981 | sc_ratio = 4; |
| 982 | else if (main_hratio <= GSC_SC_DOWN_RATIO_3_8) |
| 983 | sc_ratio = 5; |
| 984 | else |
| 985 | sc_ratio = 6; |
| 986 | |
| 987 | for (i = 0; i < GSC_COEF_PHASE; i++) |
| 988 | for (j = 0; j < GSC_COEF_H_8T; j++) |
| 989 | for (k = 0; k < GSC_COEF_DEPTH; k++) |
| 990 | gsc_write(h_coef_8t[sc_ratio][i][j], |
| 991 | GSC_HCOEF(i, j, k)); |
| 992 | } |
| 993 | |
| 994 | static void gsc_set_v_coef(struct gsc_context *ctx, unsigned long main_vratio) |
| 995 | { |
| 996 | int i, j, k, sc_ratio; |
| 997 | |
| 998 | if (main_vratio <= GSC_SC_UP_MAX_RATIO) |
| 999 | sc_ratio = 0; |
| 1000 | else if (main_vratio <= GSC_SC_DOWN_RATIO_7_8) |
| 1001 | sc_ratio = 1; |
| 1002 | else if (main_vratio <= GSC_SC_DOWN_RATIO_6_8) |
| 1003 | sc_ratio = 2; |
| 1004 | else if (main_vratio <= GSC_SC_DOWN_RATIO_5_8) |
| 1005 | sc_ratio = 3; |
| 1006 | else if (main_vratio <= GSC_SC_DOWN_RATIO_4_8) |
| 1007 | sc_ratio = 4; |
| 1008 | else if (main_vratio <= GSC_SC_DOWN_RATIO_3_8) |
| 1009 | sc_ratio = 5; |
| 1010 | else |
| 1011 | sc_ratio = 6; |
| 1012 | |
| 1013 | for (i = 0; i < GSC_COEF_PHASE; i++) |
| 1014 | for (j = 0; j < GSC_COEF_V_4T; j++) |
| 1015 | for (k = 0; k < GSC_COEF_DEPTH; k++) |
| 1016 | gsc_write(v_coef_4t[sc_ratio][i][j], |
| 1017 | GSC_VCOEF(i, j, k)); |
| 1018 | } |
| 1019 | |
| 1020 | static void gsc_set_scaler(struct gsc_context *ctx, struct gsc_scaler *sc) |
| 1021 | { |
| 1022 | u32 cfg; |
| 1023 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1024 | DRM_DEBUG_KMS("main_hratio[%ld]main_vratio[%ld]\n", |
| 1025 | sc->main_hratio, sc->main_vratio); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1026 | |
| 1027 | gsc_set_h_coef(ctx, sc->main_hratio); |
| 1028 | cfg = GSC_MAIN_H_RATIO_VALUE(sc->main_hratio); |
| 1029 | gsc_write(cfg, GSC_MAIN_H_RATIO); |
| 1030 | |
| 1031 | gsc_set_v_coef(ctx, sc->main_vratio); |
| 1032 | cfg = GSC_MAIN_V_RATIO_VALUE(sc->main_vratio); |
| 1033 | gsc_write(cfg, GSC_MAIN_V_RATIO); |
| 1034 | } |
| 1035 | |
| 1036 | static int gsc_dst_set_size(struct device *dev, int swap, |
| 1037 | struct drm_exynos_pos *pos, struct drm_exynos_sz *sz) |
| 1038 | { |
| 1039 | struct gsc_context *ctx = get_gsc_context(dev); |
| 1040 | struct drm_exynos_pos img_pos = *pos; |
| 1041 | struct gsc_scaler *sc = &ctx->sc; |
| 1042 | u32 cfg; |
| 1043 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1044 | DRM_DEBUG_KMS("swap[%d]x[%d]y[%d]w[%d]h[%d]\n", |
| 1045 | swap, pos->x, pos->y, pos->w, pos->h); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1046 | |
| 1047 | if (swap) { |
| 1048 | img_pos.w = pos->h; |
| 1049 | img_pos.h = pos->w; |
| 1050 | } |
| 1051 | |
| 1052 | /* pixel offset */ |
| 1053 | cfg = (GSC_DSTIMG_OFFSET_X(pos->x) | |
| 1054 | GSC_DSTIMG_OFFSET_Y(pos->y)); |
| 1055 | gsc_write(cfg, GSC_DSTIMG_OFFSET); |
| 1056 | |
| 1057 | /* scaled size */ |
| 1058 | cfg = (GSC_SCALED_WIDTH(img_pos.w) | GSC_SCALED_HEIGHT(img_pos.h)); |
| 1059 | gsc_write(cfg, GSC_SCALED_SIZE); |
| 1060 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1061 | DRM_DEBUG_KMS("hsize[%d]vsize[%d]\n", sz->hsize, sz->vsize); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1062 | |
| 1063 | /* original size */ |
| 1064 | cfg = gsc_read(GSC_DSTIMG_SIZE); |
| 1065 | cfg &= ~(GSC_DSTIMG_HEIGHT_MASK | |
| 1066 | GSC_DSTIMG_WIDTH_MASK); |
| 1067 | cfg |= (GSC_DSTIMG_WIDTH(sz->hsize) | |
| 1068 | GSC_DSTIMG_HEIGHT(sz->vsize)); |
| 1069 | gsc_write(cfg, GSC_DSTIMG_SIZE); |
| 1070 | |
| 1071 | cfg = gsc_read(GSC_OUT_CON); |
| 1072 | cfg &= ~GSC_OUT_RGB_TYPE_MASK; |
| 1073 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1074 | DRM_DEBUG_KMS("width[%d]range[%d]\n", pos->w, sc->range); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1075 | |
| 1076 | if (pos->w >= GSC_WIDTH_ITU_709) |
| 1077 | if (sc->range) |
| 1078 | cfg |= GSC_OUT_RGB_HD_WIDE; |
| 1079 | else |
| 1080 | cfg |= GSC_OUT_RGB_HD_NARROW; |
| 1081 | else |
| 1082 | if (sc->range) |
| 1083 | cfg |= GSC_OUT_RGB_SD_WIDE; |
| 1084 | else |
| 1085 | cfg |= GSC_OUT_RGB_SD_NARROW; |
| 1086 | |
| 1087 | gsc_write(cfg, GSC_OUT_CON); |
| 1088 | |
| 1089 | return 0; |
| 1090 | } |
| 1091 | |
| 1092 | static int gsc_dst_get_buf_seq(struct gsc_context *ctx) |
| 1093 | { |
| 1094 | u32 cfg, i, buf_num = GSC_REG_SZ; |
| 1095 | u32 mask = 0x00000001; |
| 1096 | |
| 1097 | cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK); |
| 1098 | |
| 1099 | for (i = 0; i < GSC_REG_SZ; i++) |
| 1100 | if (cfg & (mask << i)) |
| 1101 | buf_num--; |
| 1102 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1103 | DRM_DEBUG_KMS("buf_num[%d]\n", buf_num); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1104 | |
| 1105 | return buf_num; |
| 1106 | } |
| 1107 | |
| 1108 | static int gsc_dst_set_buf_seq(struct gsc_context *ctx, u32 buf_id, |
| 1109 | enum drm_exynos_ipp_buf_type buf_type) |
| 1110 | { |
| 1111 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; |
| 1112 | bool masked; |
| 1113 | u32 cfg; |
| 1114 | u32 mask = 0x00000001 << buf_id; |
| 1115 | int ret = 0; |
| 1116 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1117 | DRM_DEBUG_KMS("buf_id[%d]buf_type[%d]\n", buf_id, buf_type); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1118 | |
| 1119 | mutex_lock(&ctx->lock); |
| 1120 | |
| 1121 | /* mask register set */ |
| 1122 | cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK); |
| 1123 | |
| 1124 | switch (buf_type) { |
| 1125 | case IPP_BUF_ENQUEUE: |
| 1126 | masked = false; |
| 1127 | break; |
| 1128 | case IPP_BUF_DEQUEUE: |
| 1129 | masked = true; |
| 1130 | break; |
| 1131 | default: |
| 1132 | dev_err(ippdrv->dev, "invalid buf ctrl parameter.\n"); |
| 1133 | ret = -EINVAL; |
| 1134 | goto err_unlock; |
| 1135 | } |
| 1136 | |
| 1137 | /* sequence id */ |
| 1138 | cfg &= ~mask; |
| 1139 | cfg |= masked << buf_id; |
| 1140 | gsc_write(cfg, GSC_OUT_BASE_ADDR_Y_MASK); |
| 1141 | gsc_write(cfg, GSC_OUT_BASE_ADDR_CB_MASK); |
| 1142 | gsc_write(cfg, GSC_OUT_BASE_ADDR_CR_MASK); |
| 1143 | |
| 1144 | /* interrupt enable */ |
| 1145 | if (buf_type == IPP_BUF_ENQUEUE && |
| 1146 | gsc_dst_get_buf_seq(ctx) >= GSC_BUF_START) |
| 1147 | gsc_handle_irq(ctx, true, false, true); |
| 1148 | |
| 1149 | /* interrupt disable */ |
| 1150 | if (buf_type == IPP_BUF_DEQUEUE && |
| 1151 | gsc_dst_get_buf_seq(ctx) <= GSC_BUF_STOP) |
| 1152 | gsc_handle_irq(ctx, false, false, true); |
| 1153 | |
| 1154 | err_unlock: |
| 1155 | mutex_unlock(&ctx->lock); |
| 1156 | return ret; |
| 1157 | } |
| 1158 | |
| 1159 | static int gsc_dst_set_addr(struct device *dev, |
| 1160 | struct drm_exynos_ipp_buf_info *buf_info, u32 buf_id, |
| 1161 | enum drm_exynos_ipp_buf_type buf_type) |
| 1162 | { |
| 1163 | struct gsc_context *ctx = get_gsc_context(dev); |
| 1164 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; |
Eunchul Kim | 7259c3d | 2012-12-22 17:49:22 +0900 | [diff] [blame] | 1165 | struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1166 | struct drm_exynos_ipp_property *property; |
| 1167 | |
| 1168 | if (!c_node) { |
| 1169 | DRM_ERROR("failed to get c_node.\n"); |
| 1170 | return -EFAULT; |
| 1171 | } |
| 1172 | |
| 1173 | property = &c_node->property; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1174 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1175 | DRM_DEBUG_KMS("prop_id[%d]buf_id[%d]buf_type[%d]\n", |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1176 | property->prop_id, buf_id, buf_type); |
| 1177 | |
| 1178 | if (buf_id > GSC_MAX_DST) { |
Ingi Kim | c691349 | 2015-10-02 17:59:26 +0900 | [diff] [blame] | 1179 | dev_info(ippdrv->dev, "invalid buf_id %d.\n", buf_id); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1180 | return -EINVAL; |
| 1181 | } |
| 1182 | |
| 1183 | /* address register set */ |
| 1184 | switch (buf_type) { |
| 1185 | case IPP_BUF_ENQUEUE: |
| 1186 | gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_Y], |
| 1187 | GSC_OUT_BASE_ADDR_Y(buf_id)); |
| 1188 | gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CB], |
| 1189 | GSC_OUT_BASE_ADDR_CB(buf_id)); |
| 1190 | gsc_write(buf_info->base[EXYNOS_DRM_PLANAR_CR], |
| 1191 | GSC_OUT_BASE_ADDR_CR(buf_id)); |
| 1192 | break; |
| 1193 | case IPP_BUF_DEQUEUE: |
| 1194 | gsc_write(0x0, GSC_OUT_BASE_ADDR_Y(buf_id)); |
| 1195 | gsc_write(0x0, GSC_OUT_BASE_ADDR_CB(buf_id)); |
| 1196 | gsc_write(0x0, GSC_OUT_BASE_ADDR_CR(buf_id)); |
| 1197 | break; |
| 1198 | default: |
| 1199 | /* bypass */ |
| 1200 | break; |
| 1201 | } |
| 1202 | |
| 1203 | return gsc_dst_set_buf_seq(ctx, buf_id, buf_type); |
| 1204 | } |
| 1205 | |
| 1206 | static struct exynos_drm_ipp_ops gsc_dst_ops = { |
| 1207 | .set_fmt = gsc_dst_set_fmt, |
| 1208 | .set_transf = gsc_dst_set_transf, |
| 1209 | .set_size = gsc_dst_set_size, |
| 1210 | .set_addr = gsc_dst_set_addr, |
| 1211 | }; |
| 1212 | |
| 1213 | static int gsc_clk_ctrl(struct gsc_context *ctx, bool enable) |
| 1214 | { |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1215 | DRM_DEBUG_KMS("enable[%d]\n", enable); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1216 | |
| 1217 | if (enable) { |
| 1218 | clk_enable(ctx->gsc_clk); |
| 1219 | ctx->suspended = false; |
| 1220 | } else { |
| 1221 | clk_disable(ctx->gsc_clk); |
| 1222 | ctx->suspended = true; |
| 1223 | } |
| 1224 | |
| 1225 | return 0; |
| 1226 | } |
| 1227 | |
| 1228 | static int gsc_get_src_buf_index(struct gsc_context *ctx) |
| 1229 | { |
| 1230 | u32 cfg, curr_index, i; |
| 1231 | u32 buf_id = GSC_MAX_SRC; |
| 1232 | int ret; |
| 1233 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1234 | DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1235 | |
| 1236 | cfg = gsc_read(GSC_IN_BASE_ADDR_Y_MASK); |
| 1237 | curr_index = GSC_IN_CURR_GET_INDEX(cfg); |
| 1238 | |
| 1239 | for (i = curr_index; i < GSC_MAX_SRC; i++) { |
| 1240 | if (!((cfg >> i) & 0x1)) { |
| 1241 | buf_id = i; |
| 1242 | break; |
| 1243 | } |
| 1244 | } |
| 1245 | |
| 1246 | if (buf_id == GSC_MAX_SRC) { |
| 1247 | DRM_ERROR("failed to get in buffer index.\n"); |
| 1248 | return -EINVAL; |
| 1249 | } |
| 1250 | |
| 1251 | ret = gsc_src_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE); |
| 1252 | if (ret < 0) { |
| 1253 | DRM_ERROR("failed to dequeue.\n"); |
| 1254 | return ret; |
| 1255 | } |
| 1256 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1257 | DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg, |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1258 | curr_index, buf_id); |
| 1259 | |
| 1260 | return buf_id; |
| 1261 | } |
| 1262 | |
| 1263 | static int gsc_get_dst_buf_index(struct gsc_context *ctx) |
| 1264 | { |
| 1265 | u32 cfg, curr_index, i; |
| 1266 | u32 buf_id = GSC_MAX_DST; |
| 1267 | int ret; |
| 1268 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1269 | DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1270 | |
| 1271 | cfg = gsc_read(GSC_OUT_BASE_ADDR_Y_MASK); |
| 1272 | curr_index = GSC_OUT_CURR_GET_INDEX(cfg); |
| 1273 | |
| 1274 | for (i = curr_index; i < GSC_MAX_DST; i++) { |
| 1275 | if (!((cfg >> i) & 0x1)) { |
| 1276 | buf_id = i; |
| 1277 | break; |
| 1278 | } |
| 1279 | } |
| 1280 | |
| 1281 | if (buf_id == GSC_MAX_DST) { |
| 1282 | DRM_ERROR("failed to get out buffer index.\n"); |
| 1283 | return -EINVAL; |
| 1284 | } |
| 1285 | |
| 1286 | ret = gsc_dst_set_buf_seq(ctx, buf_id, IPP_BUF_DEQUEUE); |
| 1287 | if (ret < 0) { |
| 1288 | DRM_ERROR("failed to dequeue.\n"); |
| 1289 | return ret; |
| 1290 | } |
| 1291 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1292 | DRM_DEBUG_KMS("cfg[0x%x]curr_index[%d]buf_id[%d]\n", cfg, |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1293 | curr_index, buf_id); |
| 1294 | |
| 1295 | return buf_id; |
| 1296 | } |
| 1297 | |
| 1298 | static irqreturn_t gsc_irq_handler(int irq, void *dev_id) |
| 1299 | { |
| 1300 | struct gsc_context *ctx = dev_id; |
| 1301 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; |
Eunchul Kim | 7259c3d | 2012-12-22 17:49:22 +0900 | [diff] [blame] | 1302 | struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1303 | struct drm_exynos_ipp_event_work *event_work = |
| 1304 | c_node->event_work; |
| 1305 | u32 status; |
| 1306 | int buf_id[EXYNOS_DRM_OPS_MAX]; |
| 1307 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1308 | DRM_DEBUG_KMS("gsc id[%d]\n", ctx->id); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1309 | |
| 1310 | status = gsc_read(GSC_IRQ); |
| 1311 | if (status & GSC_IRQ_STATUS_OR_IRQ) { |
Masanari Iida | 77d84ff | 2013-12-09 00:22:53 +0900 | [diff] [blame] | 1312 | dev_err(ippdrv->dev, "occurred overflow at %d, status 0x%x.\n", |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1313 | ctx->id, status); |
| 1314 | return IRQ_NONE; |
| 1315 | } |
| 1316 | |
| 1317 | if (status & GSC_IRQ_STATUS_OR_FRM_DONE) { |
Masanari Iida | 77d84ff | 2013-12-09 00:22:53 +0900 | [diff] [blame] | 1318 | dev_dbg(ippdrv->dev, "occurred frame done at %d, status 0x%x.\n", |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1319 | ctx->id, status); |
| 1320 | |
| 1321 | buf_id[EXYNOS_DRM_OPS_SRC] = gsc_get_src_buf_index(ctx); |
| 1322 | if (buf_id[EXYNOS_DRM_OPS_SRC] < 0) |
| 1323 | return IRQ_HANDLED; |
| 1324 | |
| 1325 | buf_id[EXYNOS_DRM_OPS_DST] = gsc_get_dst_buf_index(ctx); |
| 1326 | if (buf_id[EXYNOS_DRM_OPS_DST] < 0) |
| 1327 | return IRQ_HANDLED; |
| 1328 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1329 | DRM_DEBUG_KMS("buf_id_src[%d]buf_id_dst[%d]\n", |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1330 | buf_id[EXYNOS_DRM_OPS_SRC], buf_id[EXYNOS_DRM_OPS_DST]); |
| 1331 | |
| 1332 | event_work->ippdrv = ippdrv; |
| 1333 | event_work->buf_id[EXYNOS_DRM_OPS_SRC] = |
| 1334 | buf_id[EXYNOS_DRM_OPS_SRC]; |
| 1335 | event_work->buf_id[EXYNOS_DRM_OPS_DST] = |
| 1336 | buf_id[EXYNOS_DRM_OPS_DST]; |
Andrzej Hajda | 05afb1a | 2014-08-28 11:07:33 +0200 | [diff] [blame] | 1337 | queue_work(ippdrv->event_workq, &event_work->work); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1338 | } |
| 1339 | |
| 1340 | return IRQ_HANDLED; |
| 1341 | } |
| 1342 | |
| 1343 | static int gsc_init_prop_list(struct exynos_drm_ippdrv *ippdrv) |
| 1344 | { |
Andrzej Hajda | 3164605 | 2014-05-19 12:54:05 +0200 | [diff] [blame] | 1345 | struct drm_exynos_ipp_prop_list *prop_list = &ippdrv->prop_list; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1346 | |
| 1347 | prop_list->version = 1; |
| 1348 | prop_list->writeback = 1; |
| 1349 | prop_list->refresh_min = GSC_REFRESH_MIN; |
| 1350 | prop_list->refresh_max = GSC_REFRESH_MAX; |
| 1351 | prop_list->flip = (1 << EXYNOS_DRM_FLIP_VERTICAL) | |
| 1352 | (1 << EXYNOS_DRM_FLIP_HORIZONTAL); |
| 1353 | prop_list->degree = (1 << EXYNOS_DRM_DEGREE_0) | |
| 1354 | (1 << EXYNOS_DRM_DEGREE_90) | |
| 1355 | (1 << EXYNOS_DRM_DEGREE_180) | |
| 1356 | (1 << EXYNOS_DRM_DEGREE_270); |
| 1357 | prop_list->csc = 1; |
| 1358 | prop_list->crop = 1; |
| 1359 | prop_list->crop_max.hsize = GSC_CROP_MAX; |
| 1360 | prop_list->crop_max.vsize = GSC_CROP_MAX; |
| 1361 | prop_list->crop_min.hsize = GSC_CROP_MIN; |
| 1362 | prop_list->crop_min.vsize = GSC_CROP_MIN; |
| 1363 | prop_list->scale = 1; |
| 1364 | prop_list->scale_max.hsize = GSC_SCALE_MAX; |
| 1365 | prop_list->scale_max.vsize = GSC_SCALE_MAX; |
| 1366 | prop_list->scale_min.hsize = GSC_SCALE_MIN; |
| 1367 | prop_list->scale_min.vsize = GSC_SCALE_MIN; |
| 1368 | |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1369 | return 0; |
| 1370 | } |
| 1371 | |
| 1372 | static inline bool gsc_check_drm_flip(enum drm_exynos_flip flip) |
| 1373 | { |
| 1374 | switch (flip) { |
| 1375 | case EXYNOS_DRM_FLIP_NONE: |
| 1376 | case EXYNOS_DRM_FLIP_VERTICAL: |
| 1377 | case EXYNOS_DRM_FLIP_HORIZONTAL: |
Eunchul Kim | 4f21877 | 2012-12-22 17:49:24 +0900 | [diff] [blame] | 1378 | case EXYNOS_DRM_FLIP_BOTH: |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1379 | return true; |
| 1380 | default: |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1381 | DRM_DEBUG_KMS("invalid flip\n"); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1382 | return false; |
| 1383 | } |
| 1384 | } |
| 1385 | |
| 1386 | static int gsc_ippdrv_check_property(struct device *dev, |
| 1387 | struct drm_exynos_ipp_property *property) |
| 1388 | { |
| 1389 | struct gsc_context *ctx = get_gsc_context(dev); |
| 1390 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; |
Andrzej Hajda | 3164605 | 2014-05-19 12:54:05 +0200 | [diff] [blame] | 1391 | struct drm_exynos_ipp_prop_list *pp = &ippdrv->prop_list; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1392 | struct drm_exynos_ipp_config *config; |
| 1393 | struct drm_exynos_pos *pos; |
| 1394 | struct drm_exynos_sz *sz; |
| 1395 | bool swap; |
| 1396 | int i; |
| 1397 | |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1398 | for_each_ipp_ops(i) { |
| 1399 | if ((i == EXYNOS_DRM_OPS_SRC) && |
| 1400 | (property->cmd == IPP_CMD_WB)) |
| 1401 | continue; |
| 1402 | |
| 1403 | config = &property->config[i]; |
| 1404 | pos = &config->pos; |
| 1405 | sz = &config->sz; |
| 1406 | |
| 1407 | /* check for flip */ |
| 1408 | if (!gsc_check_drm_flip(config->flip)) { |
| 1409 | DRM_ERROR("invalid flip.\n"); |
| 1410 | goto err_property; |
| 1411 | } |
| 1412 | |
| 1413 | /* check for degree */ |
| 1414 | switch (config->degree) { |
| 1415 | case EXYNOS_DRM_DEGREE_90: |
| 1416 | case EXYNOS_DRM_DEGREE_270: |
| 1417 | swap = true; |
| 1418 | break; |
| 1419 | case EXYNOS_DRM_DEGREE_0: |
| 1420 | case EXYNOS_DRM_DEGREE_180: |
| 1421 | swap = false; |
| 1422 | break; |
| 1423 | default: |
| 1424 | DRM_ERROR("invalid degree.\n"); |
| 1425 | goto err_property; |
| 1426 | } |
| 1427 | |
| 1428 | /* check for buffer bound */ |
| 1429 | if ((pos->x + pos->w > sz->hsize) || |
| 1430 | (pos->y + pos->h > sz->vsize)) { |
| 1431 | DRM_ERROR("out of buf bound.\n"); |
| 1432 | goto err_property; |
| 1433 | } |
| 1434 | |
| 1435 | /* check for crop */ |
| 1436 | if ((i == EXYNOS_DRM_OPS_SRC) && (pp->crop)) { |
| 1437 | if (swap) { |
| 1438 | if ((pos->h < pp->crop_min.hsize) || |
| 1439 | (sz->vsize > pp->crop_max.hsize) || |
| 1440 | (pos->w < pp->crop_min.vsize) || |
| 1441 | (sz->hsize > pp->crop_max.vsize)) { |
| 1442 | DRM_ERROR("out of crop size.\n"); |
| 1443 | goto err_property; |
| 1444 | } |
| 1445 | } else { |
| 1446 | if ((pos->w < pp->crop_min.hsize) || |
| 1447 | (sz->hsize > pp->crop_max.hsize) || |
| 1448 | (pos->h < pp->crop_min.vsize) || |
| 1449 | (sz->vsize > pp->crop_max.vsize)) { |
| 1450 | DRM_ERROR("out of crop size.\n"); |
| 1451 | goto err_property; |
| 1452 | } |
| 1453 | } |
| 1454 | } |
| 1455 | |
| 1456 | /* check for scale */ |
| 1457 | if ((i == EXYNOS_DRM_OPS_DST) && (pp->scale)) { |
| 1458 | if (swap) { |
| 1459 | if ((pos->h < pp->scale_min.hsize) || |
| 1460 | (sz->vsize > pp->scale_max.hsize) || |
| 1461 | (pos->w < pp->scale_min.vsize) || |
| 1462 | (sz->hsize > pp->scale_max.vsize)) { |
| 1463 | DRM_ERROR("out of scale size.\n"); |
| 1464 | goto err_property; |
| 1465 | } |
| 1466 | } else { |
| 1467 | if ((pos->w < pp->scale_min.hsize) || |
| 1468 | (sz->hsize > pp->scale_max.hsize) || |
| 1469 | (pos->h < pp->scale_min.vsize) || |
| 1470 | (sz->vsize > pp->scale_max.vsize)) { |
| 1471 | DRM_ERROR("out of scale size.\n"); |
| 1472 | goto err_property; |
| 1473 | } |
| 1474 | } |
| 1475 | } |
| 1476 | } |
| 1477 | |
| 1478 | return 0; |
| 1479 | |
| 1480 | err_property: |
| 1481 | for_each_ipp_ops(i) { |
| 1482 | if ((i == EXYNOS_DRM_OPS_SRC) && |
| 1483 | (property->cmd == IPP_CMD_WB)) |
| 1484 | continue; |
| 1485 | |
| 1486 | config = &property->config[i]; |
| 1487 | pos = &config->pos; |
| 1488 | sz = &config->sz; |
| 1489 | |
| 1490 | DRM_ERROR("[%s]f[%d]r[%d]pos[%d %d %d %d]sz[%d %d]\n", |
| 1491 | i ? "dst" : "src", config->flip, config->degree, |
| 1492 | pos->x, pos->y, pos->w, pos->h, |
| 1493 | sz->hsize, sz->vsize); |
| 1494 | } |
| 1495 | |
| 1496 | return -EINVAL; |
| 1497 | } |
| 1498 | |
| 1499 | |
| 1500 | static int gsc_ippdrv_reset(struct device *dev) |
| 1501 | { |
| 1502 | struct gsc_context *ctx = get_gsc_context(dev); |
| 1503 | struct gsc_scaler *sc = &ctx->sc; |
| 1504 | int ret; |
| 1505 | |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1506 | /* reset h/w block */ |
| 1507 | ret = gsc_sw_reset(ctx); |
| 1508 | if (ret < 0) { |
| 1509 | dev_err(dev, "failed to reset hardware.\n"); |
| 1510 | return ret; |
| 1511 | } |
| 1512 | |
| 1513 | /* scaler setting */ |
| 1514 | memset(&ctx->sc, 0x0, sizeof(ctx->sc)); |
| 1515 | sc->range = true; |
| 1516 | |
| 1517 | return 0; |
| 1518 | } |
| 1519 | |
| 1520 | static int gsc_ippdrv_start(struct device *dev, enum drm_exynos_ipp_cmd cmd) |
| 1521 | { |
| 1522 | struct gsc_context *ctx = get_gsc_context(dev); |
| 1523 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; |
Eunchul Kim | 7259c3d | 2012-12-22 17:49:22 +0900 | [diff] [blame] | 1524 | struct drm_exynos_ipp_cmd_node *c_node = ippdrv->c_node; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1525 | struct drm_exynos_ipp_property *property; |
| 1526 | struct drm_exynos_ipp_config *config; |
| 1527 | struct drm_exynos_pos img_pos[EXYNOS_DRM_OPS_MAX]; |
| 1528 | struct drm_exynos_ipp_set_wb set_wb; |
| 1529 | u32 cfg; |
| 1530 | int ret, i; |
| 1531 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1532 | DRM_DEBUG_KMS("cmd[%d]\n", cmd); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1533 | |
| 1534 | if (!c_node) { |
| 1535 | DRM_ERROR("failed to get c_node.\n"); |
| 1536 | return -EINVAL; |
| 1537 | } |
| 1538 | |
| 1539 | property = &c_node->property; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1540 | |
| 1541 | gsc_handle_irq(ctx, true, false, true); |
| 1542 | |
| 1543 | for_each_ipp_ops(i) { |
| 1544 | config = &property->config[i]; |
| 1545 | img_pos[i] = config->pos; |
| 1546 | } |
| 1547 | |
| 1548 | switch (cmd) { |
| 1549 | case IPP_CMD_M2M: |
| 1550 | /* enable one shot */ |
| 1551 | cfg = gsc_read(GSC_ENABLE); |
| 1552 | cfg &= ~(GSC_ENABLE_ON_CLEAR_MASK | |
| 1553 | GSC_ENABLE_CLK_GATE_MODE_MASK); |
| 1554 | cfg |= GSC_ENABLE_ON_CLEAR_ONESHOT; |
| 1555 | gsc_write(cfg, GSC_ENABLE); |
| 1556 | |
| 1557 | /* src dma memory */ |
| 1558 | cfg = gsc_read(GSC_IN_CON); |
| 1559 | cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK); |
| 1560 | cfg |= GSC_IN_PATH_MEMORY; |
| 1561 | gsc_write(cfg, GSC_IN_CON); |
| 1562 | |
| 1563 | /* dst dma memory */ |
| 1564 | cfg = gsc_read(GSC_OUT_CON); |
| 1565 | cfg |= GSC_OUT_PATH_MEMORY; |
| 1566 | gsc_write(cfg, GSC_OUT_CON); |
| 1567 | break; |
| 1568 | case IPP_CMD_WB: |
| 1569 | set_wb.enable = 1; |
| 1570 | set_wb.refresh = property->refresh_rate; |
| 1571 | gsc_set_gscblk_fimd_wb(ctx, set_wb.enable); |
| 1572 | exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb); |
| 1573 | |
| 1574 | /* src local path */ |
Eunchul Kim | 5bbea0c | 2012-12-22 17:49:25 +0900 | [diff] [blame] | 1575 | cfg = gsc_read(GSC_IN_CON); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1576 | cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK); |
| 1577 | cfg |= (GSC_IN_PATH_LOCAL | GSC_IN_LOCAL_FIMD_WB); |
| 1578 | gsc_write(cfg, GSC_IN_CON); |
| 1579 | |
| 1580 | /* dst dma memory */ |
| 1581 | cfg = gsc_read(GSC_OUT_CON); |
| 1582 | cfg |= GSC_OUT_PATH_MEMORY; |
| 1583 | gsc_write(cfg, GSC_OUT_CON); |
| 1584 | break; |
| 1585 | case IPP_CMD_OUTPUT: |
| 1586 | /* src dma memory */ |
| 1587 | cfg = gsc_read(GSC_IN_CON); |
| 1588 | cfg &= ~(GSC_IN_PATH_MASK | GSC_IN_LOCAL_SEL_MASK); |
| 1589 | cfg |= GSC_IN_PATH_MEMORY; |
| 1590 | gsc_write(cfg, GSC_IN_CON); |
| 1591 | |
| 1592 | /* dst local path */ |
| 1593 | cfg = gsc_read(GSC_OUT_CON); |
| 1594 | cfg |= GSC_OUT_PATH_MEMORY; |
| 1595 | gsc_write(cfg, GSC_OUT_CON); |
| 1596 | break; |
| 1597 | default: |
| 1598 | ret = -EINVAL; |
| 1599 | dev_err(dev, "invalid operations.\n"); |
| 1600 | return ret; |
| 1601 | } |
| 1602 | |
| 1603 | ret = gsc_set_prescaler(ctx, &ctx->sc, |
| 1604 | &img_pos[EXYNOS_DRM_OPS_SRC], |
| 1605 | &img_pos[EXYNOS_DRM_OPS_DST]); |
| 1606 | if (ret) { |
| 1607 | dev_err(dev, "failed to set precalser.\n"); |
| 1608 | return ret; |
| 1609 | } |
| 1610 | |
| 1611 | gsc_set_scaler(ctx, &ctx->sc); |
| 1612 | |
| 1613 | cfg = gsc_read(GSC_ENABLE); |
| 1614 | cfg |= GSC_ENABLE_ON; |
| 1615 | gsc_write(cfg, GSC_ENABLE); |
| 1616 | |
| 1617 | return 0; |
| 1618 | } |
| 1619 | |
| 1620 | static void gsc_ippdrv_stop(struct device *dev, enum drm_exynos_ipp_cmd cmd) |
| 1621 | { |
| 1622 | struct gsc_context *ctx = get_gsc_context(dev); |
| 1623 | struct drm_exynos_ipp_set_wb set_wb = {0, 0}; |
| 1624 | u32 cfg; |
| 1625 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1626 | DRM_DEBUG_KMS("cmd[%d]\n", cmd); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1627 | |
| 1628 | switch (cmd) { |
| 1629 | case IPP_CMD_M2M: |
| 1630 | /* bypass */ |
| 1631 | break; |
| 1632 | case IPP_CMD_WB: |
| 1633 | gsc_set_gscblk_fimd_wb(ctx, set_wb.enable); |
| 1634 | exynos_drm_ippnb_send_event(IPP_SET_WRITEBACK, (void *)&set_wb); |
| 1635 | break; |
| 1636 | case IPP_CMD_OUTPUT: |
| 1637 | default: |
| 1638 | dev_err(dev, "invalid operations.\n"); |
| 1639 | break; |
| 1640 | } |
| 1641 | |
| 1642 | gsc_handle_irq(ctx, false, false, true); |
| 1643 | |
| 1644 | /* reset sequence */ |
| 1645 | gsc_write(0xff, GSC_OUT_BASE_ADDR_Y_MASK); |
| 1646 | gsc_write(0xff, GSC_OUT_BASE_ADDR_CB_MASK); |
| 1647 | gsc_write(0xff, GSC_OUT_BASE_ADDR_CR_MASK); |
| 1648 | |
| 1649 | cfg = gsc_read(GSC_ENABLE); |
| 1650 | cfg &= ~GSC_ENABLE_ON; |
| 1651 | gsc_write(cfg, GSC_ENABLE); |
| 1652 | } |
| 1653 | |
Greg Kroah-Hartman | 56550d9 | 2012-12-21 15:09:25 -0800 | [diff] [blame] | 1654 | static int gsc_probe(struct platform_device *pdev) |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1655 | { |
| 1656 | struct device *dev = &pdev->dev; |
| 1657 | struct gsc_context *ctx; |
| 1658 | struct resource *res; |
| 1659 | struct exynos_drm_ippdrv *ippdrv; |
| 1660 | int ret; |
| 1661 | |
| 1662 | ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); |
| 1663 | if (!ctx) |
| 1664 | return -ENOMEM; |
| 1665 | |
| 1666 | /* clock control */ |
Sachin Kamat | 5cbd419 | 2012-12-24 14:03:51 +0530 | [diff] [blame] | 1667 | ctx->gsc_clk = devm_clk_get(dev, "gscl"); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1668 | if (IS_ERR(ctx->gsc_clk)) { |
| 1669 | dev_err(dev, "failed to get gsc clock.\n"); |
Sachin Kamat | cfdee8f | 2012-12-24 14:03:49 +0530 | [diff] [blame] | 1670 | return PTR_ERR(ctx->gsc_clk); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1671 | } |
| 1672 | |
| 1673 | /* resource memory */ |
| 1674 | ctx->regs_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
Thierry Reding | d4ed602 | 2013-01-21 11:09:02 +0100 | [diff] [blame] | 1675 | ctx->regs = devm_ioremap_resource(dev, ctx->regs_res); |
| 1676 | if (IS_ERR(ctx->regs)) |
| 1677 | return PTR_ERR(ctx->regs); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1678 | |
| 1679 | /* resource irq */ |
| 1680 | res = platform_get_resource(pdev, IORESOURCE_IRQ, 0); |
| 1681 | if (!res) { |
| 1682 | dev_err(dev, "failed to request irq resource.\n"); |
Sachin Kamat | 5cbd419 | 2012-12-24 14:03:51 +0530 | [diff] [blame] | 1683 | return -ENOENT; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1684 | } |
| 1685 | |
| 1686 | ctx->irq = res->start; |
Seung-Woo Kim | dcb9a7c | 2013-05-22 21:14:17 +0900 | [diff] [blame] | 1687 | ret = devm_request_threaded_irq(dev, ctx->irq, NULL, gsc_irq_handler, |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1688 | IRQF_ONESHOT, "drm_gsc", ctx); |
| 1689 | if (ret < 0) { |
| 1690 | dev_err(dev, "failed to request irq.\n"); |
Sachin Kamat | 5cbd419 | 2012-12-24 14:03:51 +0530 | [diff] [blame] | 1691 | return ret; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1692 | } |
| 1693 | |
| 1694 | /* context initailization */ |
| 1695 | ctx->id = pdev->id; |
| 1696 | |
| 1697 | ippdrv = &ctx->ippdrv; |
| 1698 | ippdrv->dev = dev; |
| 1699 | ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &gsc_src_ops; |
| 1700 | ippdrv->ops[EXYNOS_DRM_OPS_DST] = &gsc_dst_ops; |
| 1701 | ippdrv->check_property = gsc_ippdrv_check_property; |
| 1702 | ippdrv->reset = gsc_ippdrv_reset; |
| 1703 | ippdrv->start = gsc_ippdrv_start; |
| 1704 | ippdrv->stop = gsc_ippdrv_stop; |
| 1705 | ret = gsc_init_prop_list(ippdrv); |
| 1706 | if (ret < 0) { |
| 1707 | dev_err(dev, "failed to init property list.\n"); |
Seung-Woo Kim | dcb9a7c | 2013-05-22 21:14:17 +0900 | [diff] [blame] | 1708 | return ret; |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1709 | } |
| 1710 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1711 | DRM_DEBUG_KMS("id[%d]ippdrv[0x%x]\n", ctx->id, (int)ippdrv); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1712 | |
| 1713 | mutex_init(&ctx->lock); |
| 1714 | platform_set_drvdata(pdev, ctx); |
| 1715 | |
| 1716 | pm_runtime_set_active(dev); |
| 1717 | pm_runtime_enable(dev); |
| 1718 | |
| 1719 | ret = exynos_drm_ippdrv_register(ippdrv); |
| 1720 | if (ret < 0) { |
| 1721 | dev_err(dev, "failed to register drm gsc device.\n"); |
| 1722 | goto err_ippdrv_register; |
| 1723 | } |
| 1724 | |
Seung-Woo Kim | d873ab9 | 2013-05-22 21:14:14 +0900 | [diff] [blame] | 1725 | dev_info(dev, "drm gsc registered successfully.\n"); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1726 | |
| 1727 | return 0; |
| 1728 | |
| 1729 | err_ippdrv_register: |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1730 | pm_runtime_disable(dev); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1731 | return ret; |
| 1732 | } |
| 1733 | |
Greg Kroah-Hartman | 56550d9 | 2012-12-21 15:09:25 -0800 | [diff] [blame] | 1734 | static int gsc_remove(struct platform_device *pdev) |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1735 | { |
| 1736 | struct device *dev = &pdev->dev; |
| 1737 | struct gsc_context *ctx = get_gsc_context(dev); |
| 1738 | struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv; |
| 1739 | |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1740 | exynos_drm_ippdrv_unregister(ippdrv); |
| 1741 | mutex_destroy(&ctx->lock); |
| 1742 | |
| 1743 | pm_runtime_set_suspended(dev); |
| 1744 | pm_runtime_disable(dev); |
| 1745 | |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1746 | return 0; |
| 1747 | } |
| 1748 | |
| 1749 | #ifdef CONFIG_PM_SLEEP |
| 1750 | static int gsc_suspend(struct device *dev) |
| 1751 | { |
| 1752 | struct gsc_context *ctx = get_gsc_context(dev); |
| 1753 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1754 | DRM_DEBUG_KMS("id[%d]\n", ctx->id); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1755 | |
| 1756 | if (pm_runtime_suspended(dev)) |
| 1757 | return 0; |
| 1758 | |
| 1759 | return gsc_clk_ctrl(ctx, false); |
| 1760 | } |
| 1761 | |
| 1762 | static int gsc_resume(struct device *dev) |
| 1763 | { |
| 1764 | struct gsc_context *ctx = get_gsc_context(dev); |
| 1765 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1766 | DRM_DEBUG_KMS("id[%d]\n", ctx->id); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1767 | |
| 1768 | if (!pm_runtime_suspended(dev)) |
| 1769 | return gsc_clk_ctrl(ctx, true); |
| 1770 | |
| 1771 | return 0; |
| 1772 | } |
| 1773 | #endif |
| 1774 | |
Rafael J. Wysocki | 06453ed | 2014-12-04 01:04:55 +0100 | [diff] [blame] | 1775 | #ifdef CONFIG_PM |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1776 | static int gsc_runtime_suspend(struct device *dev) |
| 1777 | { |
| 1778 | struct gsc_context *ctx = get_gsc_context(dev); |
| 1779 | |
YoungJun Cho | cbc4c33 | 2013-06-12 10:44:40 +0900 | [diff] [blame] | 1780 | DRM_DEBUG_KMS("id[%d]\n", ctx->id); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1781 | |
| 1782 | return gsc_clk_ctrl(ctx, false); |
| 1783 | } |
| 1784 | |
| 1785 | static int gsc_runtime_resume(struct device *dev) |
| 1786 | { |
| 1787 | struct gsc_context *ctx = get_gsc_context(dev); |
| 1788 | |
YoungJun Cho | bca34c9 | 2013-06-12 10:40:52 +0900 | [diff] [blame] | 1789 | DRM_DEBUG_KMS("id[%d]\n", ctx->id); |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1790 | |
| 1791 | return gsc_clk_ctrl(ctx, true); |
| 1792 | } |
| 1793 | #endif |
| 1794 | |
| 1795 | static const struct dev_pm_ops gsc_pm_ops = { |
| 1796 | SET_SYSTEM_SLEEP_PM_OPS(gsc_suspend, gsc_resume) |
| 1797 | SET_RUNTIME_PM_OPS(gsc_runtime_suspend, gsc_runtime_resume, NULL) |
| 1798 | }; |
| 1799 | |
| 1800 | struct platform_driver gsc_driver = { |
| 1801 | .probe = gsc_probe, |
Greg Kroah-Hartman | 56550d9 | 2012-12-21 15:09:25 -0800 | [diff] [blame] | 1802 | .remove = gsc_remove, |
Eunchul Kim | f264638 | 2012-12-14 17:58:57 +0900 | [diff] [blame] | 1803 | .driver = { |
| 1804 | .name = "exynos-drm-gsc", |
| 1805 | .owner = THIS_MODULE, |
| 1806 | .pm = &gsc_pm_ops, |
| 1807 | }, |
| 1808 | }; |
| 1809 | |