stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1 | /* |
| 2 | * drivers/net/ethernet/nxp/lpc_eth.c |
| 3 | * |
| 4 | * Author: Kevin Wells <kevin.wells@nxp.com> |
| 5 | * |
| 6 | * Copyright (C) 2010 NXP Semiconductors |
| 7 | * Copyright (C) 2012 Roland Stigge <stigge@antcom.de> |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as published by |
| 11 | * the Free Software Foundation; either version 2 of the License, or |
| 12 | * (at your option) any later version. |
| 13 | * |
| 14 | * This program is distributed in the hope that it will be useful, |
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 17 | * GNU General Public License for more details. |
| 18 | */ |
| 19 | |
| 20 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
| 21 | |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 22 | #include <linux/module.h> |
| 23 | #include <linux/kernel.h> |
| 24 | #include <linux/sched.h> |
| 25 | #include <linux/slab.h> |
| 26 | #include <linux/delay.h> |
| 27 | #include <linux/interrupt.h> |
| 28 | #include <linux/errno.h> |
| 29 | #include <linux/ioport.h> |
| 30 | #include <linux/crc32.h> |
| 31 | #include <linux/platform_device.h> |
| 32 | #include <linux/spinlock.h> |
| 33 | #include <linux/ethtool.h> |
| 34 | #include <linux/mii.h> |
| 35 | #include <linux/clk.h> |
| 36 | #include <linux/workqueue.h> |
| 37 | #include <linux/netdevice.h> |
| 38 | #include <linux/etherdevice.h> |
| 39 | #include <linux/skbuff.h> |
| 40 | #include <linux/phy.h> |
| 41 | #include <linux/dma-mapping.h> |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 42 | #include <linux/of.h> |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 43 | #include <linux/of_net.h> |
| 44 | #include <linux/types.h> |
| 45 | |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 46 | #include <linux/io.h> |
| 47 | #include <mach/board.h> |
| 48 | #include <mach/platform.h> |
| 49 | #include <mach/hardware.h> |
| 50 | |
| 51 | #define MODNAME "lpc-eth" |
| 52 | #define DRV_VERSION "1.00" |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 53 | |
| 54 | #define ENET_MAXF_SIZE 1536 |
| 55 | #define ENET_RX_DESC 48 |
| 56 | #define ENET_TX_DESC 16 |
| 57 | |
| 58 | #define NAPI_WEIGHT 16 |
| 59 | |
| 60 | /* |
| 61 | * Ethernet MAC controller Register offsets |
| 62 | */ |
| 63 | #define LPC_ENET_MAC1(x) (x + 0x000) |
| 64 | #define LPC_ENET_MAC2(x) (x + 0x004) |
| 65 | #define LPC_ENET_IPGT(x) (x + 0x008) |
| 66 | #define LPC_ENET_IPGR(x) (x + 0x00C) |
| 67 | #define LPC_ENET_CLRT(x) (x + 0x010) |
| 68 | #define LPC_ENET_MAXF(x) (x + 0x014) |
| 69 | #define LPC_ENET_SUPP(x) (x + 0x018) |
| 70 | #define LPC_ENET_TEST(x) (x + 0x01C) |
| 71 | #define LPC_ENET_MCFG(x) (x + 0x020) |
| 72 | #define LPC_ENET_MCMD(x) (x + 0x024) |
| 73 | #define LPC_ENET_MADR(x) (x + 0x028) |
| 74 | #define LPC_ENET_MWTD(x) (x + 0x02C) |
| 75 | #define LPC_ENET_MRDD(x) (x + 0x030) |
| 76 | #define LPC_ENET_MIND(x) (x + 0x034) |
| 77 | #define LPC_ENET_SA0(x) (x + 0x040) |
| 78 | #define LPC_ENET_SA1(x) (x + 0x044) |
| 79 | #define LPC_ENET_SA2(x) (x + 0x048) |
| 80 | #define LPC_ENET_COMMAND(x) (x + 0x100) |
| 81 | #define LPC_ENET_STATUS(x) (x + 0x104) |
| 82 | #define LPC_ENET_RXDESCRIPTOR(x) (x + 0x108) |
| 83 | #define LPC_ENET_RXSTATUS(x) (x + 0x10C) |
| 84 | #define LPC_ENET_RXDESCRIPTORNUMBER(x) (x + 0x110) |
| 85 | #define LPC_ENET_RXPRODUCEINDEX(x) (x + 0x114) |
| 86 | #define LPC_ENET_RXCONSUMEINDEX(x) (x + 0x118) |
| 87 | #define LPC_ENET_TXDESCRIPTOR(x) (x + 0x11C) |
| 88 | #define LPC_ENET_TXSTATUS(x) (x + 0x120) |
| 89 | #define LPC_ENET_TXDESCRIPTORNUMBER(x) (x + 0x124) |
| 90 | #define LPC_ENET_TXPRODUCEINDEX(x) (x + 0x128) |
| 91 | #define LPC_ENET_TXCONSUMEINDEX(x) (x + 0x12C) |
| 92 | #define LPC_ENET_TSV0(x) (x + 0x158) |
| 93 | #define LPC_ENET_TSV1(x) (x + 0x15C) |
| 94 | #define LPC_ENET_RSV(x) (x + 0x160) |
| 95 | #define LPC_ENET_FLOWCONTROLCOUNTER(x) (x + 0x170) |
| 96 | #define LPC_ENET_FLOWCONTROLSTATUS(x) (x + 0x174) |
| 97 | #define LPC_ENET_RXFILTER_CTRL(x) (x + 0x200) |
| 98 | #define LPC_ENET_RXFILTERWOLSTATUS(x) (x + 0x204) |
| 99 | #define LPC_ENET_RXFILTERWOLCLEAR(x) (x + 0x208) |
| 100 | #define LPC_ENET_HASHFILTERL(x) (x + 0x210) |
| 101 | #define LPC_ENET_HASHFILTERH(x) (x + 0x214) |
| 102 | #define LPC_ENET_INTSTATUS(x) (x + 0xFE0) |
| 103 | #define LPC_ENET_INTENABLE(x) (x + 0xFE4) |
| 104 | #define LPC_ENET_INTCLEAR(x) (x + 0xFE8) |
| 105 | #define LPC_ENET_INTSET(x) (x + 0xFEC) |
| 106 | #define LPC_ENET_POWERDOWN(x) (x + 0xFF4) |
| 107 | |
| 108 | /* |
| 109 | * mac1 register definitions |
| 110 | */ |
| 111 | #define LPC_MAC1_RECV_ENABLE (1 << 0) |
| 112 | #define LPC_MAC1_PASS_ALL_RX_FRAMES (1 << 1) |
| 113 | #define LPC_MAC1_RX_FLOW_CONTROL (1 << 2) |
| 114 | #define LPC_MAC1_TX_FLOW_CONTROL (1 << 3) |
| 115 | #define LPC_MAC1_LOOPBACK (1 << 4) |
| 116 | #define LPC_MAC1_RESET_TX (1 << 8) |
| 117 | #define LPC_MAC1_RESET_MCS_TX (1 << 9) |
| 118 | #define LPC_MAC1_RESET_RX (1 << 10) |
| 119 | #define LPC_MAC1_RESET_MCS_RX (1 << 11) |
| 120 | #define LPC_MAC1_SIMULATION_RESET (1 << 14) |
| 121 | #define LPC_MAC1_SOFT_RESET (1 << 15) |
| 122 | |
| 123 | /* |
| 124 | * mac2 register definitions |
| 125 | */ |
| 126 | #define LPC_MAC2_FULL_DUPLEX (1 << 0) |
| 127 | #define LPC_MAC2_FRAME_LENGTH_CHECKING (1 << 1) |
| 128 | #define LPC_MAC2_HUGH_LENGTH_CHECKING (1 << 2) |
| 129 | #define LPC_MAC2_DELAYED_CRC (1 << 3) |
| 130 | #define LPC_MAC2_CRC_ENABLE (1 << 4) |
| 131 | #define LPC_MAC2_PAD_CRC_ENABLE (1 << 5) |
| 132 | #define LPC_MAC2_VLAN_PAD_ENABLE (1 << 6) |
| 133 | #define LPC_MAC2_AUTO_DETECT_PAD_ENABLE (1 << 7) |
| 134 | #define LPC_MAC2_PURE_PREAMBLE_ENFORCEMENT (1 << 8) |
| 135 | #define LPC_MAC2_LONG_PREAMBLE_ENFORCEMENT (1 << 9) |
| 136 | #define LPC_MAC2_NO_BACKOFF (1 << 12) |
| 137 | #define LPC_MAC2_BACK_PRESSURE (1 << 13) |
| 138 | #define LPC_MAC2_EXCESS_DEFER (1 << 14) |
| 139 | |
| 140 | /* |
| 141 | * ipgt register definitions |
| 142 | */ |
| 143 | #define LPC_IPGT_LOAD(n) ((n) & 0x7F) |
| 144 | |
| 145 | /* |
| 146 | * ipgr register definitions |
| 147 | */ |
| 148 | #define LPC_IPGR_LOAD_PART2(n) ((n) & 0x7F) |
| 149 | #define LPC_IPGR_LOAD_PART1(n) (((n) & 0x7F) << 8) |
| 150 | |
| 151 | /* |
| 152 | * clrt register definitions |
| 153 | */ |
| 154 | #define LPC_CLRT_LOAD_RETRY_MAX(n) ((n) & 0xF) |
| 155 | #define LPC_CLRT_LOAD_COLLISION_WINDOW(n) (((n) & 0x3F) << 8) |
| 156 | |
| 157 | /* |
| 158 | * maxf register definitions |
| 159 | */ |
| 160 | #define LPC_MAXF_LOAD_MAX_FRAME_LEN(n) ((n) & 0xFFFF) |
| 161 | |
| 162 | /* |
| 163 | * supp register definitions |
| 164 | */ |
| 165 | #define LPC_SUPP_SPEED (1 << 8) |
| 166 | #define LPC_SUPP_RESET_RMII (1 << 11) |
| 167 | |
| 168 | /* |
| 169 | * test register definitions |
| 170 | */ |
| 171 | #define LPC_TEST_SHORTCUT_PAUSE_QUANTA (1 << 0) |
| 172 | #define LPC_TEST_PAUSE (1 << 1) |
| 173 | #define LPC_TEST_BACKPRESSURE (1 << 2) |
| 174 | |
| 175 | /* |
| 176 | * mcfg register definitions |
| 177 | */ |
| 178 | #define LPC_MCFG_SCAN_INCREMENT (1 << 0) |
| 179 | #define LPC_MCFG_SUPPRESS_PREAMBLE (1 << 1) |
| 180 | #define LPC_MCFG_CLOCK_SELECT(n) (((n) & 0x7) << 2) |
| 181 | #define LPC_MCFG_CLOCK_HOST_DIV_4 0 |
| 182 | #define LPC_MCFG_CLOCK_HOST_DIV_6 2 |
| 183 | #define LPC_MCFG_CLOCK_HOST_DIV_8 3 |
| 184 | #define LPC_MCFG_CLOCK_HOST_DIV_10 4 |
| 185 | #define LPC_MCFG_CLOCK_HOST_DIV_14 5 |
| 186 | #define LPC_MCFG_CLOCK_HOST_DIV_20 6 |
| 187 | #define LPC_MCFG_CLOCK_HOST_DIV_28 7 |
| 188 | #define LPC_MCFG_RESET_MII_MGMT (1 << 15) |
| 189 | |
| 190 | /* |
| 191 | * mcmd register definitions |
| 192 | */ |
| 193 | #define LPC_MCMD_READ (1 << 0) |
| 194 | #define LPC_MCMD_SCAN (1 << 1) |
| 195 | |
| 196 | /* |
| 197 | * madr register definitions |
| 198 | */ |
| 199 | #define LPC_MADR_REGISTER_ADDRESS(n) ((n) & 0x1F) |
| 200 | #define LPC_MADR_PHY_0ADDRESS(n) (((n) & 0x1F) << 8) |
| 201 | |
| 202 | /* |
| 203 | * mwtd register definitions |
| 204 | */ |
| 205 | #define LPC_MWDT_WRITE(n) ((n) & 0xFFFF) |
| 206 | |
| 207 | /* |
| 208 | * mrdd register definitions |
| 209 | */ |
| 210 | #define LPC_MRDD_READ_MASK 0xFFFF |
| 211 | |
| 212 | /* |
| 213 | * mind register definitions |
| 214 | */ |
| 215 | #define LPC_MIND_BUSY (1 << 0) |
| 216 | #define LPC_MIND_SCANNING (1 << 1) |
| 217 | #define LPC_MIND_NOT_VALID (1 << 2) |
| 218 | #define LPC_MIND_MII_LINK_FAIL (1 << 3) |
| 219 | |
| 220 | /* |
| 221 | * command register definitions |
| 222 | */ |
| 223 | #define LPC_COMMAND_RXENABLE (1 << 0) |
| 224 | #define LPC_COMMAND_TXENABLE (1 << 1) |
| 225 | #define LPC_COMMAND_REG_RESET (1 << 3) |
| 226 | #define LPC_COMMAND_TXRESET (1 << 4) |
| 227 | #define LPC_COMMAND_RXRESET (1 << 5) |
| 228 | #define LPC_COMMAND_PASSRUNTFRAME (1 << 6) |
| 229 | #define LPC_COMMAND_PASSRXFILTER (1 << 7) |
| 230 | #define LPC_COMMAND_TXFLOWCONTROL (1 << 8) |
| 231 | #define LPC_COMMAND_RMII (1 << 9) |
| 232 | #define LPC_COMMAND_FULLDUPLEX (1 << 10) |
| 233 | |
| 234 | /* |
| 235 | * status register definitions |
| 236 | */ |
| 237 | #define LPC_STATUS_RXACTIVE (1 << 0) |
| 238 | #define LPC_STATUS_TXACTIVE (1 << 1) |
| 239 | |
| 240 | /* |
| 241 | * tsv0 register definitions |
| 242 | */ |
| 243 | #define LPC_TSV0_CRC_ERROR (1 << 0) |
| 244 | #define LPC_TSV0_LENGTH_CHECK_ERROR (1 << 1) |
| 245 | #define LPC_TSV0_LENGTH_OUT_OF_RANGE (1 << 2) |
| 246 | #define LPC_TSV0_DONE (1 << 3) |
| 247 | #define LPC_TSV0_MULTICAST (1 << 4) |
| 248 | #define LPC_TSV0_BROADCAST (1 << 5) |
| 249 | #define LPC_TSV0_PACKET_DEFER (1 << 6) |
| 250 | #define LPC_TSV0_ESCESSIVE_DEFER (1 << 7) |
| 251 | #define LPC_TSV0_ESCESSIVE_COLLISION (1 << 8) |
| 252 | #define LPC_TSV0_LATE_COLLISION (1 << 9) |
| 253 | #define LPC_TSV0_GIANT (1 << 10) |
| 254 | #define LPC_TSV0_UNDERRUN (1 << 11) |
| 255 | #define LPC_TSV0_TOTAL_BYTES(n) (((n) >> 12) & 0xFFFF) |
| 256 | #define LPC_TSV0_CONTROL_FRAME (1 << 28) |
| 257 | #define LPC_TSV0_PAUSE (1 << 29) |
| 258 | #define LPC_TSV0_BACKPRESSURE (1 << 30) |
| 259 | #define LPC_TSV0_VLAN (1 << 31) |
| 260 | |
| 261 | /* |
| 262 | * tsv1 register definitions |
| 263 | */ |
| 264 | #define LPC_TSV1_TRANSMIT_BYTE_COUNT(n) ((n) & 0xFFFF) |
| 265 | #define LPC_TSV1_COLLISION_COUNT(n) (((n) >> 16) & 0xF) |
| 266 | |
| 267 | /* |
| 268 | * rsv register definitions |
| 269 | */ |
| 270 | #define LPC_RSV_RECEIVED_BYTE_COUNT(n) ((n) & 0xFFFF) |
| 271 | #define LPC_RSV_RXDV_EVENT_IGNORED (1 << 16) |
| 272 | #define LPC_RSV_RXDV_EVENT_PREVIOUSLY_SEEN (1 << 17) |
| 273 | #define LPC_RSV_CARRIER_EVNT_PREVIOUS_SEEN (1 << 18) |
| 274 | #define LPC_RSV_RECEIVE_CODE_VIOLATION (1 << 19) |
| 275 | #define LPC_RSV_CRC_ERROR (1 << 20) |
| 276 | #define LPC_RSV_LENGTH_CHECK_ERROR (1 << 21) |
| 277 | #define LPC_RSV_LENGTH_OUT_OF_RANGE (1 << 22) |
| 278 | #define LPC_RSV_RECEIVE_OK (1 << 23) |
| 279 | #define LPC_RSV_MULTICAST (1 << 24) |
| 280 | #define LPC_RSV_BROADCAST (1 << 25) |
| 281 | #define LPC_RSV_DRIBBLE_NIBBLE (1 << 26) |
| 282 | #define LPC_RSV_CONTROL_FRAME (1 << 27) |
| 283 | #define LPC_RSV_PAUSE (1 << 28) |
| 284 | #define LPC_RSV_UNSUPPORTED_OPCODE (1 << 29) |
| 285 | #define LPC_RSV_VLAN (1 << 30) |
| 286 | |
| 287 | /* |
| 288 | * flowcontrolcounter register definitions |
| 289 | */ |
| 290 | #define LPC_FCCR_MIRRORCOUNTER(n) ((n) & 0xFFFF) |
| 291 | #define LPC_FCCR_PAUSETIMER(n) (((n) >> 16) & 0xFFFF) |
| 292 | |
| 293 | /* |
| 294 | * flowcontrolstatus register definitions |
| 295 | */ |
| 296 | #define LPC_FCCR_MIRRORCOUNTERCURRENT(n) ((n) & 0xFFFF) |
| 297 | |
| 298 | /* |
| 299 | * rxfliterctrl, rxfilterwolstatus, and rxfilterwolclear shared |
| 300 | * register definitions |
| 301 | */ |
| 302 | #define LPC_RXFLTRW_ACCEPTUNICAST (1 << 0) |
| 303 | #define LPC_RXFLTRW_ACCEPTUBROADCAST (1 << 1) |
| 304 | #define LPC_RXFLTRW_ACCEPTUMULTICAST (1 << 2) |
| 305 | #define LPC_RXFLTRW_ACCEPTUNICASTHASH (1 << 3) |
| 306 | #define LPC_RXFLTRW_ACCEPTUMULTICASTHASH (1 << 4) |
| 307 | #define LPC_RXFLTRW_ACCEPTPERFECT (1 << 5) |
| 308 | |
| 309 | /* |
| 310 | * rxfliterctrl register definitions |
| 311 | */ |
| 312 | #define LPC_RXFLTRWSTS_MAGICPACKETENWOL (1 << 12) |
| 313 | #define LPC_RXFLTRWSTS_RXFILTERENWOL (1 << 13) |
| 314 | |
| 315 | /* |
| 316 | * rxfilterwolstatus/rxfilterwolclear register definitions |
| 317 | */ |
| 318 | #define LPC_RXFLTRWSTS_RXFILTERWOL (1 << 7) |
| 319 | #define LPC_RXFLTRWSTS_MAGICPACKETWOL (1 << 8) |
| 320 | |
| 321 | /* |
| 322 | * intstatus, intenable, intclear, and Intset shared register |
| 323 | * definitions |
| 324 | */ |
| 325 | #define LPC_MACINT_RXOVERRUNINTEN (1 << 0) |
| 326 | #define LPC_MACINT_RXERRORONINT (1 << 1) |
| 327 | #define LPC_MACINT_RXFINISHEDINTEN (1 << 2) |
| 328 | #define LPC_MACINT_RXDONEINTEN (1 << 3) |
| 329 | #define LPC_MACINT_TXUNDERRUNINTEN (1 << 4) |
| 330 | #define LPC_MACINT_TXERRORINTEN (1 << 5) |
| 331 | #define LPC_MACINT_TXFINISHEDINTEN (1 << 6) |
| 332 | #define LPC_MACINT_TXDONEINTEN (1 << 7) |
| 333 | #define LPC_MACINT_SOFTINTEN (1 << 12) |
| 334 | #define LPC_MACINT_WAKEUPINTEN (1 << 13) |
| 335 | |
| 336 | /* |
| 337 | * powerdown register definitions |
| 338 | */ |
| 339 | #define LPC_POWERDOWN_MACAHB (1 << 31) |
| 340 | |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 341 | static phy_interface_t lpc_phy_interface_mode(struct device *dev) |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 342 | { |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 343 | if (dev && dev->of_node) { |
| 344 | const char *mode = of_get_property(dev->of_node, |
| 345 | "phy-mode", NULL); |
| 346 | if (mode && !strcmp(mode, "mii")) |
| 347 | return PHY_INTERFACE_MODE_MII; |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 348 | } |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 349 | return PHY_INTERFACE_MODE_RMII; |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 350 | } |
| 351 | |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 352 | static bool use_iram_for_net(struct device *dev) |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 353 | { |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 354 | if (dev && dev->of_node) |
| 355 | return of_property_read_bool(dev->of_node, "use-iram"); |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 356 | return false; |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 357 | } |
| 358 | |
| 359 | /* Receive Status information word */ |
| 360 | #define RXSTATUS_SIZE 0x000007FF |
| 361 | #define RXSTATUS_CONTROL (1 << 18) |
| 362 | #define RXSTATUS_VLAN (1 << 19) |
| 363 | #define RXSTATUS_FILTER (1 << 20) |
| 364 | #define RXSTATUS_MULTICAST (1 << 21) |
| 365 | #define RXSTATUS_BROADCAST (1 << 22) |
| 366 | #define RXSTATUS_CRC (1 << 23) |
| 367 | #define RXSTATUS_SYMBOL (1 << 24) |
| 368 | #define RXSTATUS_LENGTH (1 << 25) |
| 369 | #define RXSTATUS_RANGE (1 << 26) |
| 370 | #define RXSTATUS_ALIGN (1 << 27) |
| 371 | #define RXSTATUS_OVERRUN (1 << 28) |
| 372 | #define RXSTATUS_NODESC (1 << 29) |
| 373 | #define RXSTATUS_LAST (1 << 30) |
| 374 | #define RXSTATUS_ERROR (1 << 31) |
| 375 | |
| 376 | #define RXSTATUS_STATUS_ERROR \ |
| 377 | (RXSTATUS_NODESC | RXSTATUS_OVERRUN | RXSTATUS_ALIGN | \ |
| 378 | RXSTATUS_RANGE | RXSTATUS_LENGTH | RXSTATUS_SYMBOL | RXSTATUS_CRC) |
| 379 | |
| 380 | /* Receive Descriptor control word */ |
| 381 | #define RXDESC_CONTROL_SIZE 0x000007FF |
| 382 | #define RXDESC_CONTROL_INT (1 << 31) |
| 383 | |
| 384 | /* Transmit Status information word */ |
| 385 | #define TXSTATUS_COLLISIONS_GET(x) (((x) >> 21) & 0xF) |
| 386 | #define TXSTATUS_DEFER (1 << 25) |
| 387 | #define TXSTATUS_EXCESSDEFER (1 << 26) |
| 388 | #define TXSTATUS_EXCESSCOLL (1 << 27) |
| 389 | #define TXSTATUS_LATECOLL (1 << 28) |
| 390 | #define TXSTATUS_UNDERRUN (1 << 29) |
| 391 | #define TXSTATUS_NODESC (1 << 30) |
| 392 | #define TXSTATUS_ERROR (1 << 31) |
| 393 | |
| 394 | /* Transmit Descriptor control word */ |
| 395 | #define TXDESC_CONTROL_SIZE 0x000007FF |
| 396 | #define TXDESC_CONTROL_OVERRIDE (1 << 26) |
| 397 | #define TXDESC_CONTROL_HUGE (1 << 27) |
| 398 | #define TXDESC_CONTROL_PAD (1 << 28) |
| 399 | #define TXDESC_CONTROL_CRC (1 << 29) |
| 400 | #define TXDESC_CONTROL_LAST (1 << 30) |
| 401 | #define TXDESC_CONTROL_INT (1 << 31) |
| 402 | |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 403 | /* |
| 404 | * Structure of a TX/RX descriptors and RX status |
| 405 | */ |
| 406 | struct txrx_desc_t { |
| 407 | __le32 packet; |
| 408 | __le32 control; |
| 409 | }; |
| 410 | struct rx_status_t { |
| 411 | __le32 statusinfo; |
| 412 | __le32 statushashcrc; |
| 413 | }; |
| 414 | |
| 415 | /* |
| 416 | * Device driver data structure |
| 417 | */ |
| 418 | struct netdata_local { |
| 419 | struct platform_device *pdev; |
| 420 | struct net_device *ndev; |
| 421 | spinlock_t lock; |
| 422 | void __iomem *net_base; |
| 423 | u32 msg_enable; |
Eric Dumazet | a7e2eaa | 2012-06-12 23:58:16 +0000 | [diff] [blame] | 424 | unsigned int skblen[ENET_TX_DESC]; |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 425 | unsigned int last_tx_idx; |
| 426 | unsigned int num_used_tx_buffs; |
| 427 | struct mii_bus *mii_bus; |
| 428 | struct phy_device *phy_dev; |
| 429 | struct clk *clk; |
| 430 | dma_addr_t dma_buff_base_p; |
| 431 | void *dma_buff_base_v; |
| 432 | size_t dma_buff_size; |
| 433 | struct txrx_desc_t *tx_desc_v; |
| 434 | u32 *tx_stat_v; |
| 435 | void *tx_buff_v; |
| 436 | struct txrx_desc_t *rx_desc_v; |
| 437 | struct rx_status_t *rx_stat_v; |
| 438 | void *rx_buff_v; |
| 439 | int link; |
| 440 | int speed; |
| 441 | int duplex; |
| 442 | struct napi_struct napi; |
| 443 | }; |
| 444 | |
| 445 | /* |
| 446 | * MAC support functions |
| 447 | */ |
| 448 | static void __lpc_set_mac(struct netdata_local *pldat, u8 *mac) |
| 449 | { |
| 450 | u32 tmp; |
| 451 | |
| 452 | /* Set station address */ |
| 453 | tmp = mac[0] | ((u32)mac[1] << 8); |
| 454 | writel(tmp, LPC_ENET_SA2(pldat->net_base)); |
| 455 | tmp = mac[2] | ((u32)mac[3] << 8); |
| 456 | writel(tmp, LPC_ENET_SA1(pldat->net_base)); |
| 457 | tmp = mac[4] | ((u32)mac[5] << 8); |
| 458 | writel(tmp, LPC_ENET_SA0(pldat->net_base)); |
| 459 | |
| 460 | netdev_dbg(pldat->ndev, "Ethernet MAC address %pM\n", mac); |
| 461 | } |
| 462 | |
| 463 | static void __lpc_get_mac(struct netdata_local *pldat, u8 *mac) |
| 464 | { |
| 465 | u32 tmp; |
| 466 | |
| 467 | /* Get station address */ |
| 468 | tmp = readl(LPC_ENET_SA2(pldat->net_base)); |
| 469 | mac[0] = tmp & 0xFF; |
| 470 | mac[1] = tmp >> 8; |
| 471 | tmp = readl(LPC_ENET_SA1(pldat->net_base)); |
| 472 | mac[2] = tmp & 0xFF; |
| 473 | mac[3] = tmp >> 8; |
| 474 | tmp = readl(LPC_ENET_SA0(pldat->net_base)); |
| 475 | mac[4] = tmp & 0xFF; |
| 476 | mac[5] = tmp >> 8; |
| 477 | } |
| 478 | |
Vladimir Zapolskiy | 33a8316 | 2015-10-01 00:37:43 +0300 | [diff] [blame] | 479 | static void __lpc_eth_clock_enable(struct netdata_local *pldat, bool enable) |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 480 | { |
| 481 | if (enable) |
Vladimir Zapolskiy | 33a8316 | 2015-10-01 00:37:43 +0300 | [diff] [blame] | 482 | clk_prepare_enable(pldat->clk); |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 483 | else |
Vladimir Zapolskiy | 33a8316 | 2015-10-01 00:37:43 +0300 | [diff] [blame] | 484 | clk_disable_unprepare(pldat->clk); |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 485 | } |
| 486 | |
| 487 | static void __lpc_params_setup(struct netdata_local *pldat) |
| 488 | { |
| 489 | u32 tmp; |
| 490 | |
| 491 | if (pldat->duplex == DUPLEX_FULL) { |
| 492 | tmp = readl(LPC_ENET_MAC2(pldat->net_base)); |
| 493 | tmp |= LPC_MAC2_FULL_DUPLEX; |
| 494 | writel(tmp, LPC_ENET_MAC2(pldat->net_base)); |
| 495 | tmp = readl(LPC_ENET_COMMAND(pldat->net_base)); |
| 496 | tmp |= LPC_COMMAND_FULLDUPLEX; |
| 497 | writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); |
| 498 | writel(LPC_IPGT_LOAD(0x15), LPC_ENET_IPGT(pldat->net_base)); |
| 499 | } else { |
| 500 | tmp = readl(LPC_ENET_MAC2(pldat->net_base)); |
| 501 | tmp &= ~LPC_MAC2_FULL_DUPLEX; |
| 502 | writel(tmp, LPC_ENET_MAC2(pldat->net_base)); |
| 503 | tmp = readl(LPC_ENET_COMMAND(pldat->net_base)); |
| 504 | tmp &= ~LPC_COMMAND_FULLDUPLEX; |
| 505 | writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); |
| 506 | writel(LPC_IPGT_LOAD(0x12), LPC_ENET_IPGT(pldat->net_base)); |
| 507 | } |
| 508 | |
| 509 | if (pldat->speed == SPEED_100) |
| 510 | writel(LPC_SUPP_SPEED, LPC_ENET_SUPP(pldat->net_base)); |
| 511 | else |
| 512 | writel(0, LPC_ENET_SUPP(pldat->net_base)); |
| 513 | } |
| 514 | |
| 515 | static void __lpc_eth_reset(struct netdata_local *pldat) |
| 516 | { |
| 517 | /* Reset all MAC logic */ |
| 518 | writel((LPC_MAC1_RESET_TX | LPC_MAC1_RESET_MCS_TX | LPC_MAC1_RESET_RX | |
| 519 | LPC_MAC1_RESET_MCS_RX | LPC_MAC1_SIMULATION_RESET | |
| 520 | LPC_MAC1_SOFT_RESET), LPC_ENET_MAC1(pldat->net_base)); |
| 521 | writel((LPC_COMMAND_REG_RESET | LPC_COMMAND_TXRESET | |
| 522 | LPC_COMMAND_RXRESET), LPC_ENET_COMMAND(pldat->net_base)); |
| 523 | } |
| 524 | |
| 525 | static int __lpc_mii_mngt_reset(struct netdata_local *pldat) |
| 526 | { |
| 527 | /* Reset MII management hardware */ |
| 528 | writel(LPC_MCFG_RESET_MII_MGMT, LPC_ENET_MCFG(pldat->net_base)); |
| 529 | |
| 530 | /* Setup MII clock to slowest rate with a /28 divider */ |
| 531 | writel(LPC_MCFG_CLOCK_SELECT(LPC_MCFG_CLOCK_HOST_DIV_28), |
| 532 | LPC_ENET_MCFG(pldat->net_base)); |
| 533 | |
| 534 | return 0; |
| 535 | } |
| 536 | |
| 537 | static inline phys_addr_t __va_to_pa(void *addr, struct netdata_local *pldat) |
| 538 | { |
| 539 | phys_addr_t phaddr; |
| 540 | |
| 541 | phaddr = addr - pldat->dma_buff_base_v; |
| 542 | phaddr += pldat->dma_buff_base_p; |
| 543 | |
| 544 | return phaddr; |
| 545 | } |
| 546 | |
| 547 | static void lpc_eth_enable_int(void __iomem *regbase) |
| 548 | { |
| 549 | writel((LPC_MACINT_RXDONEINTEN | LPC_MACINT_TXDONEINTEN), |
| 550 | LPC_ENET_INTENABLE(regbase)); |
| 551 | } |
| 552 | |
| 553 | static void lpc_eth_disable_int(void __iomem *regbase) |
| 554 | { |
| 555 | writel(0, LPC_ENET_INTENABLE(regbase)); |
| 556 | } |
| 557 | |
| 558 | /* Setup TX/RX descriptors */ |
| 559 | static void __lpc_txrx_desc_setup(struct netdata_local *pldat) |
| 560 | { |
| 561 | u32 *ptxstat; |
| 562 | void *tbuff; |
| 563 | int i; |
| 564 | struct txrx_desc_t *ptxrxdesc; |
| 565 | struct rx_status_t *prxstat; |
| 566 | |
| 567 | tbuff = PTR_ALIGN(pldat->dma_buff_base_v, 16); |
| 568 | |
| 569 | /* Setup TX descriptors, status, and buffers */ |
| 570 | pldat->tx_desc_v = tbuff; |
| 571 | tbuff += sizeof(struct txrx_desc_t) * ENET_TX_DESC; |
| 572 | |
| 573 | pldat->tx_stat_v = tbuff; |
| 574 | tbuff += sizeof(u32) * ENET_TX_DESC; |
| 575 | |
| 576 | tbuff = PTR_ALIGN(tbuff, 16); |
| 577 | pldat->tx_buff_v = tbuff; |
| 578 | tbuff += ENET_MAXF_SIZE * ENET_TX_DESC; |
| 579 | |
| 580 | /* Setup RX descriptors, status, and buffers */ |
| 581 | pldat->rx_desc_v = tbuff; |
| 582 | tbuff += sizeof(struct txrx_desc_t) * ENET_RX_DESC; |
| 583 | |
| 584 | tbuff = PTR_ALIGN(tbuff, 16); |
| 585 | pldat->rx_stat_v = tbuff; |
| 586 | tbuff += sizeof(struct rx_status_t) * ENET_RX_DESC; |
| 587 | |
| 588 | tbuff = PTR_ALIGN(tbuff, 16); |
| 589 | pldat->rx_buff_v = tbuff; |
| 590 | tbuff += ENET_MAXF_SIZE * ENET_RX_DESC; |
| 591 | |
| 592 | /* Map the TX descriptors to the TX buffers in hardware */ |
| 593 | for (i = 0; i < ENET_TX_DESC; i++) { |
| 594 | ptxstat = &pldat->tx_stat_v[i]; |
| 595 | ptxrxdesc = &pldat->tx_desc_v[i]; |
| 596 | |
| 597 | ptxrxdesc->packet = __va_to_pa( |
| 598 | pldat->tx_buff_v + i * ENET_MAXF_SIZE, pldat); |
| 599 | ptxrxdesc->control = 0; |
| 600 | *ptxstat = 0; |
| 601 | } |
| 602 | |
| 603 | /* Map the RX descriptors to the RX buffers in hardware */ |
| 604 | for (i = 0; i < ENET_RX_DESC; i++) { |
| 605 | prxstat = &pldat->rx_stat_v[i]; |
| 606 | ptxrxdesc = &pldat->rx_desc_v[i]; |
| 607 | |
| 608 | ptxrxdesc->packet = __va_to_pa( |
| 609 | pldat->rx_buff_v + i * ENET_MAXF_SIZE, pldat); |
| 610 | ptxrxdesc->control = RXDESC_CONTROL_INT | (ENET_MAXF_SIZE - 1); |
| 611 | prxstat->statusinfo = 0; |
| 612 | prxstat->statushashcrc = 0; |
| 613 | } |
| 614 | |
| 615 | /* Setup base addresses in hardware to point to buffers and |
| 616 | * descriptors |
| 617 | */ |
| 618 | writel((ENET_TX_DESC - 1), |
| 619 | LPC_ENET_TXDESCRIPTORNUMBER(pldat->net_base)); |
| 620 | writel(__va_to_pa(pldat->tx_desc_v, pldat), |
| 621 | LPC_ENET_TXDESCRIPTOR(pldat->net_base)); |
| 622 | writel(__va_to_pa(pldat->tx_stat_v, pldat), |
| 623 | LPC_ENET_TXSTATUS(pldat->net_base)); |
| 624 | writel((ENET_RX_DESC - 1), |
| 625 | LPC_ENET_RXDESCRIPTORNUMBER(pldat->net_base)); |
| 626 | writel(__va_to_pa(pldat->rx_desc_v, pldat), |
| 627 | LPC_ENET_RXDESCRIPTOR(pldat->net_base)); |
| 628 | writel(__va_to_pa(pldat->rx_stat_v, pldat), |
| 629 | LPC_ENET_RXSTATUS(pldat->net_base)); |
| 630 | } |
| 631 | |
| 632 | static void __lpc_eth_init(struct netdata_local *pldat) |
| 633 | { |
| 634 | u32 tmp; |
| 635 | |
| 636 | /* Disable controller and reset */ |
| 637 | tmp = readl(LPC_ENET_COMMAND(pldat->net_base)); |
| 638 | tmp &= ~LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE; |
| 639 | writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); |
| 640 | tmp = readl(LPC_ENET_MAC1(pldat->net_base)); |
| 641 | tmp &= ~LPC_MAC1_RECV_ENABLE; |
| 642 | writel(tmp, LPC_ENET_MAC1(pldat->net_base)); |
| 643 | |
| 644 | /* Initial MAC setup */ |
| 645 | writel(LPC_MAC1_PASS_ALL_RX_FRAMES, LPC_ENET_MAC1(pldat->net_base)); |
| 646 | writel((LPC_MAC2_PAD_CRC_ENABLE | LPC_MAC2_CRC_ENABLE), |
| 647 | LPC_ENET_MAC2(pldat->net_base)); |
| 648 | writel(ENET_MAXF_SIZE, LPC_ENET_MAXF(pldat->net_base)); |
| 649 | |
| 650 | /* Collision window, gap */ |
| 651 | writel((LPC_CLRT_LOAD_RETRY_MAX(0xF) | |
| 652 | LPC_CLRT_LOAD_COLLISION_WINDOW(0x37)), |
| 653 | LPC_ENET_CLRT(pldat->net_base)); |
| 654 | writel(LPC_IPGR_LOAD_PART2(0x12), LPC_ENET_IPGR(pldat->net_base)); |
| 655 | |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 656 | if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII) |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 657 | writel(LPC_COMMAND_PASSRUNTFRAME, |
| 658 | LPC_ENET_COMMAND(pldat->net_base)); |
| 659 | else { |
| 660 | writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII), |
| 661 | LPC_ENET_COMMAND(pldat->net_base)); |
| 662 | writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base)); |
| 663 | } |
| 664 | |
| 665 | __lpc_params_setup(pldat); |
| 666 | |
| 667 | /* Setup TX and RX descriptors */ |
| 668 | __lpc_txrx_desc_setup(pldat); |
| 669 | |
| 670 | /* Setup packet filtering */ |
| 671 | writel((LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT), |
| 672 | LPC_ENET_RXFILTER_CTRL(pldat->net_base)); |
| 673 | |
| 674 | /* Get the next TX buffer output index */ |
| 675 | pldat->num_used_tx_buffs = 0; |
| 676 | pldat->last_tx_idx = |
| 677 | readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base)); |
| 678 | |
| 679 | /* Clear and enable interrupts */ |
| 680 | writel(0xFFFF, LPC_ENET_INTCLEAR(pldat->net_base)); |
| 681 | smp_wmb(); |
| 682 | lpc_eth_enable_int(pldat->net_base); |
| 683 | |
| 684 | /* Enable controller */ |
| 685 | tmp = readl(LPC_ENET_COMMAND(pldat->net_base)); |
| 686 | tmp |= LPC_COMMAND_RXENABLE | LPC_COMMAND_TXENABLE; |
| 687 | writel(tmp, LPC_ENET_COMMAND(pldat->net_base)); |
| 688 | tmp = readl(LPC_ENET_MAC1(pldat->net_base)); |
| 689 | tmp |= LPC_MAC1_RECV_ENABLE; |
| 690 | writel(tmp, LPC_ENET_MAC1(pldat->net_base)); |
| 691 | } |
| 692 | |
| 693 | static void __lpc_eth_shutdown(struct netdata_local *pldat) |
| 694 | { |
| 695 | /* Reset ethernet and power down PHY */ |
| 696 | __lpc_eth_reset(pldat); |
| 697 | writel(0, LPC_ENET_MAC1(pldat->net_base)); |
| 698 | writel(0, LPC_ENET_MAC2(pldat->net_base)); |
| 699 | } |
| 700 | |
| 701 | /* |
| 702 | * MAC<--->PHY support functions |
| 703 | */ |
| 704 | static int lpc_mdio_read(struct mii_bus *bus, int phy_id, int phyreg) |
| 705 | { |
| 706 | struct netdata_local *pldat = bus->priv; |
| 707 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
| 708 | int lps; |
| 709 | |
| 710 | writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base)); |
| 711 | writel(LPC_MCMD_READ, LPC_ENET_MCMD(pldat->net_base)); |
| 712 | |
| 713 | /* Wait for unbusy status */ |
| 714 | while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) { |
| 715 | if (time_after(jiffies, timeout)) |
| 716 | return -EIO; |
| 717 | cpu_relax(); |
| 718 | } |
| 719 | |
| 720 | lps = readl(LPC_ENET_MRDD(pldat->net_base)); |
| 721 | writel(0, LPC_ENET_MCMD(pldat->net_base)); |
| 722 | |
| 723 | return lps; |
| 724 | } |
| 725 | |
| 726 | static int lpc_mdio_write(struct mii_bus *bus, int phy_id, int phyreg, |
| 727 | u16 phydata) |
| 728 | { |
| 729 | struct netdata_local *pldat = bus->priv; |
| 730 | unsigned long timeout = jiffies + msecs_to_jiffies(100); |
| 731 | |
| 732 | writel(((phy_id << 8) | phyreg), LPC_ENET_MADR(pldat->net_base)); |
| 733 | writel(phydata, LPC_ENET_MWTD(pldat->net_base)); |
| 734 | |
| 735 | /* Wait for completion */ |
| 736 | while (readl(LPC_ENET_MIND(pldat->net_base)) & LPC_MIND_BUSY) { |
| 737 | if (time_after(jiffies, timeout)) |
| 738 | return -EIO; |
| 739 | cpu_relax(); |
| 740 | } |
| 741 | |
| 742 | return 0; |
| 743 | } |
| 744 | |
| 745 | static int lpc_mdio_reset(struct mii_bus *bus) |
| 746 | { |
| 747 | return __lpc_mii_mngt_reset((struct netdata_local *)bus->priv); |
| 748 | } |
| 749 | |
| 750 | static void lpc_handle_link_change(struct net_device *ndev) |
| 751 | { |
| 752 | struct netdata_local *pldat = netdev_priv(ndev); |
| 753 | struct phy_device *phydev = pldat->phy_dev; |
| 754 | unsigned long flags; |
| 755 | |
| 756 | bool status_change = false; |
| 757 | |
| 758 | spin_lock_irqsave(&pldat->lock, flags); |
| 759 | |
| 760 | if (phydev->link) { |
| 761 | if ((pldat->speed != phydev->speed) || |
| 762 | (pldat->duplex != phydev->duplex)) { |
| 763 | pldat->speed = phydev->speed; |
| 764 | pldat->duplex = phydev->duplex; |
| 765 | status_change = true; |
| 766 | } |
| 767 | } |
| 768 | |
| 769 | if (phydev->link != pldat->link) { |
| 770 | if (!phydev->link) { |
| 771 | pldat->speed = 0; |
| 772 | pldat->duplex = -1; |
| 773 | } |
| 774 | pldat->link = phydev->link; |
| 775 | |
| 776 | status_change = true; |
| 777 | } |
| 778 | |
| 779 | spin_unlock_irqrestore(&pldat->lock, flags); |
| 780 | |
| 781 | if (status_change) |
| 782 | __lpc_params_setup(pldat); |
| 783 | } |
| 784 | |
| 785 | static int lpc_mii_probe(struct net_device *ndev) |
| 786 | { |
| 787 | struct netdata_local *pldat = netdev_priv(ndev); |
| 788 | struct phy_device *phydev = phy_find_first(pldat->mii_bus); |
| 789 | |
| 790 | if (!phydev) { |
| 791 | netdev_err(ndev, "no PHY found\n"); |
| 792 | return -ENODEV; |
| 793 | } |
| 794 | |
| 795 | /* Attach to the PHY */ |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 796 | if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII) |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 797 | netdev_info(ndev, "using MII interface\n"); |
| 798 | else |
| 799 | netdev_info(ndev, "using RMII interface\n"); |
| 800 | phydev = phy_connect(ndev, dev_name(&phydev->dev), |
Florian Fainelli | f9a8f83 | 2013-01-14 00:52:52 +0000 | [diff] [blame] | 801 | &lpc_handle_link_change, |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 802 | lpc_phy_interface_mode(&pldat->pdev->dev)); |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 803 | |
| 804 | if (IS_ERR(phydev)) { |
| 805 | netdev_err(ndev, "Could not attach to PHY\n"); |
| 806 | return PTR_ERR(phydev); |
| 807 | } |
| 808 | |
| 809 | /* mask with MAC supported features */ |
| 810 | phydev->supported &= PHY_BASIC_FEATURES; |
| 811 | |
| 812 | phydev->advertising = phydev->supported; |
| 813 | |
| 814 | pldat->link = 0; |
| 815 | pldat->speed = 0; |
| 816 | pldat->duplex = -1; |
| 817 | pldat->phy_dev = phydev; |
| 818 | |
| 819 | netdev_info(ndev, |
| 820 | "attached PHY driver [%s] (mii_bus:phy_addr=%s, irq=%d)\n", |
| 821 | phydev->drv->name, dev_name(&phydev->dev), phydev->irq); |
| 822 | return 0; |
| 823 | } |
| 824 | |
| 825 | static int lpc_mii_init(struct netdata_local *pldat) |
| 826 | { |
| 827 | int err = -ENXIO, i; |
| 828 | |
| 829 | pldat->mii_bus = mdiobus_alloc(); |
| 830 | if (!pldat->mii_bus) { |
| 831 | err = -ENOMEM; |
| 832 | goto err_out; |
| 833 | } |
| 834 | |
| 835 | /* Setup MII mode */ |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 836 | if (lpc_phy_interface_mode(&pldat->pdev->dev) == PHY_INTERFACE_MODE_MII) |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 837 | writel(LPC_COMMAND_PASSRUNTFRAME, |
| 838 | LPC_ENET_COMMAND(pldat->net_base)); |
| 839 | else { |
| 840 | writel((LPC_COMMAND_PASSRUNTFRAME | LPC_COMMAND_RMII), |
| 841 | LPC_ENET_COMMAND(pldat->net_base)); |
| 842 | writel(LPC_SUPP_RESET_RMII, LPC_ENET_SUPP(pldat->net_base)); |
| 843 | } |
| 844 | |
| 845 | pldat->mii_bus->name = "lpc_mii_bus"; |
| 846 | pldat->mii_bus->read = &lpc_mdio_read; |
| 847 | pldat->mii_bus->write = &lpc_mdio_write; |
| 848 | pldat->mii_bus->reset = &lpc_mdio_reset; |
| 849 | snprintf(pldat->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", |
| 850 | pldat->pdev->name, pldat->pdev->id); |
| 851 | pldat->mii_bus->priv = pldat; |
| 852 | pldat->mii_bus->parent = &pldat->pdev->dev; |
| 853 | |
| 854 | pldat->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); |
| 855 | if (!pldat->mii_bus->irq) { |
| 856 | err = -ENOMEM; |
| 857 | goto err_out_1; |
| 858 | } |
| 859 | |
| 860 | for (i = 0; i < PHY_MAX_ADDR; i++) |
| 861 | pldat->mii_bus->irq[i] = PHY_POLL; |
| 862 | |
| 863 | platform_set_drvdata(pldat->pdev, pldat->mii_bus); |
| 864 | |
| 865 | if (mdiobus_register(pldat->mii_bus)) |
| 866 | goto err_out_free_mdio_irq; |
| 867 | |
| 868 | if (lpc_mii_probe(pldat->ndev) != 0) |
| 869 | goto err_out_unregister_bus; |
| 870 | |
| 871 | return 0; |
| 872 | |
| 873 | err_out_unregister_bus: |
| 874 | mdiobus_unregister(pldat->mii_bus); |
| 875 | err_out_free_mdio_irq: |
| 876 | kfree(pldat->mii_bus->irq); |
| 877 | err_out_1: |
| 878 | mdiobus_free(pldat->mii_bus); |
| 879 | err_out: |
| 880 | return err; |
| 881 | } |
| 882 | |
| 883 | static void __lpc_handle_xmit(struct net_device *ndev) |
| 884 | { |
| 885 | struct netdata_local *pldat = netdev_priv(ndev); |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 886 | u32 txcidx, *ptxstat, txstat; |
| 887 | |
| 888 | txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base)); |
| 889 | while (pldat->last_tx_idx != txcidx) { |
Eric Dumazet | a7e2eaa | 2012-06-12 23:58:16 +0000 | [diff] [blame] | 890 | unsigned int skblen = pldat->skblen[pldat->last_tx_idx]; |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 891 | |
| 892 | /* A buffer is available, get buffer status */ |
| 893 | ptxstat = &pldat->tx_stat_v[pldat->last_tx_idx]; |
| 894 | txstat = *ptxstat; |
| 895 | |
| 896 | /* Next buffer and decrement used buffer counter */ |
| 897 | pldat->num_used_tx_buffs--; |
| 898 | pldat->last_tx_idx++; |
| 899 | if (pldat->last_tx_idx >= ENET_TX_DESC) |
| 900 | pldat->last_tx_idx = 0; |
| 901 | |
| 902 | /* Update collision counter */ |
| 903 | ndev->stats.collisions += TXSTATUS_COLLISIONS_GET(txstat); |
| 904 | |
| 905 | /* Any errors occurred? */ |
| 906 | if (txstat & TXSTATUS_ERROR) { |
| 907 | if (txstat & TXSTATUS_UNDERRUN) { |
| 908 | /* FIFO underrun */ |
| 909 | ndev->stats.tx_fifo_errors++; |
| 910 | } |
| 911 | if (txstat & TXSTATUS_LATECOLL) { |
| 912 | /* Late collision */ |
| 913 | ndev->stats.tx_aborted_errors++; |
| 914 | } |
| 915 | if (txstat & TXSTATUS_EXCESSCOLL) { |
| 916 | /* Excessive collision */ |
| 917 | ndev->stats.tx_aborted_errors++; |
| 918 | } |
| 919 | if (txstat & TXSTATUS_EXCESSDEFER) { |
| 920 | /* Defer limit */ |
| 921 | ndev->stats.tx_aborted_errors++; |
| 922 | } |
| 923 | ndev->stats.tx_errors++; |
| 924 | } else { |
| 925 | /* Update stats */ |
| 926 | ndev->stats.tx_packets++; |
Eric Dumazet | a7e2eaa | 2012-06-12 23:58:16 +0000 | [diff] [blame] | 927 | ndev->stats.tx_bytes += skblen; |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 928 | } |
| 929 | |
| 930 | txcidx = readl(LPC_ENET_TXCONSUMEINDEX(pldat->net_base)); |
| 931 | } |
| 932 | |
Eric Dumazet | 3f16da5 | 2012-06-11 07:21:36 +0000 | [diff] [blame] | 933 | if (pldat->num_used_tx_buffs <= ENET_TX_DESC/2) { |
| 934 | if (netif_queue_stopped(ndev)) |
| 935 | netif_wake_queue(ndev); |
| 936 | } |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 937 | } |
| 938 | |
| 939 | static int __lpc_handle_recv(struct net_device *ndev, int budget) |
| 940 | { |
| 941 | struct netdata_local *pldat = netdev_priv(ndev); |
| 942 | struct sk_buff *skb; |
| 943 | u32 rxconsidx, len, ethst; |
| 944 | struct rx_status_t *prxstat; |
| 945 | u8 *prdbuf; |
| 946 | int rx_done = 0; |
| 947 | |
| 948 | /* Get the current RX buffer indexes */ |
| 949 | rxconsidx = readl(LPC_ENET_RXCONSUMEINDEX(pldat->net_base)); |
| 950 | while (rx_done < budget && rxconsidx != |
| 951 | readl(LPC_ENET_RXPRODUCEINDEX(pldat->net_base))) { |
| 952 | /* Get pointer to receive status */ |
| 953 | prxstat = &pldat->rx_stat_v[rxconsidx]; |
| 954 | len = (prxstat->statusinfo & RXSTATUS_SIZE) + 1; |
| 955 | |
| 956 | /* Status error? */ |
| 957 | ethst = prxstat->statusinfo; |
| 958 | if ((ethst & (RXSTATUS_ERROR | RXSTATUS_STATUS_ERROR)) == |
| 959 | (RXSTATUS_ERROR | RXSTATUS_RANGE)) |
| 960 | ethst &= ~RXSTATUS_ERROR; |
| 961 | |
| 962 | if (ethst & RXSTATUS_ERROR) { |
| 963 | int si = prxstat->statusinfo; |
| 964 | /* Check statuses */ |
| 965 | if (si & RXSTATUS_OVERRUN) { |
| 966 | /* Overrun error */ |
| 967 | ndev->stats.rx_fifo_errors++; |
| 968 | } else if (si & RXSTATUS_CRC) { |
| 969 | /* CRC error */ |
| 970 | ndev->stats.rx_crc_errors++; |
| 971 | } else if (si & RXSTATUS_LENGTH) { |
| 972 | /* Length error */ |
| 973 | ndev->stats.rx_length_errors++; |
| 974 | } else if (si & RXSTATUS_ERROR) { |
| 975 | /* Other error */ |
| 976 | ndev->stats.rx_length_errors++; |
| 977 | } |
| 978 | ndev->stats.rx_errors++; |
| 979 | } else { |
| 980 | /* Packet is good */ |
Eric Dumazet | e7f8c1f | 2012-04-03 12:02:11 +0000 | [diff] [blame] | 981 | skb = dev_alloc_skb(len); |
| 982 | if (!skb) { |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 983 | ndev->stats.rx_dropped++; |
Eric Dumazet | e7f8c1f | 2012-04-03 12:02:11 +0000 | [diff] [blame] | 984 | } else { |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 985 | prdbuf = skb_put(skb, len); |
| 986 | |
| 987 | /* Copy packet from buffer */ |
| 988 | memcpy(prdbuf, pldat->rx_buff_v + |
| 989 | rxconsidx * ENET_MAXF_SIZE, len); |
| 990 | |
| 991 | /* Pass to upper layer */ |
| 992 | skb->protocol = eth_type_trans(skb, ndev); |
| 993 | netif_receive_skb(skb); |
| 994 | ndev->stats.rx_packets++; |
| 995 | ndev->stats.rx_bytes += len; |
| 996 | } |
| 997 | } |
| 998 | |
| 999 | /* Increment consume index */ |
| 1000 | rxconsidx = rxconsidx + 1; |
| 1001 | if (rxconsidx >= ENET_RX_DESC) |
| 1002 | rxconsidx = 0; |
| 1003 | writel(rxconsidx, |
| 1004 | LPC_ENET_RXCONSUMEINDEX(pldat->net_base)); |
| 1005 | rx_done++; |
| 1006 | } |
| 1007 | |
| 1008 | return rx_done; |
| 1009 | } |
| 1010 | |
| 1011 | static int lpc_eth_poll(struct napi_struct *napi, int budget) |
| 1012 | { |
| 1013 | struct netdata_local *pldat = container_of(napi, |
| 1014 | struct netdata_local, napi); |
| 1015 | struct net_device *ndev = pldat->ndev; |
| 1016 | int rx_done = 0; |
| 1017 | struct netdev_queue *txq = netdev_get_tx_queue(ndev, 0); |
| 1018 | |
| 1019 | __netif_tx_lock(txq, smp_processor_id()); |
| 1020 | __lpc_handle_xmit(ndev); |
| 1021 | __netif_tx_unlock(txq); |
| 1022 | rx_done = __lpc_handle_recv(ndev, budget); |
| 1023 | |
| 1024 | if (rx_done < budget) { |
| 1025 | napi_complete(napi); |
| 1026 | lpc_eth_enable_int(pldat->net_base); |
| 1027 | } |
| 1028 | |
| 1029 | return rx_done; |
| 1030 | } |
| 1031 | |
| 1032 | static irqreturn_t __lpc_eth_interrupt(int irq, void *dev_id) |
| 1033 | { |
| 1034 | struct net_device *ndev = dev_id; |
| 1035 | struct netdata_local *pldat = netdev_priv(ndev); |
| 1036 | u32 tmp; |
| 1037 | |
| 1038 | spin_lock(&pldat->lock); |
| 1039 | |
| 1040 | tmp = readl(LPC_ENET_INTSTATUS(pldat->net_base)); |
| 1041 | /* Clear interrupts */ |
| 1042 | writel(tmp, LPC_ENET_INTCLEAR(pldat->net_base)); |
| 1043 | |
| 1044 | lpc_eth_disable_int(pldat->net_base); |
| 1045 | if (likely(napi_schedule_prep(&pldat->napi))) |
| 1046 | __napi_schedule(&pldat->napi); |
| 1047 | |
| 1048 | spin_unlock(&pldat->lock); |
| 1049 | |
| 1050 | return IRQ_HANDLED; |
| 1051 | } |
| 1052 | |
| 1053 | static int lpc_eth_close(struct net_device *ndev) |
| 1054 | { |
| 1055 | unsigned long flags; |
| 1056 | struct netdata_local *pldat = netdev_priv(ndev); |
| 1057 | |
| 1058 | if (netif_msg_ifdown(pldat)) |
| 1059 | dev_dbg(&pldat->pdev->dev, "shutting down %s\n", ndev->name); |
| 1060 | |
| 1061 | napi_disable(&pldat->napi); |
| 1062 | netif_stop_queue(ndev); |
| 1063 | |
| 1064 | if (pldat->phy_dev) |
| 1065 | phy_stop(pldat->phy_dev); |
| 1066 | |
| 1067 | spin_lock_irqsave(&pldat->lock, flags); |
| 1068 | __lpc_eth_reset(pldat); |
| 1069 | netif_carrier_off(ndev); |
| 1070 | writel(0, LPC_ENET_MAC1(pldat->net_base)); |
| 1071 | writel(0, LPC_ENET_MAC2(pldat->net_base)); |
| 1072 | spin_unlock_irqrestore(&pldat->lock, flags); |
| 1073 | |
| 1074 | __lpc_eth_clock_enable(pldat, false); |
| 1075 | |
| 1076 | return 0; |
| 1077 | } |
| 1078 | |
| 1079 | static int lpc_eth_hard_start_xmit(struct sk_buff *skb, struct net_device *ndev) |
| 1080 | { |
| 1081 | struct netdata_local *pldat = netdev_priv(ndev); |
| 1082 | u32 len, txidx; |
| 1083 | u32 *ptxstat; |
| 1084 | struct txrx_desc_t *ptxrxdesc; |
| 1085 | |
| 1086 | len = skb->len; |
| 1087 | |
| 1088 | spin_lock_irq(&pldat->lock); |
| 1089 | |
| 1090 | if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1)) { |
| 1091 | /* This function should never be called when there are no |
| 1092 | buffers */ |
| 1093 | netif_stop_queue(ndev); |
| 1094 | spin_unlock_irq(&pldat->lock); |
| 1095 | WARN(1, "BUG! TX request when no free TX buffers!\n"); |
| 1096 | return NETDEV_TX_BUSY; |
| 1097 | } |
| 1098 | |
| 1099 | /* Get the next TX descriptor index */ |
| 1100 | txidx = readl(LPC_ENET_TXPRODUCEINDEX(pldat->net_base)); |
| 1101 | |
| 1102 | /* Setup control for the transfer */ |
| 1103 | ptxstat = &pldat->tx_stat_v[txidx]; |
| 1104 | *ptxstat = 0; |
| 1105 | ptxrxdesc = &pldat->tx_desc_v[txidx]; |
| 1106 | ptxrxdesc->control = |
| 1107 | (len - 1) | TXDESC_CONTROL_LAST | TXDESC_CONTROL_INT; |
| 1108 | |
| 1109 | /* Copy data to the DMA buffer */ |
| 1110 | memcpy(pldat->tx_buff_v + txidx * ENET_MAXF_SIZE, skb->data, len); |
| 1111 | |
| 1112 | /* Save the buffer and increment the buffer counter */ |
Eric Dumazet | a7e2eaa | 2012-06-12 23:58:16 +0000 | [diff] [blame] | 1113 | pldat->skblen[txidx] = len; |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1114 | pldat->num_used_tx_buffs++; |
| 1115 | |
| 1116 | /* Start transmit */ |
| 1117 | txidx++; |
| 1118 | if (txidx >= ENET_TX_DESC) |
| 1119 | txidx = 0; |
| 1120 | writel(txidx, LPC_ENET_TXPRODUCEINDEX(pldat->net_base)); |
| 1121 | |
| 1122 | /* Stop queue if no more TX buffers */ |
| 1123 | if (pldat->num_used_tx_buffs >= (ENET_TX_DESC - 1)) |
| 1124 | netif_stop_queue(ndev); |
| 1125 | |
| 1126 | spin_unlock_irq(&pldat->lock); |
| 1127 | |
Eric Dumazet | a7e2eaa | 2012-06-12 23:58:16 +0000 | [diff] [blame] | 1128 | dev_kfree_skb(skb); |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1129 | return NETDEV_TX_OK; |
| 1130 | } |
| 1131 | |
| 1132 | static int lpc_set_mac_address(struct net_device *ndev, void *p) |
| 1133 | { |
| 1134 | struct sockaddr *addr = p; |
| 1135 | struct netdata_local *pldat = netdev_priv(ndev); |
| 1136 | unsigned long flags; |
| 1137 | |
| 1138 | if (!is_valid_ether_addr(addr->sa_data)) |
| 1139 | return -EADDRNOTAVAIL; |
| 1140 | memcpy(ndev->dev_addr, addr->sa_data, ETH_ALEN); |
| 1141 | |
| 1142 | spin_lock_irqsave(&pldat->lock, flags); |
| 1143 | |
| 1144 | /* Set station address */ |
| 1145 | __lpc_set_mac(pldat, ndev->dev_addr); |
| 1146 | |
| 1147 | spin_unlock_irqrestore(&pldat->lock, flags); |
| 1148 | |
| 1149 | return 0; |
| 1150 | } |
| 1151 | |
| 1152 | static void lpc_eth_set_multicast_list(struct net_device *ndev) |
| 1153 | { |
| 1154 | struct netdata_local *pldat = netdev_priv(ndev); |
| 1155 | struct netdev_hw_addr_list *mcptr = &ndev->mc; |
| 1156 | struct netdev_hw_addr *ha; |
| 1157 | u32 tmp32, hash_val, hashlo, hashhi; |
| 1158 | unsigned long flags; |
| 1159 | |
| 1160 | spin_lock_irqsave(&pldat->lock, flags); |
| 1161 | |
| 1162 | /* Set station address */ |
| 1163 | __lpc_set_mac(pldat, ndev->dev_addr); |
| 1164 | |
| 1165 | tmp32 = LPC_RXFLTRW_ACCEPTUBROADCAST | LPC_RXFLTRW_ACCEPTPERFECT; |
| 1166 | |
| 1167 | if (ndev->flags & IFF_PROMISC) |
| 1168 | tmp32 |= LPC_RXFLTRW_ACCEPTUNICAST | |
| 1169 | LPC_RXFLTRW_ACCEPTUMULTICAST; |
| 1170 | if (ndev->flags & IFF_ALLMULTI) |
| 1171 | tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICAST; |
| 1172 | |
| 1173 | if (netdev_hw_addr_list_count(mcptr)) |
| 1174 | tmp32 |= LPC_RXFLTRW_ACCEPTUMULTICASTHASH; |
| 1175 | |
| 1176 | writel(tmp32, LPC_ENET_RXFILTER_CTRL(pldat->net_base)); |
| 1177 | |
| 1178 | |
| 1179 | /* Set initial hash table */ |
| 1180 | hashlo = 0x0; |
| 1181 | hashhi = 0x0; |
| 1182 | |
| 1183 | /* 64 bits : multicast address in hash table */ |
| 1184 | netdev_hw_addr_list_for_each(ha, mcptr) { |
| 1185 | hash_val = (ether_crc(6, ha->addr) >> 23) & 0x3F; |
| 1186 | |
| 1187 | if (hash_val >= 32) |
| 1188 | hashhi |= 1 << (hash_val - 32); |
| 1189 | else |
| 1190 | hashlo |= 1 << hash_val; |
| 1191 | } |
| 1192 | |
| 1193 | writel(hashlo, LPC_ENET_HASHFILTERL(pldat->net_base)); |
| 1194 | writel(hashhi, LPC_ENET_HASHFILTERH(pldat->net_base)); |
| 1195 | |
| 1196 | spin_unlock_irqrestore(&pldat->lock, flags); |
| 1197 | } |
| 1198 | |
| 1199 | static int lpc_eth_ioctl(struct net_device *ndev, struct ifreq *req, int cmd) |
| 1200 | { |
| 1201 | struct netdata_local *pldat = netdev_priv(ndev); |
| 1202 | struct phy_device *phydev = pldat->phy_dev; |
| 1203 | |
| 1204 | if (!netif_running(ndev)) |
| 1205 | return -EINVAL; |
| 1206 | |
| 1207 | if (!phydev) |
| 1208 | return -ENODEV; |
| 1209 | |
| 1210 | return phy_mii_ioctl(phydev, req, cmd); |
| 1211 | } |
| 1212 | |
| 1213 | static int lpc_eth_open(struct net_device *ndev) |
| 1214 | { |
| 1215 | struct netdata_local *pldat = netdev_priv(ndev); |
| 1216 | |
| 1217 | if (netif_msg_ifup(pldat)) |
| 1218 | dev_dbg(&pldat->pdev->dev, "enabling %s\n", ndev->name); |
| 1219 | |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1220 | __lpc_eth_clock_enable(pldat, true); |
| 1221 | |
Roland Stigge | aff88a0 | 2014-09-01 13:46:46 +0200 | [diff] [blame] | 1222 | /* Suspended PHY makes LPC ethernet core block, so resume now */ |
| 1223 | phy_resume(pldat->phy_dev); |
| 1224 | |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1225 | /* Reset and initialize */ |
| 1226 | __lpc_eth_reset(pldat); |
| 1227 | __lpc_eth_init(pldat); |
| 1228 | |
| 1229 | /* schedule a link state check */ |
| 1230 | phy_start(pldat->phy_dev); |
| 1231 | netif_start_queue(ndev); |
| 1232 | napi_enable(&pldat->napi); |
| 1233 | |
| 1234 | return 0; |
| 1235 | } |
| 1236 | |
| 1237 | /* |
| 1238 | * Ethtool ops |
| 1239 | */ |
| 1240 | static void lpc_eth_ethtool_getdrvinfo(struct net_device *ndev, |
| 1241 | struct ethtool_drvinfo *info) |
| 1242 | { |
Jiri Pirko | 7826d43 | 2013-01-06 00:44:26 +0000 | [diff] [blame] | 1243 | strlcpy(info->driver, MODNAME, sizeof(info->driver)); |
| 1244 | strlcpy(info->version, DRV_VERSION, sizeof(info->version)); |
| 1245 | strlcpy(info->bus_info, dev_name(ndev->dev.parent), |
| 1246 | sizeof(info->bus_info)); |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1247 | } |
| 1248 | |
| 1249 | static u32 lpc_eth_ethtool_getmsglevel(struct net_device *ndev) |
| 1250 | { |
| 1251 | struct netdata_local *pldat = netdev_priv(ndev); |
| 1252 | |
| 1253 | return pldat->msg_enable; |
| 1254 | } |
| 1255 | |
| 1256 | static void lpc_eth_ethtool_setmsglevel(struct net_device *ndev, u32 level) |
| 1257 | { |
| 1258 | struct netdata_local *pldat = netdev_priv(ndev); |
| 1259 | |
| 1260 | pldat->msg_enable = level; |
| 1261 | } |
| 1262 | |
| 1263 | static int lpc_eth_ethtool_getsettings(struct net_device *ndev, |
| 1264 | struct ethtool_cmd *cmd) |
| 1265 | { |
| 1266 | struct netdata_local *pldat = netdev_priv(ndev); |
| 1267 | struct phy_device *phydev = pldat->phy_dev; |
| 1268 | |
| 1269 | if (!phydev) |
| 1270 | return -EOPNOTSUPP; |
| 1271 | |
| 1272 | return phy_ethtool_gset(phydev, cmd); |
| 1273 | } |
| 1274 | |
| 1275 | static int lpc_eth_ethtool_setsettings(struct net_device *ndev, |
| 1276 | struct ethtool_cmd *cmd) |
| 1277 | { |
| 1278 | struct netdata_local *pldat = netdev_priv(ndev); |
| 1279 | struct phy_device *phydev = pldat->phy_dev; |
| 1280 | |
| 1281 | if (!phydev) |
| 1282 | return -EOPNOTSUPP; |
| 1283 | |
| 1284 | return phy_ethtool_sset(phydev, cmd); |
| 1285 | } |
| 1286 | |
| 1287 | static const struct ethtool_ops lpc_eth_ethtool_ops = { |
| 1288 | .get_drvinfo = lpc_eth_ethtool_getdrvinfo, |
| 1289 | .get_settings = lpc_eth_ethtool_getsettings, |
| 1290 | .set_settings = lpc_eth_ethtool_setsettings, |
| 1291 | .get_msglevel = lpc_eth_ethtool_getmsglevel, |
| 1292 | .set_msglevel = lpc_eth_ethtool_setmsglevel, |
| 1293 | .get_link = ethtool_op_get_link, |
| 1294 | }; |
| 1295 | |
| 1296 | static const struct net_device_ops lpc_netdev_ops = { |
| 1297 | .ndo_open = lpc_eth_open, |
| 1298 | .ndo_stop = lpc_eth_close, |
| 1299 | .ndo_start_xmit = lpc_eth_hard_start_xmit, |
| 1300 | .ndo_set_rx_mode = lpc_eth_set_multicast_list, |
| 1301 | .ndo_do_ioctl = lpc_eth_ioctl, |
| 1302 | .ndo_set_mac_address = lpc_set_mac_address, |
Joachim Eastwood | c867b55 | 2012-11-16 04:47:15 +0000 | [diff] [blame] | 1303 | .ndo_validate_addr = eth_validate_addr, |
Eric Dumazet | e304785 | 2012-06-10 23:24:00 +0000 | [diff] [blame] | 1304 | .ndo_change_mtu = eth_change_mtu, |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1305 | }; |
| 1306 | |
| 1307 | static int lpc_eth_drv_probe(struct platform_device *pdev) |
| 1308 | { |
| 1309 | struct resource *res; |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1310 | struct net_device *ndev; |
| 1311 | struct netdata_local *pldat; |
| 1312 | struct phy_device *phydev; |
| 1313 | dma_addr_t dma_handle; |
| 1314 | int irq, ret; |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 1315 | u32 tmp; |
| 1316 | |
| 1317 | /* Setup network interface for RMII or MII mode */ |
| 1318 | tmp = __raw_readl(LPC32XX_CLKPWR_MACCLK_CTRL); |
| 1319 | tmp &= ~LPC32XX_CLKPWR_MACCTRL_PINS_MSK; |
| 1320 | if (lpc_phy_interface_mode(&pdev->dev) == PHY_INTERFACE_MODE_MII) |
| 1321 | tmp |= LPC32XX_CLKPWR_MACCTRL_USE_MII_PINS; |
| 1322 | else |
| 1323 | tmp |= LPC32XX_CLKPWR_MACCTRL_USE_RMII_PINS; |
| 1324 | __raw_writel(tmp, LPC32XX_CLKPWR_MACCLK_CTRL); |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1325 | |
| 1326 | /* Get platform resources */ |
| 1327 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1328 | irq = platform_get_irq(pdev, 0); |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 1329 | if ((!res) || (irq < 0) || (irq >= NR_IRQS)) { |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1330 | dev_err(&pdev->dev, "error getting resources.\n"); |
| 1331 | ret = -ENXIO; |
| 1332 | goto err_exit; |
| 1333 | } |
| 1334 | |
| 1335 | /* Allocate net driver data structure */ |
| 1336 | ndev = alloc_etherdev(sizeof(struct netdata_local)); |
| 1337 | if (!ndev) { |
| 1338 | dev_err(&pdev->dev, "could not allocate device.\n"); |
| 1339 | ret = -ENOMEM; |
| 1340 | goto err_exit; |
| 1341 | } |
| 1342 | |
| 1343 | SET_NETDEV_DEV(ndev, &pdev->dev); |
| 1344 | |
| 1345 | pldat = netdev_priv(ndev); |
| 1346 | pldat->pdev = pdev; |
| 1347 | pldat->ndev = ndev; |
| 1348 | |
| 1349 | spin_lock_init(&pldat->lock); |
| 1350 | |
| 1351 | /* Save resources */ |
| 1352 | ndev->irq = irq; |
| 1353 | |
| 1354 | /* Get clock for the device */ |
| 1355 | pldat->clk = clk_get(&pdev->dev, NULL); |
| 1356 | if (IS_ERR(pldat->clk)) { |
| 1357 | dev_err(&pdev->dev, "error getting clock.\n"); |
| 1358 | ret = PTR_ERR(pldat->clk); |
| 1359 | goto err_out_free_dev; |
| 1360 | } |
| 1361 | |
| 1362 | /* Enable network clock */ |
| 1363 | __lpc_eth_clock_enable(pldat, true); |
| 1364 | |
| 1365 | /* Map IO space */ |
Benoit Taine | 9323b23 | 2014-06-03 12:45:59 +0200 | [diff] [blame] | 1366 | pldat->net_base = ioremap(res->start, resource_size(res)); |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1367 | if (!pldat->net_base) { |
| 1368 | dev_err(&pdev->dev, "failed to map registers\n"); |
| 1369 | ret = -ENOMEM; |
| 1370 | goto err_out_disable_clocks; |
| 1371 | } |
| 1372 | ret = request_irq(ndev->irq, __lpc_eth_interrupt, 0, |
| 1373 | ndev->name, ndev); |
| 1374 | if (ret) { |
| 1375 | dev_err(&pdev->dev, "error requesting interrupt.\n"); |
| 1376 | goto err_out_iounmap; |
| 1377 | } |
| 1378 | |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1379 | /* Setup driver functions */ |
| 1380 | ndev->netdev_ops = &lpc_netdev_ops; |
| 1381 | ndev->ethtool_ops = &lpc_eth_ethtool_ops; |
| 1382 | ndev->watchdog_timeo = msecs_to_jiffies(2500); |
| 1383 | |
| 1384 | /* Get size of DMA buffers/descriptors region */ |
| 1385 | pldat->dma_buff_size = (ENET_TX_DESC + ENET_RX_DESC) * (ENET_MAXF_SIZE + |
| 1386 | sizeof(struct txrx_desc_t) + sizeof(struct rx_status_t)); |
| 1387 | pldat->dma_buff_base_v = 0; |
| 1388 | |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 1389 | if (use_iram_for_net(&pldat->pdev->dev)) { |
| 1390 | dma_handle = LPC32XX_IRAM_BASE; |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1391 | if (pldat->dma_buff_size <= lpc32xx_return_iram_size()) |
| 1392 | pldat->dma_buff_base_v = |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 1393 | io_p2v(LPC32XX_IRAM_BASE); |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1394 | else |
| 1395 | netdev_err(ndev, |
| 1396 | "IRAM not big enough for net buffers, using SDRAM instead.\n"); |
| 1397 | } |
| 1398 | |
| 1399 | if (pldat->dma_buff_base_v == 0) { |
Russell King | b469357 | 2013-06-27 14:03:13 +0100 | [diff] [blame] | 1400 | ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); |
| 1401 | if (ret) |
| 1402 | goto err_out_free_irq; |
| 1403 | |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1404 | pldat->dma_buff_size = PAGE_ALIGN(pldat->dma_buff_size); |
| 1405 | |
| 1406 | /* Allocate a chunk of memory for the DMA ethernet buffers |
| 1407 | and descriptors */ |
| 1408 | pldat->dma_buff_base_v = |
| 1409 | dma_alloc_coherent(&pldat->pdev->dev, |
| 1410 | pldat->dma_buff_size, &dma_handle, |
| 1411 | GFP_KERNEL); |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1412 | if (pldat->dma_buff_base_v == NULL) { |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1413 | ret = -ENOMEM; |
| 1414 | goto err_out_free_irq; |
| 1415 | } |
| 1416 | } |
| 1417 | pldat->dma_buff_base_p = dma_handle; |
| 1418 | |
Benoit Taine | 9323b23 | 2014-06-03 12:45:59 +0200 | [diff] [blame] | 1419 | netdev_dbg(ndev, "IO address space :%pR\n", res); |
| 1420 | netdev_dbg(ndev, "IO address size :%d\n", resource_size(res)); |
stigge@antcom.de | b31525d | 2012-06-18 10:14:42 +0000 | [diff] [blame] | 1421 | netdev_dbg(ndev, "IO address (mapped) :0x%p\n", |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1422 | pldat->net_base); |
| 1423 | netdev_dbg(ndev, "IRQ number :%d\n", ndev->irq); |
| 1424 | netdev_dbg(ndev, "DMA buffer size :%d\n", pldat->dma_buff_size); |
| 1425 | netdev_dbg(ndev, "DMA buffer P address :0x%08x\n", |
| 1426 | pldat->dma_buff_base_p); |
| 1427 | netdev_dbg(ndev, "DMA buffer V address :0x%p\n", |
| 1428 | pldat->dma_buff_base_v); |
| 1429 | |
| 1430 | /* Get MAC address from current HW setting (POR state is all zeros) */ |
| 1431 | __lpc_get_mac(pldat, ndev->dev_addr); |
| 1432 | |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1433 | if (!is_valid_ether_addr(ndev->dev_addr)) { |
| 1434 | const char *macaddr = of_get_mac_address(pdev->dev.of_node); |
| 1435 | if (macaddr) |
| 1436 | memcpy(ndev->dev_addr, macaddr, ETH_ALEN); |
| 1437 | } |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1438 | if (!is_valid_ether_addr(ndev->dev_addr)) |
stigge@antcom.de | cdaf0b8 | 2012-03-28 12:36:26 +0000 | [diff] [blame] | 1439 | eth_hw_addr_random(ndev); |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1440 | |
| 1441 | /* Reset the ethernet controller */ |
| 1442 | __lpc_eth_reset(pldat); |
| 1443 | |
| 1444 | /* then shut everything down to save power */ |
| 1445 | __lpc_eth_shutdown(pldat); |
| 1446 | |
| 1447 | /* Set default parameters */ |
| 1448 | pldat->msg_enable = NETIF_MSG_LINK; |
| 1449 | |
| 1450 | /* Force an MII interface reset and clock setup */ |
| 1451 | __lpc_mii_mngt_reset(pldat); |
| 1452 | |
| 1453 | /* Force default PHY interface setup in chip, this will probably be |
| 1454 | changed by the PHY driver */ |
| 1455 | pldat->link = 0; |
| 1456 | pldat->speed = 100; |
| 1457 | pldat->duplex = DUPLEX_FULL; |
| 1458 | __lpc_params_setup(pldat); |
| 1459 | |
| 1460 | netif_napi_add(ndev, &pldat->napi, lpc_eth_poll, NAPI_WEIGHT); |
| 1461 | |
| 1462 | ret = register_netdev(ndev); |
| 1463 | if (ret) { |
| 1464 | dev_err(&pdev->dev, "Cannot register net device, aborting.\n"); |
| 1465 | goto err_out_dma_unmap; |
| 1466 | } |
| 1467 | platform_set_drvdata(pdev, ndev); |
| 1468 | |
Wei Yongjun | fa90b07 | 2013-03-20 02:21:48 +0000 | [diff] [blame] | 1469 | ret = lpc_mii_init(pldat); |
| 1470 | if (ret) |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1471 | goto err_out_unregister_netdev; |
| 1472 | |
| 1473 | netdev_info(ndev, "LPC mac at 0x%08x irq %d\n", |
| 1474 | res->start, ndev->irq); |
| 1475 | |
| 1476 | phydev = pldat->phy_dev; |
| 1477 | |
| 1478 | device_init_wakeup(&pdev->dev, 1); |
| 1479 | device_set_wakeup_enable(&pdev->dev, 0); |
| 1480 | |
| 1481 | return 0; |
| 1482 | |
| 1483 | err_out_unregister_netdev: |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1484 | unregister_netdev(ndev); |
| 1485 | err_out_dma_unmap: |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 1486 | if (!use_iram_for_net(&pldat->pdev->dev) || |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1487 | pldat->dma_buff_size > lpc32xx_return_iram_size()) |
| 1488 | dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size, |
| 1489 | pldat->dma_buff_base_v, |
| 1490 | pldat->dma_buff_base_p); |
| 1491 | err_out_free_irq: |
| 1492 | free_irq(ndev->irq, ndev); |
| 1493 | err_out_iounmap: |
| 1494 | iounmap(pldat->net_base); |
| 1495 | err_out_disable_clocks: |
Vladimir Zapolskiy | 33a8316 | 2015-10-01 00:37:43 +0300 | [diff] [blame] | 1496 | clk_disable_unprepare(pldat->clk); |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1497 | clk_put(pldat->clk); |
| 1498 | err_out_free_dev: |
| 1499 | free_netdev(ndev); |
| 1500 | err_exit: |
| 1501 | pr_err("%s: not found (%d).\n", MODNAME, ret); |
| 1502 | return ret; |
| 1503 | } |
| 1504 | |
| 1505 | static int lpc_eth_drv_remove(struct platform_device *pdev) |
| 1506 | { |
| 1507 | struct net_device *ndev = platform_get_drvdata(pdev); |
| 1508 | struct netdata_local *pldat = netdev_priv(ndev); |
| 1509 | |
| 1510 | unregister_netdev(ndev); |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1511 | |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 1512 | if (!use_iram_for_net(&pldat->pdev->dev) || |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1513 | pldat->dma_buff_size > lpc32xx_return_iram_size()) |
| 1514 | dma_free_coherent(&pldat->pdev->dev, pldat->dma_buff_size, |
| 1515 | pldat->dma_buff_base_v, |
| 1516 | pldat->dma_buff_base_p); |
| 1517 | free_irq(ndev->irq, ndev); |
| 1518 | iounmap(pldat->net_base); |
Peter Senna Tschudin | 57c10b6 | 2012-10-28 06:12:00 +0000 | [diff] [blame] | 1519 | mdiobus_unregister(pldat->mii_bus); |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1520 | mdiobus_free(pldat->mii_bus); |
Vladimir Zapolskiy | 33a8316 | 2015-10-01 00:37:43 +0300 | [diff] [blame] | 1521 | clk_disable_unprepare(pldat->clk); |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1522 | clk_put(pldat->clk); |
| 1523 | free_netdev(ndev); |
| 1524 | |
| 1525 | return 0; |
| 1526 | } |
| 1527 | |
| 1528 | #ifdef CONFIG_PM |
| 1529 | static int lpc_eth_drv_suspend(struct platform_device *pdev, |
| 1530 | pm_message_t state) |
| 1531 | { |
| 1532 | struct net_device *ndev = platform_get_drvdata(pdev); |
| 1533 | struct netdata_local *pldat = netdev_priv(ndev); |
| 1534 | |
| 1535 | if (device_may_wakeup(&pdev->dev)) |
| 1536 | enable_irq_wake(ndev->irq); |
| 1537 | |
| 1538 | if (ndev) { |
| 1539 | if (netif_running(ndev)) { |
| 1540 | netif_device_detach(ndev); |
| 1541 | __lpc_eth_shutdown(pldat); |
Vladimir Zapolskiy | 33a8316 | 2015-10-01 00:37:43 +0300 | [diff] [blame] | 1542 | clk_disable_unprepare(pldat->clk); |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1543 | |
| 1544 | /* |
| 1545 | * Reset again now clock is disable to be sure |
| 1546 | * EMC_MDC is down |
| 1547 | */ |
| 1548 | __lpc_eth_reset(pldat); |
| 1549 | } |
| 1550 | } |
| 1551 | |
| 1552 | return 0; |
| 1553 | } |
| 1554 | |
| 1555 | static int lpc_eth_drv_resume(struct platform_device *pdev) |
| 1556 | { |
| 1557 | struct net_device *ndev = platform_get_drvdata(pdev); |
| 1558 | struct netdata_local *pldat; |
| 1559 | |
| 1560 | if (device_may_wakeup(&pdev->dev)) |
| 1561 | disable_irq_wake(ndev->irq); |
| 1562 | |
| 1563 | if (ndev) { |
| 1564 | if (netif_running(ndev)) { |
| 1565 | pldat = netdev_priv(ndev); |
| 1566 | |
| 1567 | /* Enable interface clock */ |
| 1568 | clk_enable(pldat->clk); |
| 1569 | |
| 1570 | /* Reset and initialize */ |
| 1571 | __lpc_eth_reset(pldat); |
| 1572 | __lpc_eth_init(pldat); |
| 1573 | |
| 1574 | netif_device_attach(ndev); |
| 1575 | } |
| 1576 | } |
| 1577 | |
| 1578 | return 0; |
| 1579 | } |
| 1580 | #endif |
| 1581 | |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 1582 | #ifdef CONFIG_OF |
| 1583 | static const struct of_device_id lpc_eth_match[] = { |
| 1584 | { .compatible = "nxp,lpc-eth" }, |
| 1585 | { } |
| 1586 | }; |
| 1587 | MODULE_DEVICE_TABLE(of, lpc_eth_match); |
| 1588 | #endif |
| 1589 | |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1590 | static struct platform_driver lpc_eth_driver = { |
| 1591 | .probe = lpc_eth_drv_probe, |
Bill Pemberton | 2152452 | 2012-12-03 09:23:21 -0500 | [diff] [blame] | 1592 | .remove = lpc_eth_drv_remove, |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1593 | #ifdef CONFIG_PM |
| 1594 | .suspend = lpc_eth_drv_suspend, |
| 1595 | .resume = lpc_eth_drv_resume, |
| 1596 | #endif |
| 1597 | .driver = { |
| 1598 | .name = MODNAME, |
Roland Stigge | 4de02e4 | 2012-04-22 12:01:19 +0200 | [diff] [blame] | 1599 | .of_match_table = of_match_ptr(lpc_eth_match), |
stigge@antcom.de | b737011 | 2012-03-08 11:49:17 +0000 | [diff] [blame] | 1600 | }, |
| 1601 | }; |
| 1602 | |
| 1603 | module_platform_driver(lpc_eth_driver); |
| 1604 | |
| 1605 | MODULE_AUTHOR("Kevin Wells <kevin.wells@nxp.com>"); |
| 1606 | MODULE_AUTHOR("Roland Stigge <stigge@antcom.de>"); |
| 1607 | MODULE_DESCRIPTION("LPC Ethernet Driver"); |
| 1608 | MODULE_LICENSE("GPL"); |