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Linus Walleijbd41b992009-04-23 21:15:04 +01001/*
Grant Likelyc103de22011-06-04 18:38:28 -06002 * U300 GPIO module.
Linus Walleijbd41b992009-04-23 21:15:04 +01003 *
Linus Walleij04b13de2012-08-13 10:36:55 +02004 * Copyright (C) 2007-2012 ST-Ericsson AB
Linus Walleijbd41b992009-04-23 21:15:04 +01005 * License terms: GNU General Public License (GPL) version 2
Linus Walleijbd41b992009-04-23 21:15:04 +01006 * COH 901 571/3 - Used in DB3210 (U365 2.0) and DB3350 (U335 1.0)
Linus Walleijcc890cd2011-09-08 09:04:51 +01007 * Author: Linus Walleij <linus.walleij@linaro.org>
Linus Walleijbd41b992009-04-23 21:15:04 +01008 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
Linus Walleijbd41b992009-04-23 21:15:04 +01009 */
10#include <linux/module.h>
Linus Walleijcc890cd2011-09-08 09:04:51 +010011#include <linux/irq.h>
Linus Walleijbd41b992009-04-23 21:15:04 +010012#include <linux/interrupt.h>
13#include <linux/delay.h>
14#include <linux/errno.h>
15#include <linux/io.h>
Linus Walleija6c45b92012-10-17 18:31:20 +020016#include <linux/irqdomain.h>
Linus Walleijbd41b992009-04-23 21:15:04 +010017#include <linux/clk.h>
18#include <linux/err.h>
19#include <linux/platform_device.h>
20#include <linux/gpio.h>
Linus Walleijcc890cd2011-09-08 09:04:51 +010021#include <linux/list.h>
22#include <linux/slab.h>
Linus Walleij28a8d142012-02-09 01:52:22 +010023#include <linux/pinctrl/consumer.h>
Linus Walleijdc0b1aa2011-11-16 21:58:10 +010024#include <linux/pinctrl/pinconf-generic.h>
Linus Walleijdc0b1aa2011-11-16 21:58:10 +010025#include "pinctrl-coh901.h"
Linus Walleijbd41b992009-04-23 21:15:04 +010026
Linus Walleij04b13de2012-08-13 10:36:55 +020027#define U300_GPIO_PORT_STRIDE (0x30)
Linus Walleijcc890cd2011-09-08 09:04:51 +010028/*
Linus Walleij04b13de2012-08-13 10:36:55 +020029 * Control Register 32bit (R/W)
30 * bit 15-9 (mask 0x0000FE00) contains the number of cores. 8*cores
31 * gives the number of GPIO pins.
32 * bit 8-2 (mask 0x000001FC) contains the core version ID.
Linus Walleijcc890cd2011-09-08 09:04:51 +010033 */
Linus Walleij04b13de2012-08-13 10:36:55 +020034#define U300_GPIO_CR (0x00)
35#define U300_GPIO_CR_SYNC_SEL_ENABLE (0x00000002UL)
36#define U300_GPIO_CR_BLOCK_CLKRQ_ENABLE (0x00000001UL)
37#define U300_GPIO_PXPDIR (0x04)
38#define U300_GPIO_PXPDOR (0x08)
39#define U300_GPIO_PXPCR (0x0C)
Linus Walleijcc890cd2011-09-08 09:04:51 +010040#define U300_GPIO_PXPCR_ALL_PINS_MODE_MASK (0x0000FFFFUL)
41#define U300_GPIO_PXPCR_PIN_MODE_MASK (0x00000003UL)
42#define U300_GPIO_PXPCR_PIN_MODE_SHIFT (0x00000002UL)
43#define U300_GPIO_PXPCR_PIN_MODE_INPUT (0x00000000UL)
44#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL (0x00000001UL)
45#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN (0x00000002UL)
46#define U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE (0x00000003UL)
Linus Walleij04b13de2012-08-13 10:36:55 +020047#define U300_GPIO_PXPER (0x10)
48#define U300_GPIO_PXPER_ALL_PULL_UP_DISABLE_MASK (0x000000FFUL)
49#define U300_GPIO_PXPER_PULL_UP_DISABLE (0x00000001UL)
50#define U300_GPIO_PXIEV (0x14)
51#define U300_GPIO_PXIEN (0x18)
52#define U300_GPIO_PXIFR (0x1C)
53#define U300_GPIO_PXICR (0x20)
Linus Walleijcc890cd2011-09-08 09:04:51 +010054#define U300_GPIO_PXICR_ALL_IRQ_CONFIG_MASK (0x000000FFUL)
55#define U300_GPIO_PXICR_IRQ_CONFIG_MASK (0x00000001UL)
56#define U300_GPIO_PXICR_IRQ_CONFIG_FALLING_EDGE (0x00000000UL)
57#define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE (0x00000001UL)
Linus Walleijcc890cd2011-09-08 09:04:51 +010058
59/* 8 bits per port, no version has more than 7 ports */
Linus Walleijb263e9b2013-05-23 20:09:43 +020060#define U300_GPIO_NUM_PORTS 7
Linus Walleijcc890cd2011-09-08 09:04:51 +010061#define U300_GPIO_PINS_PER_PORT 8
Linus Walleijb263e9b2013-05-23 20:09:43 +020062#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS)
Linus Walleijcc890cd2011-09-08 09:04:51 +010063
64struct u300_gpio {
65 struct gpio_chip chip;
66 struct list_head port_list;
67 struct clk *clk;
Linus Walleijcc890cd2011-09-08 09:04:51 +010068 void __iomem *base;
69 struct device *dev;
Linus Walleijcc890cd2011-09-08 09:04:51 +010070 u32 stride;
71 /* Register offsets */
72 u32 pcr;
73 u32 dor;
74 u32 dir;
75 u32 per;
76 u32 icr;
77 u32 ien;
78 u32 iev;
79};
Linus Walleijbd41b992009-04-23 21:15:04 +010080
81struct u300_gpio_port {
Linus Walleijcc890cd2011-09-08 09:04:51 +010082 struct list_head node;
83 struct u300_gpio *gpio;
84 char name[8];
Linus Walleija6c45b92012-10-17 18:31:20 +020085 struct irq_domain *domain;
Linus Walleijbd41b992009-04-23 21:15:04 +010086 int irq;
87 int number;
Linus Walleijcc890cd2011-09-08 09:04:51 +010088 u8 toggle_edge_mode;
Linus Walleijbd41b992009-04-23 21:15:04 +010089};
90
Linus Walleijcc890cd2011-09-08 09:04:51 +010091/*
92 * Macro to expand to read a specific register found in the "gpio"
93 * struct. It requires the struct u300_gpio *gpio variable to exist in
94 * its context. It calculates the port offset from the given pin
95 * offset, muliplies by the port stride and adds the register offset
96 * so it provides a pointer to the desired register.
97 */
98#define U300_PIN_REG(pin, reg) \
99 (gpio->base + (pin >> 3) * gpio->stride + gpio->reg)
Linus Walleijbd41b992009-04-23 21:15:04 +0100100
Linus Walleijcc890cd2011-09-08 09:04:51 +0100101/*
102 * Provides a bitmask for a specific gpio pin inside an 8-bit GPIO
103 * register.
104 */
105#define U300_PIN_BIT(pin) \
106 (1 << (pin & 0x07))
Linus Walleijbd41b992009-04-23 21:15:04 +0100107
Linus Walleijcc890cd2011-09-08 09:04:51 +0100108struct u300_gpio_confdata {
109 u16 bias_mode;
110 bool output;
111 int outval;
Linus Walleijbd41b992009-04-23 21:15:04 +0100112};
113
Linus Walleijcc890cd2011-09-08 09:04:51 +0100114#define U300_FLOATING_INPUT { \
Linus Walleija050b3e2011-11-16 20:10:09 +0100115 .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
Linus Walleijcc890cd2011-09-08 09:04:51 +0100116 .output = false, \
117}
Linus Walleijbd41b992009-04-23 21:15:04 +0100118
Linus Walleijcc890cd2011-09-08 09:04:51 +0100119#define U300_PULL_UP_INPUT { \
Linus Walleija050b3e2011-11-16 20:10:09 +0100120 .bias_mode = PIN_CONFIG_BIAS_PULL_UP, \
Linus Walleijcc890cd2011-09-08 09:04:51 +0100121 .output = false, \
122}
Linus Walleijbd41b992009-04-23 21:15:04 +0100123
Linus Walleijcc890cd2011-09-08 09:04:51 +0100124#define U300_OUTPUT_LOW { \
125 .output = true, \
126 .outval = 0, \
127}
Linus Walleijbd41b992009-04-23 21:15:04 +0100128
Linus Walleijcc890cd2011-09-08 09:04:51 +0100129#define U300_OUTPUT_HIGH { \
130 .output = true, \
131 .outval = 1, \
132}
Linus Walleijbd41b992009-04-23 21:15:04 +0100133
Linus Walleijbd41b992009-04-23 21:15:04 +0100134/* Initial configuration */
Uwe Kleine-König122dbe72012-03-30 22:04:51 +0200135static const struct __initconst u300_gpio_confdata
Linus Walleijb263e9b2013-05-23 20:09:43 +0200136bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
Linus Walleijbd41b992009-04-23 21:15:04 +0100137 /* Port 0, pins 0-7 */
138 {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100139 U300_FLOATING_INPUT,
140 U300_OUTPUT_HIGH,
141 U300_FLOATING_INPUT,
142 U300_OUTPUT_LOW,
143 U300_OUTPUT_LOW,
144 U300_OUTPUT_LOW,
145 U300_OUTPUT_LOW,
146 U300_OUTPUT_LOW,
Linus Walleijbd41b992009-04-23 21:15:04 +0100147 },
148 /* Port 1, pins 0-7 */
149 {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100150 U300_OUTPUT_LOW,
151 U300_OUTPUT_LOW,
152 U300_OUTPUT_LOW,
153 U300_PULL_UP_INPUT,
154 U300_FLOATING_INPUT,
155 U300_OUTPUT_HIGH,
156 U300_OUTPUT_LOW,
157 U300_OUTPUT_LOW,
Linus Walleijbd41b992009-04-23 21:15:04 +0100158 },
159 /* Port 2, pins 0-7 */
160 {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100161 U300_FLOATING_INPUT,
162 U300_FLOATING_INPUT,
163 U300_FLOATING_INPUT,
164 U300_FLOATING_INPUT,
165 U300_OUTPUT_LOW,
166 U300_PULL_UP_INPUT,
167 U300_OUTPUT_LOW,
168 U300_PULL_UP_INPUT,
Linus Walleijbd41b992009-04-23 21:15:04 +0100169 },
170 /* Port 3, pins 0-7 */
171 {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100172 U300_PULL_UP_INPUT,
173 U300_OUTPUT_LOW,
174 U300_FLOATING_INPUT,
175 U300_FLOATING_INPUT,
176 U300_FLOATING_INPUT,
177 U300_FLOATING_INPUT,
178 U300_FLOATING_INPUT,
179 U300_FLOATING_INPUT,
Linus Walleijbd41b992009-04-23 21:15:04 +0100180 },
181 /* Port 4, pins 0-7 */
182 {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100183 U300_FLOATING_INPUT,
184 U300_FLOATING_INPUT,
185 U300_FLOATING_INPUT,
186 U300_FLOATING_INPUT,
187 U300_FLOATING_INPUT,
188 U300_FLOATING_INPUT,
189 U300_FLOATING_INPUT,
190 U300_FLOATING_INPUT,
Linus Walleijbd41b992009-04-23 21:15:04 +0100191 },
192 /* Port 5, pins 0-7 */
193 {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100194 U300_FLOATING_INPUT,
195 U300_FLOATING_INPUT,
196 U300_FLOATING_INPUT,
197 U300_FLOATING_INPUT,
198 U300_FLOATING_INPUT,
199 U300_FLOATING_INPUT,
200 U300_FLOATING_INPUT,
201 U300_FLOATING_INPUT,
Linus Walleijbd41b992009-04-23 21:15:04 +0100202 },
203 /* Port 6, pind 0-7 */
204 {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100205 U300_FLOATING_INPUT,
206 U300_FLOATING_INPUT,
207 U300_FLOATING_INPUT,
208 U300_FLOATING_INPUT,
209 U300_FLOATING_INPUT,
210 U300_FLOATING_INPUT,
211 U300_FLOATING_INPUT,
212 U300_FLOATING_INPUT,
Linus Walleijbd41b992009-04-23 21:15:04 +0100213 }
Linus Walleijcc890cd2011-09-08 09:04:51 +0100214};
Linus Walleijbd41b992009-04-23 21:15:04 +0100215
Linus Walleijcc890cd2011-09-08 09:04:51 +0100216/**
217 * to_u300_gpio() - get the pointer to u300_gpio
218 * @chip: the gpio chip member of the structure u300_gpio
Linus Walleijbd41b992009-04-23 21:15:04 +0100219 */
Linus Walleijcc890cd2011-09-08 09:04:51 +0100220static inline struct u300_gpio *to_u300_gpio(struct gpio_chip *chip)
Linus Walleijbd41b992009-04-23 21:15:04 +0100221{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100222 return container_of(chip, struct u300_gpio, chip);
Linus Walleijbd41b992009-04-23 21:15:04 +0100223}
Linus Walleijbd41b992009-04-23 21:15:04 +0100224
Linus Walleijb4e3ac72011-11-16 10:24:39 +0100225static int u300_gpio_request(struct gpio_chip *chip, unsigned offset)
226{
227 /*
228 * Map back to global GPIO space and request muxing, the direction
229 * parameter does not matter for this controller.
230 */
231 int gpio = chip->base + offset;
232
Linus Walleije93bcee2012-02-09 07:23:28 +0100233 return pinctrl_request_gpio(gpio);
Linus Walleijb4e3ac72011-11-16 10:24:39 +0100234}
235
236static void u300_gpio_free(struct gpio_chip *chip, unsigned offset)
237{
238 int gpio = chip->base + offset;
239
Linus Walleije93bcee2012-02-09 07:23:28 +0100240 pinctrl_free_gpio(gpio);
Linus Walleijb4e3ac72011-11-16 10:24:39 +0100241}
242
Linus Walleijcc890cd2011-09-08 09:04:51 +0100243static int u300_gpio_get(struct gpio_chip *chip, unsigned offset)
Linus Walleijbd41b992009-04-23 21:15:04 +0100244{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100245 struct u300_gpio *gpio = to_u300_gpio(chip);
Linus Walleijbd41b992009-04-23 21:15:04 +0100246
Linus Walleijcc890cd2011-09-08 09:04:51 +0100247 return readl(U300_PIN_REG(offset, dir)) & U300_PIN_BIT(offset);
Linus Walleijbd41b992009-04-23 21:15:04 +0100248}
Linus Walleijbd41b992009-04-23 21:15:04 +0100249
Linus Walleijcc890cd2011-09-08 09:04:51 +0100250static void u300_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
Linus Walleijee179622009-09-28 12:36:18 +0100251{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100252 struct u300_gpio *gpio = to_u300_gpio(chip);
253 unsigned long flags;
254 u32 val;
Linus Walleijee179622009-09-28 12:36:18 +0100255
Linus Walleijcc890cd2011-09-08 09:04:51 +0100256 local_irq_save(flags);
257
258 val = readl(U300_PIN_REG(offset, dor));
259 if (value)
260 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
Linus Walleijbd41b992009-04-23 21:15:04 +0100261 else
Linus Walleijcc890cd2011-09-08 09:04:51 +0100262 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, dor));
Linus Walleijbd41b992009-04-23 21:15:04 +0100263
Linus Walleijbd41b992009-04-23 21:15:04 +0100264 local_irq_restore(flags);
265}
Linus Walleijbd41b992009-04-23 21:15:04 +0100266
Linus Walleijcc890cd2011-09-08 09:04:51 +0100267static int u300_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
Linus Walleijbd41b992009-04-23 21:15:04 +0100268{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100269 struct u300_gpio *gpio = to_u300_gpio(chip);
Linus Walleijbd41b992009-04-23 21:15:04 +0100270 unsigned long flags;
271 u32 val;
272
Linus Walleijbd41b992009-04-23 21:15:04 +0100273 local_irq_save(flags);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100274 val = readl(U300_PIN_REG(offset, pcr));
275 /* Mask out this pin, note 2 bits per setting */
276 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
277 writel(val, U300_PIN_REG(offset, pcr));
Linus Walleijbd41b992009-04-23 21:15:04 +0100278 local_irq_restore(flags);
279 return 0;
280}
Linus Walleijbd41b992009-04-23 21:15:04 +0100281
Linus Walleijcc890cd2011-09-08 09:04:51 +0100282static int u300_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
283 int value)
Linus Walleijbd41b992009-04-23 21:15:04 +0100284{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100285 struct u300_gpio *gpio = to_u300_gpio(chip);
Linus Walleijbd41b992009-04-23 21:15:04 +0100286 unsigned long flags;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100287 u32 oldmode;
Linus Walleijbd41b992009-04-23 21:15:04 +0100288 u32 val;
289
Linus Walleijbd41b992009-04-23 21:15:04 +0100290 local_irq_save(flags);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100291 val = readl(U300_PIN_REG(offset, pcr));
Linus Walleijbd41b992009-04-23 21:15:04 +0100292 /*
Linus Walleijcc890cd2011-09-08 09:04:51 +0100293 * Drive mode must be set by the special mode set function, set
294 * push/pull mode by default if no mode has been selected.
Linus Walleijbd41b992009-04-23 21:15:04 +0100295 */
Linus Walleijcc890cd2011-09-08 09:04:51 +0100296 oldmode = val & (U300_GPIO_PXPCR_PIN_MODE_MASK <<
297 ((offset & 0x07) << 1));
298 /* mode = 0 means input, else some mode is already set */
299 if (oldmode == 0) {
300 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK <<
301 ((offset & 0x07) << 1));
302 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
303 << ((offset & 0x07) << 1));
304 writel(val, U300_PIN_REG(offset, pcr));
305 }
306 u300_gpio_set(chip, offset, value);
Linus Walleijbd41b992009-04-23 21:15:04 +0100307 local_irq_restore(flags);
308 return 0;
309}
Linus Walleijbd41b992009-04-23 21:15:04 +0100310
Linus Walleijcc890cd2011-09-08 09:04:51 +0100311static int u300_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
Linus Walleijbd41b992009-04-23 21:15:04 +0100312{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100313 struct u300_gpio *gpio = to_u300_gpio(chip);
Linus Walleija6c45b92012-10-17 18:31:20 +0200314 int portno = offset >> 3;
315 struct u300_gpio_port *port = NULL;
316 struct list_head *p;
317 int retirq;
Axel Lin28d0c142013-03-29 00:18:12 +0800318 bool found = false;
Linus Walleijbd41b992009-04-23 21:15:04 +0100319
Linus Walleija6c45b92012-10-17 18:31:20 +0200320 list_for_each(p, &gpio->port_list) {
321 port = list_entry(p, struct u300_gpio_port, node);
Axel Lin28d0c142013-03-29 00:18:12 +0800322 if (port->number == portno) {
323 found = true;
Linus Walleija6c45b92012-10-17 18:31:20 +0200324 break;
Axel Lin28d0c142013-03-29 00:18:12 +0800325 }
Linus Walleija6c45b92012-10-17 18:31:20 +0200326 }
Axel Lin28d0c142013-03-29 00:18:12 +0800327 if (!found) {
Linus Walleija6c45b92012-10-17 18:31:20 +0200328 dev_err(gpio->dev, "could not locate port for GPIO %d IRQ\n",
329 offset);
330 return -EINVAL;
331 }
332
333 /*
334 * The local hwirqs on the port are the lower three bits, there
335 * are exactly 8 IRQs per port since they are 8-bit
336 */
337 retirq = irq_find_mapping(port->domain, (offset & 0x7));
338
339 dev_dbg(gpio->dev, "request IRQ for GPIO %d, return %d from port %d\n",
340 offset, retirq, port->number);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100341 return retirq;
Linus Walleijbd41b992009-04-23 21:15:04 +0100342}
Linus Walleijbd41b992009-04-23 21:15:04 +0100343
Linus Walleijdc0b1aa2011-11-16 21:58:10 +0100344/* Returning -EINVAL means "supported but not available" */
345int u300_gpio_config_get(struct gpio_chip *chip,
346 unsigned offset,
347 unsigned long *config)
348{
349 struct u300_gpio *gpio = to_u300_gpio(chip);
350 enum pin_config_param param = (enum pin_config_param) *config;
351 bool biasmode;
352 u32 drmode;
353
354 /* One bit per pin, clamp to bool range */
355 biasmode = !!(readl(U300_PIN_REG(offset, per)) & U300_PIN_BIT(offset));
356
357 /* Mask out the two bits for this pin and shift to bits 0,1 */
358 drmode = readl(U300_PIN_REG(offset, pcr));
359 drmode &= (U300_GPIO_PXPCR_PIN_MODE_MASK << ((offset & 0x07) << 1));
360 drmode >>= ((offset & 0x07) << 1);
361
Sachin Kamat8b0ef252013-03-15 10:39:52 +0530362 switch (param) {
Linus Walleijdc0b1aa2011-11-16 21:58:10 +0100363 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
364 *config = 0;
365 if (biasmode)
366 return 0;
367 else
368 return -EINVAL;
369 break;
370 case PIN_CONFIG_BIAS_PULL_UP:
371 *config = 0;
372 if (!biasmode)
373 return 0;
374 else
375 return -EINVAL;
376 break;
377 case PIN_CONFIG_DRIVE_PUSH_PULL:
378 *config = 0;
379 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL)
380 return 0;
381 else
382 return -EINVAL;
383 break;
384 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
385 *config = 0;
386 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN)
387 return 0;
388 else
389 return -EINVAL;
390 break;
391 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
392 *config = 0;
393 if (drmode == U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE)
394 return 0;
395 else
396 return -EINVAL;
397 break;
398 default:
399 break;
400 }
401 return -ENOTSUPP;
402}
403
404int u300_gpio_config_set(struct gpio_chip *chip, unsigned offset,
405 enum pin_config_param param)
Linus Walleijbd41b992009-04-23 21:15:04 +0100406{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100407 struct u300_gpio *gpio = to_u300_gpio(chip);
Linus Walleijbd41b992009-04-23 21:15:04 +0100408 unsigned long flags;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100409 u32 val;
Linus Walleijbd41b992009-04-23 21:15:04 +0100410
411 local_irq_save(flags);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100412 switch (param) {
Linus Walleija050b3e2011-11-16 20:10:09 +0100413 case PIN_CONFIG_BIAS_DISABLE:
414 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
Linus Walleijcc890cd2011-09-08 09:04:51 +0100415 val = readl(U300_PIN_REG(offset, per));
416 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
417 break;
Linus Walleija050b3e2011-11-16 20:10:09 +0100418 case PIN_CONFIG_BIAS_PULL_UP:
Linus Walleijcc890cd2011-09-08 09:04:51 +0100419 val = readl(U300_PIN_REG(offset, per));
420 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, per));
421 break;
Linus Walleija050b3e2011-11-16 20:10:09 +0100422 case PIN_CONFIG_DRIVE_PUSH_PULL:
Linus Walleijcc890cd2011-09-08 09:04:51 +0100423 val = readl(U300_PIN_REG(offset, pcr));
424 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
425 << ((offset & 0x07) << 1));
426 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_PUSH_PULL
427 << ((offset & 0x07) << 1));
428 writel(val, U300_PIN_REG(offset, pcr));
429 break;
Linus Walleija050b3e2011-11-16 20:10:09 +0100430 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
Linus Walleijcc890cd2011-09-08 09:04:51 +0100431 val = readl(U300_PIN_REG(offset, pcr));
432 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
433 << ((offset & 0x07) << 1));
434 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_DRAIN
435 << ((offset & 0x07) << 1));
436 writel(val, U300_PIN_REG(offset, pcr));
437 break;
Linus Walleija050b3e2011-11-16 20:10:09 +0100438 case PIN_CONFIG_DRIVE_OPEN_SOURCE:
Linus Walleijcc890cd2011-09-08 09:04:51 +0100439 val = readl(U300_PIN_REG(offset, pcr));
440 val &= ~(U300_GPIO_PXPCR_PIN_MODE_MASK
441 << ((offset & 0x07) << 1));
442 val |= (U300_GPIO_PXPCR_PIN_MODE_OUTPUT_OPEN_SOURCE
443 << ((offset & 0x07) << 1));
444 writel(val, U300_PIN_REG(offset, pcr));
445 break;
446 default:
Linus Walleijbd41b992009-04-23 21:15:04 +0100447 local_irq_restore(flags);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100448 dev_err(gpio->dev, "illegal configuration requested\n");
449 return -EINVAL;
450 }
451 local_irq_restore(flags);
452 return 0;
453}
454
455static struct gpio_chip u300_gpio_chip = {
456 .label = "u300-gpio-chip",
457 .owner = THIS_MODULE,
Linus Walleijb4e3ac72011-11-16 10:24:39 +0100458 .request = u300_gpio_request,
459 .free = u300_gpio_free,
Linus Walleijcc890cd2011-09-08 09:04:51 +0100460 .get = u300_gpio_get,
461 .set = u300_gpio_set,
462 .direction_input = u300_gpio_direction_input,
463 .direction_output = u300_gpio_direction_output,
464 .to_irq = u300_gpio_to_irq,
465};
466
467static void u300_toggle_trigger(struct u300_gpio *gpio, unsigned offset)
468{
469 u32 val;
470
471 val = readl(U300_PIN_REG(offset, icr));
472 /* Set mode depending on state */
473 if (u300_gpio_get(&gpio->chip, offset)) {
474 /* High now, let's trigger on falling edge next then */
475 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
476 dev_dbg(gpio->dev, "next IRQ on falling edge on pin %d\n",
477 offset);
478 } else {
479 /* Low now, let's trigger on rising edge next then */
480 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
481 dev_dbg(gpio->dev, "next IRQ on rising edge on pin %d\n",
482 offset);
483 }
484}
485
486static int u300_gpio_irq_type(struct irq_data *d, unsigned trigger)
487{
488 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
489 struct u300_gpio *gpio = port->gpio;
Linus Walleija6c45b92012-10-17 18:31:20 +0200490 int offset = (port->number << 3) + d->hwirq;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100491 u32 val;
492
493 if ((trigger & IRQF_TRIGGER_RISING) &&
494 (trigger & IRQF_TRIGGER_FALLING)) {
495 /*
496 * The GPIO block can only trigger on falling OR rising edges,
497 * not both. So we need to toggle the mode whenever the pin
498 * goes from one state to the other with a special state flag
499 */
500 dev_dbg(gpio->dev,
501 "trigger on both rising and falling edge on pin %d\n",
502 offset);
503 port->toggle_edge_mode |= U300_PIN_BIT(offset);
504 u300_toggle_trigger(gpio, offset);
505 } else if (trigger & IRQF_TRIGGER_RISING) {
506 dev_dbg(gpio->dev, "trigger on rising edge on pin %d\n",
507 offset);
508 val = readl(U300_PIN_REG(offset, icr));
509 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
510 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
511 } else if (trigger & IRQF_TRIGGER_FALLING) {
512 dev_dbg(gpio->dev, "trigger on falling edge on pin %d\n",
513 offset);
514 val = readl(U300_PIN_REG(offset, icr));
515 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, icr));
516 port->toggle_edge_mode &= ~U300_PIN_BIT(offset);
Linus Walleijbd41b992009-04-23 21:15:04 +0100517 }
518
Linus Walleijcc890cd2011-09-08 09:04:51 +0100519 return 0;
520}
Linus Walleijbd41b992009-04-23 21:15:04 +0100521
Linus Walleijcc890cd2011-09-08 09:04:51 +0100522static void u300_gpio_irq_enable(struct irq_data *d)
523{
524 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
525 struct u300_gpio *gpio = port->gpio;
Linus Walleija6c45b92012-10-17 18:31:20 +0200526 int offset = (port->number << 3) + d->hwirq;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100527 u32 val;
528 unsigned long flags;
529
Linus Walleija6c45b92012-10-17 18:31:20 +0200530 dev_dbg(gpio->dev, "enable IRQ for hwirq %lu on port %s, offset %d\n",
531 d->hwirq, port->name, offset);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100532 local_irq_save(flags);
533 val = readl(U300_PIN_REG(offset, ien));
534 writel(val | U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
535 local_irq_restore(flags);
536}
537
538static void u300_gpio_irq_disable(struct irq_data *d)
539{
540 struct u300_gpio_port *port = irq_data_get_irq_chip_data(d);
541 struct u300_gpio *gpio = port->gpio;
Linus Walleija6c45b92012-10-17 18:31:20 +0200542 int offset = (port->number << 3) + d->hwirq;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100543 u32 val;
544 unsigned long flags;
545
546 local_irq_save(flags);
547 val = readl(U300_PIN_REG(offset, ien));
548 writel(val & ~U300_PIN_BIT(offset), U300_PIN_REG(offset, ien));
549 local_irq_restore(flags);
550}
551
552static struct irq_chip u300_gpio_irqchip = {
553 .name = "u300-gpio-irqchip",
554 .irq_enable = u300_gpio_irq_enable,
555 .irq_disable = u300_gpio_irq_disable,
556 .irq_set_type = u300_gpio_irq_type,
557
558};
559
560static void u300_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
561{
562 struct u300_gpio_port *port = irq_get_handler_data(irq);
563 struct u300_gpio *gpio = port->gpio;
564 int pinoffset = port->number << 3; /* get the right stride */
565 unsigned long val;
566
567 desc->irq_data.chip->irq_ack(&desc->irq_data);
568 /* Read event register */
569 val = readl(U300_PIN_REG(pinoffset, iev));
570 /* Mask relevant bits */
571 val &= 0xFFU; /* 8 bits per port */
572 /* ACK IRQ (clear event) */
573 writel(val, U300_PIN_REG(pinoffset, iev));
574
575 /* Call IRQ handler */
576 if (val != 0) {
577 int irqoffset;
578
579 for_each_set_bit(irqoffset, &val, U300_GPIO_PINS_PER_PORT) {
Linus Walleija6c45b92012-10-17 18:31:20 +0200580 int pin_irq = irq_find_mapping(port->domain, irqoffset);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100581 int offset = pinoffset + irqoffset;
582
583 dev_dbg(gpio->dev, "GPIO IRQ %d on pin %d\n",
584 pin_irq, offset);
585 generic_handle_irq(pin_irq);
586 /*
587 * Triggering IRQ on both rising and falling edge
588 * needs mockery
589 */
590 if (port->toggle_edge_mode & U300_PIN_BIT(offset))
591 u300_toggle_trigger(gpio, offset);
Linus Walleijbd41b992009-04-23 21:15:04 +0100592 }
593 }
594
Linus Walleijcc890cd2011-09-08 09:04:51 +0100595 desc->irq_data.chip->irq_unmask(&desc->irq_data);
Linus Walleijbd41b992009-04-23 21:15:04 +0100596}
597
Linus Walleijcc890cd2011-09-08 09:04:51 +0100598static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
599 int offset,
600 const struct u300_gpio_confdata *conf)
Linus Walleijbd41b992009-04-23 21:15:04 +0100601{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100602 /* Set mode: input or output */
603 if (conf->output) {
604 u300_gpio_direction_output(&gpio->chip, offset, conf->outval);
Linus Walleijbd41b992009-04-23 21:15:04 +0100605
Linus Walleijcc890cd2011-09-08 09:04:51 +0100606 /* Deactivate bias mode for output */
Linus Walleijdc0b1aa2011-11-16 21:58:10 +0100607 u300_gpio_config_set(&gpio->chip, offset,
608 PIN_CONFIG_BIAS_HIGH_IMPEDANCE);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100609
610 /* Set drive mode for output */
Linus Walleijdc0b1aa2011-11-16 21:58:10 +0100611 u300_gpio_config_set(&gpio->chip, offset,
612 PIN_CONFIG_DRIVE_PUSH_PULL);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100613
614 dev_dbg(gpio->dev, "set up pin %d as output, value: %d\n",
615 offset, conf->outval);
616 } else {
617 u300_gpio_direction_input(&gpio->chip, offset);
618
619 /* Always set output low on input pins */
620 u300_gpio_set(&gpio->chip, offset, 0);
621
622 /* Set bias mode for input */
Linus Walleijdc0b1aa2011-11-16 21:58:10 +0100623 u300_gpio_config_set(&gpio->chip, offset, conf->bias_mode);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100624
625 dev_dbg(gpio->dev, "set up pin %d as input, bias: %04x\n",
626 offset, conf->bias_mode);
627 }
628}
629
Linus Walleijb263e9b2013-05-23 20:09:43 +0200630static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio)
Linus Walleijcc890cd2011-09-08 09:04:51 +0100631{
632 int i, j;
633
634 /* Write default config and values to all pins */
Linus Walleijb263e9b2013-05-23 20:09:43 +0200635 for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100636 for (j = 0; j < 8; j++) {
637 const struct u300_gpio_confdata *conf;
638 int offset = (i*8) + j;
639
Linus Walleij04b13de2012-08-13 10:36:55 +0200640 conf = &bs335_gpio_config[i][j];
Linus Walleijcc890cd2011-09-08 09:04:51 +0100641 u300_gpio_init_pin(gpio, offset, conf);
642 }
643 }
644}
645
646static inline void u300_gpio_free_ports(struct u300_gpio *gpio)
647{
648 struct u300_gpio_port *port;
649 struct list_head *p, *n;
650
651 list_for_each_safe(p, n, &gpio->port_list) {
652 port = list_entry(p, struct u300_gpio_port, node);
653 list_del(&port->node);
Linus Walleija6c45b92012-10-17 18:31:20 +0200654 if (port->domain)
655 irq_domain_remove(port->domain);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100656 kfree(port);
657 }
658}
659
Linus Walleij387923c2012-11-20 14:28:07 +0100660/*
661 * Here we map a GPIO in the local gpio_chip pin space to a pin in
662 * the local pinctrl pin space. The pin controller used is
663 * pinctrl-u300.
664 */
665struct coh901_pinpair {
666 unsigned int offset;
667 unsigned int pin_base;
668};
669
670#define COH901_PINRANGE(a, b) { .offset = a, .pin_base = b }
671
672static struct coh901_pinpair coh901_pintable[] = {
673 COH901_PINRANGE(10, 426),
674 COH901_PINRANGE(11, 180),
675 COH901_PINRANGE(12, 165), /* MS/MMC card insertion */
676 COH901_PINRANGE(13, 179),
677 COH901_PINRANGE(14, 178),
678 COH901_PINRANGE(16, 194),
679 COH901_PINRANGE(17, 193),
680 COH901_PINRANGE(18, 192),
681 COH901_PINRANGE(19, 191),
682 COH901_PINRANGE(20, 186),
683 COH901_PINRANGE(21, 185),
684 COH901_PINRANGE(22, 184),
685 COH901_PINRANGE(23, 183),
686 COH901_PINRANGE(24, 182),
687 COH901_PINRANGE(25, 181),
688};
689
Linus Walleijcc890cd2011-09-08 09:04:51 +0100690static int __init u300_gpio_probe(struct platform_device *pdev)
691{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100692 struct u300_gpio *gpio;
Linus Walleij585583f2012-10-17 18:49:05 +0200693 struct resource *memres;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100694 int err = 0;
695 int portno;
696 u32 val;
697 u32 ifr;
698 int i;
699
Linus Walleij585583f2012-10-17 18:49:05 +0200700 gpio = devm_kzalloc(&pdev->dev, sizeof(struct u300_gpio), GFP_KERNEL);
701 if (gpio == NULL)
Linus Walleijcc890cd2011-09-08 09:04:51 +0100702 return -ENOMEM;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100703
704 gpio->chip = u300_gpio_chip;
Linus Walleijb263e9b2013-05-23 20:09:43 +0200705 gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100706 gpio->chip.dev = &pdev->dev;
Linus Walleijb263e9b2013-05-23 20:09:43 +0200707 gpio->chip.base = 0;
Linus Walleijcc890cd2011-09-08 09:04:51 +0100708 gpio->dev = &pdev->dev;
Linus Walleijbd41b992009-04-23 21:15:04 +0100709
Linus Walleij585583f2012-10-17 18:49:05 +0200710 memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Thierry Reding9e0c1fb2013-01-21 11:09:14 +0100711 gpio->base = devm_ioremap_resource(&pdev->dev, memres);
712 if (IS_ERR(gpio->base))
713 return PTR_ERR(gpio->base);
Linus Walleij585583f2012-10-17 18:49:05 +0200714
715 gpio->clk = devm_clk_get(gpio->dev, NULL);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100716 if (IS_ERR(gpio->clk)) {
717 err = PTR_ERR(gpio->clk);
718 dev_err(gpio->dev, "could not get GPIO clock\n");
Linus Walleij585583f2012-10-17 18:49:05 +0200719 return err;
Linus Walleijbd41b992009-04-23 21:15:04 +0100720 }
Linus Walleij585583f2012-10-17 18:49:05 +0200721
Linus Walleij27e84612012-06-19 23:36:15 +0200722 err = clk_prepare_enable(gpio->clk);
Linus Walleijbd41b992009-04-23 21:15:04 +0100723 if (err) {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100724 dev_err(gpio->dev, "could not enable GPIO clock\n");
Linus Walleij585583f2012-10-17 18:49:05 +0200725 return err;
Linus Walleijbd41b992009-04-23 21:15:04 +0100726 }
727
Linus Walleij04b13de2012-08-13 10:36:55 +0200728 dev_info(gpio->dev,
729 "initializing GPIO Controller COH 901 571/3\n");
730 gpio->stride = U300_GPIO_PORT_STRIDE;
731 gpio->pcr = U300_GPIO_PXPCR;
732 gpio->dor = U300_GPIO_PXPDOR;
733 gpio->dir = U300_GPIO_PXPDIR;
734 gpio->per = U300_GPIO_PXPER;
735 gpio->icr = U300_GPIO_PXICR;
736 gpio->ien = U300_GPIO_PXIEN;
737 gpio->iev = U300_GPIO_PXIEV;
738 ifr = U300_GPIO_PXIFR;
Linus Walleijbd41b992009-04-23 21:15:04 +0100739
Linus Walleij04b13de2012-08-13 10:36:55 +0200740 val = readl(gpio->base + U300_GPIO_CR);
741 dev_info(gpio->dev, "COH901571/3 block version: %d, " \
742 "number of cores: %d totalling %d pins\n",
743 ((val & 0x000001FC) >> 2),
744 ((val & 0x0000FE00) >> 9),
745 ((val & 0x0000FE00) >> 9) * 8);
746 writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
747 gpio->base + U300_GPIO_CR);
Linus Walleijb263e9b2013-05-23 20:09:43 +0200748 u300_gpio_init_coh901571(gpio);
Linus Walleijbd41b992009-04-23 21:15:04 +0100749
Linus Walleijcc890cd2011-09-08 09:04:51 +0100750 /* Add each port with its IRQ separately */
751 INIT_LIST_HEAD(&gpio->port_list);
Linus Walleijb263e9b2013-05-23 20:09:43 +0200752 for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
Linus Walleijcc890cd2011-09-08 09:04:51 +0100753 struct u300_gpio_port *port =
754 kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
755
756 if (!port) {
757 dev_err(gpio->dev, "out of memory\n");
758 err = -ENOMEM;
759 goto err_no_port;
760 }
761
762 snprintf(port->name, 8, "gpio%d", portno);
763 port->number = portno;
764 port->gpio = gpio;
765
Linus Walleij351c2162013-04-10 10:49:31 +0200766 port->irq = platform_get_irq(pdev, portno);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100767
Linus Walleija6c45b92012-10-17 18:31:20 +0200768 dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq,
Linus Walleijcc890cd2011-09-08 09:04:51 +0100769 port->name);
770
Linus Walleija6c45b92012-10-17 18:31:20 +0200771 port->domain = irq_domain_add_linear(pdev->dev.of_node,
772 U300_GPIO_PINS_PER_PORT,
773 &irq_domain_simple_ops,
774 port);
Axel Lin80357202012-11-14 00:16:14 +0800775 if (!port->domain) {
776 err = -ENOMEM;
Linus Walleija6c45b92012-10-17 18:31:20 +0200777 goto err_no_domain;
Axel Lin80357202012-11-14 00:16:14 +0800778 }
Linus Walleija6c45b92012-10-17 18:31:20 +0200779
Linus Walleijcc890cd2011-09-08 09:04:51 +0100780 irq_set_chained_handler(port->irq, u300_gpio_irq_handler);
781 irq_set_handler_data(port->irq, port);
782
783 /* For each GPIO pin set the unique IRQ handler */
784 for (i = 0; i < U300_GPIO_PINS_PER_PORT; i++) {
Linus Walleija6c45b92012-10-17 18:31:20 +0200785 int irqno = irq_create_mapping(port->domain, i);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100786
Linus Walleija6c45b92012-10-17 18:31:20 +0200787 dev_dbg(gpio->dev, "GPIO%d on port %s gets IRQ %d\n",
788 gpio->chip.base + (port->number << 3) + i,
789 port->name, irqno);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100790 irq_set_chip_and_handler(irqno, &u300_gpio_irqchip,
791 handle_simple_irq);
792 set_irq_flags(irqno, IRQF_VALID);
793 irq_set_chip_data(irqno, port);
794 }
795
796 /* Turns off irq force (test register) for this port */
797 writel(0x0, gpio->base + portno * gpio->stride + ifr);
798
799 list_add_tail(&port->node, &gpio->port_list);
800 }
801 dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
802
Linus Walleij351c2162013-04-10 10:49:31 +0200803#ifdef CONFIG_OF_GPIO
804 gpio->chip.of_node = pdev->dev.of_node;
805#endif
Linus Walleijcc890cd2011-09-08 09:04:51 +0100806 err = gpiochip_add(&gpio->chip);
807 if (err) {
808 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
809 goto err_no_chip;
810 }
811
Linus Walleij387923c2012-11-20 14:28:07 +0100812 /*
813 * Add pinctrl pin ranges, the pin controller must be registered
814 * at this point
815 */
816 for (i = 0; i < ARRAY_SIZE(coh901_pintable); i++) {
817 struct coh901_pinpair *p = &coh901_pintable[i];
818
819 err = gpiochip_add_pin_range(&gpio->chip, "pinctrl-u300",
820 p->offset, p->pin_base, 1);
821 if (err)
822 goto err_no_range;
823 }
824
Linus Walleijcc890cd2011-09-08 09:04:51 +0100825 platform_set_drvdata(pdev, gpio);
826
Linus Walleijbd41b992009-04-23 21:15:04 +0100827 return 0;
828
Linus Walleij387923c2012-11-20 14:28:07 +0100829err_no_range:
Axel Lin97fc4632013-05-19 13:58:37 +0800830 if (gpiochip_remove(&gpio->chip))
831 dev_err(&pdev->dev, "failed to remove gpio chip\n");
Linus Walleijcc890cd2011-09-08 09:04:51 +0100832err_no_chip:
Linus Walleija6c45b92012-10-17 18:31:20 +0200833err_no_domain:
Linus Walleijcc890cd2011-09-08 09:04:51 +0100834err_no_port:
835 u300_gpio_free_ports(gpio);
Linus Walleij27e84612012-06-19 23:36:15 +0200836 clk_disable_unprepare(gpio->clk);
Axel Lin80357202012-11-14 00:16:14 +0800837 dev_err(&pdev->dev, "module ERROR:%d\n", err);
Linus Walleijbd41b992009-04-23 21:15:04 +0100838 return err;
839}
840
Linus Walleijcc890cd2011-09-08 09:04:51 +0100841static int __exit u300_gpio_remove(struct platform_device *pdev)
Linus Walleijbd41b992009-04-23 21:15:04 +0100842{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100843 struct u300_gpio *gpio = platform_get_drvdata(pdev);
844 int err;
Linus Walleijbd41b992009-04-23 21:15:04 +0100845
846 /* Turn off the GPIO block */
Linus Walleij04b13de2012-08-13 10:36:55 +0200847 writel(0x00000000U, gpio->base + U300_GPIO_CR);
Linus Walleijcc890cd2011-09-08 09:04:51 +0100848
849 err = gpiochip_remove(&gpio->chip);
850 if (err < 0) {
851 dev_err(gpio->dev, "unable to remove gpiochip: %d\n", err);
852 return err;
853 }
854 u300_gpio_free_ports(gpio);
Linus Walleij27e84612012-06-19 23:36:15 +0200855 clk_disable_unprepare(gpio->clk);
Linus Walleijbd41b992009-04-23 21:15:04 +0100856 return 0;
857}
858
Linus Walleij351c2162013-04-10 10:49:31 +0200859static const struct of_device_id u300_gpio_match[] = {
860 { .compatible = "stericsson,gpio-coh901" },
861 {},
862};
863
Linus Walleijcc890cd2011-09-08 09:04:51 +0100864static struct platform_driver u300_gpio_driver = {
Linus Walleijbd41b992009-04-23 21:15:04 +0100865 .driver = {
866 .name = "u300-gpio",
Linus Walleij351c2162013-04-10 10:49:31 +0200867 .of_match_table = u300_gpio_match,
Linus Walleijbd41b992009-04-23 21:15:04 +0100868 },
Linus Walleijcc890cd2011-09-08 09:04:51 +0100869 .remove = __exit_p(u300_gpio_remove),
Linus Walleijbd41b992009-04-23 21:15:04 +0100870};
871
Linus Walleijbd41b992009-04-23 21:15:04 +0100872static int __init u300_gpio_init(void)
873{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100874 return platform_driver_probe(&u300_gpio_driver, u300_gpio_probe);
Linus Walleijbd41b992009-04-23 21:15:04 +0100875}
876
877static void __exit u300_gpio_exit(void)
878{
Linus Walleijcc890cd2011-09-08 09:04:51 +0100879 platform_driver_unregister(&u300_gpio_driver);
Linus Walleijbd41b992009-04-23 21:15:04 +0100880}
881
882arch_initcall(u300_gpio_init);
883module_exit(u300_gpio_exit);
884
885MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
Linus Walleijcc890cd2011-09-08 09:04:51 +0100886MODULE_DESCRIPTION("ST-Ericsson AB COH 901 335/COH 901 571/3 GPIO driver");
Linus Walleijbd41b992009-04-23 21:15:04 +0100887MODULE_LICENSE("GPL");