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Catalin Marinasf668cd12012-03-05 11:49:30 +00001/*
2 * Copyright (C) 2012 ARM Ltd.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16#ifndef __ASM_ELF_H
17#define __ASM_ELF_H
18
19#include <asm/hwcap.h>
20
21/*
22 * ELF register definitions..
23 */
24#include <asm/ptrace.h>
25#include <asm/user.h>
26
Catalin Marinasf668cd12012-03-05 11:49:30 +000027/*
28 * AArch64 static relocation types.
29 */
30
31/* Miscellaneous. */
32#define R_ARM_NONE 0
33#define R_AARCH64_NONE 256
34
35/* Data. */
36#define R_AARCH64_ABS64 257
37#define R_AARCH64_ABS32 258
38#define R_AARCH64_ABS16 259
39#define R_AARCH64_PREL64 260
40#define R_AARCH64_PREL32 261
41#define R_AARCH64_PREL16 262
42
43/* Instructions. */
44#define R_AARCH64_MOVW_UABS_G0 263
45#define R_AARCH64_MOVW_UABS_G0_NC 264
46#define R_AARCH64_MOVW_UABS_G1 265
47#define R_AARCH64_MOVW_UABS_G1_NC 266
48#define R_AARCH64_MOVW_UABS_G2 267
49#define R_AARCH64_MOVW_UABS_G2_NC 268
50#define R_AARCH64_MOVW_UABS_G3 269
51
52#define R_AARCH64_MOVW_SABS_G0 270
53#define R_AARCH64_MOVW_SABS_G1 271
54#define R_AARCH64_MOVW_SABS_G2 272
55
56#define R_AARCH64_LD_PREL_LO19 273
57#define R_AARCH64_ADR_PREL_LO21 274
58#define R_AARCH64_ADR_PREL_PG_HI21 275
59#define R_AARCH64_ADR_PREL_PG_HI21_NC 276
60#define R_AARCH64_ADD_ABS_LO12_NC 277
61#define R_AARCH64_LDST8_ABS_LO12_NC 278
62
63#define R_AARCH64_TSTBR14 279
64#define R_AARCH64_CONDBR19 280
65#define R_AARCH64_JUMP26 282
66#define R_AARCH64_CALL26 283
67#define R_AARCH64_LDST16_ABS_LO12_NC 284
68#define R_AARCH64_LDST32_ABS_LO12_NC 285
69#define R_AARCH64_LDST64_ABS_LO12_NC 286
70#define R_AARCH64_LDST128_ABS_LO12_NC 299
71
72#define R_AARCH64_MOVW_PREL_G0 287
73#define R_AARCH64_MOVW_PREL_G0_NC 288
74#define R_AARCH64_MOVW_PREL_G1 289
75#define R_AARCH64_MOVW_PREL_G1_NC 290
76#define R_AARCH64_MOVW_PREL_G2 291
77#define R_AARCH64_MOVW_PREL_G2_NC 292
78#define R_AARCH64_MOVW_PREL_G3 293
79
Ard Biesheuvel1e48ef72016-01-26 09:13:44 +010080#define R_AARCH64_RELATIVE 1027
81
Catalin Marinasf668cd12012-03-05 11:49:30 +000082/*
83 * These are used to set parameters in the core dumps.
84 */
85#define ELF_CLASS ELFCLASS64
Will Deacon5436b5c2013-10-11 14:52:10 +010086#ifdef __AARCH64EB__
87#define ELF_DATA ELFDATA2MSB
88#else
Catalin Marinasf668cd12012-03-05 11:49:30 +000089#define ELF_DATA ELFDATA2LSB
Will Deacon5436b5c2013-10-11 14:52:10 +010090#endif
Catalin Marinasf668cd12012-03-05 11:49:30 +000091#define ELF_ARCH EM_AARCH64
92
Will Deacon5436b5c2013-10-11 14:52:10 +010093/*
94 * This yields a string that ld.so will use to load implementation
95 * specific libraries for optimization. This is more specific in
96 * intent than poking at uname or /proc/cpuinfo.
97 */
Catalin Marinasf668cd12012-03-05 11:49:30 +000098#define ELF_PLATFORM_SIZE 16
Will Deacon5436b5c2013-10-11 14:52:10 +010099#ifdef __AARCH64EB__
100#define ELF_PLATFORM ("aarch64_be")
101#else
Catalin Marinasf668cd12012-03-05 11:49:30 +0000102#define ELF_PLATFORM ("aarch64")
Will Deacon5436b5c2013-10-11 14:52:10 +0100103#endif
Catalin Marinasf668cd12012-03-05 11:49:30 +0000104
105/*
106 * This is used to ensure we don't load something for the wrong architecture.
107 */
108#define elf_check_arch(x) ((x)->e_machine == EM_AARCH64)
109
110#define elf_read_implies_exec(ex,stk) (stk != EXSTACK_DISABLE_X)
111
112#define CORE_DUMP_USE_REGSET
113#define ELF_EXEC_PAGESIZE PAGE_SIZE
114
115/*
Kees Cook70779e02017-07-10 15:52:44 -0700116 * This is the base location for PIE (ET_DYN with INTERP) loads. On
Kees Cook1f2347a2017-08-18 15:16:31 -0700117 * 64-bit, this is above 4GB to leave the entire 32-bit address
Kees Cook70779e02017-07-10 15:52:44 -0700118 * space open for things that want to use the area for 32-bit pointers.
Catalin Marinasf668cd12012-03-05 11:49:30 +0000119 */
Kees Cook1f2347a2017-08-18 15:16:31 -0700120#define ELF_ET_DYN_BASE (2 * TASK_SIZE_64 / 3)
Catalin Marinasf668cd12012-03-05 11:49:30 +0000121
Ard Biesheuvel4a2e0342016-01-11 17:08:26 +0100122#ifndef __ASSEMBLY__
123
124typedef unsigned long elf_greg_t;
125
126#define ELF_NGREG (sizeof(struct user_pt_regs) / sizeof(elf_greg_t))
127#define ELF_CORE_COPY_REGS(dest, regs) \
128 *(struct user_pt_regs *)&(dest) = (regs)->user_regs;
129
130typedef elf_greg_t elf_gregset_t[ELF_NGREG];
131typedef struct user_fpsimd_state elf_fpregset_t;
132
Catalin Marinasf668cd12012-03-05 11:49:30 +0000133/*
134 * When the program starts, a1 contains a pointer to a function to be
135 * registered with atexit, as per the SVR4 ABI. A value of 0 means we have no
136 * such handler.
137 */
138#define ELF_PLAT_INIT(_r, load_addr) (_r)->regs[0] = 0
139
140#define SET_PERSONALITY(ex) clear_thread_flag(TIF_32BIT);
141
James Hogan3146bc62016-07-25 16:59:52 +0100142/* update AT_VECTOR_SIZE_ARCH if the number of NEW_AUX_ENT entries changes */
Catalin Marinasf668cd12012-03-05 11:49:30 +0000143#define ARCH_DLINFO \
144do { \
145 NEW_AUX_ENT(AT_SYSINFO_EHDR, \
146 (elf_addr_t)current->mm->context.vdso); \
147} while (0)
148
149#define ARCH_HAS_SETUP_ADDITIONAL_PAGES
150struct linux_binprm;
151extern int arch_setup_additional_pages(struct linux_binprm *bprm,
152 int uses_interp);
153
154/* 1GB of VA */
155#ifdef CONFIG_COMPAT
156#define STACK_RND_MASK (test_thread_flag(TIF_32BIT) ? \
157 0x7ff >> (PAGE_SHIFT - 12) : \
158 0x3ffff >> (PAGE_SHIFT - 12))
159#else
160#define STACK_RND_MASK (0x3ffff >> (PAGE_SHIFT - 12))
161#endif
162
Will Deacona795a382013-10-11 14:52:12 +0100163#ifdef __AARCH64EB__
164#define COMPAT_ELF_PLATFORM ("v8b")
165#else
Catalin Marinasf668cd12012-03-05 11:49:30 +0000166#define COMPAT_ELF_PLATFORM ("v8l")
Will Deacona795a382013-10-11 14:52:12 +0100167#endif
Catalin Marinasf668cd12012-03-05 11:49:30 +0000168
Catalin Marinase47b0202016-05-31 15:55:03 +0100169#ifdef CONFIG_COMPAT
170
Kees Cook70779e02017-07-10 15:52:44 -0700171/* PIE load location for compat arm. Must match ARM ELF_ET_DYN_BASE. */
Evgenii Stepanovb4ace312017-11-01 15:10:12 -0700172#define COMPAT_ELF_ET_DYN_BASE (2 * TASK_SIZE_32 / 3)
Catalin Marinasf668cd12012-03-05 11:49:30 +0000173
174/* AArch32 registers. */
175#define COMPAT_ELF_NGREG 18
176typedef unsigned int compat_elf_greg_t;
177typedef compat_elf_greg_t compat_elf_gregset_t[COMPAT_ELF_NGREG];
178
179/* AArch32 EABI. */
180#define EF_ARM_EABI_MASK 0xff000000
Suzuki K Poulose643d7032016-04-18 10:28:37 +0100181#define compat_elf_check_arch(x) (system_supports_32bit_el0() && \
182 ((x)->e_machine == EM_ARM) && \
Catalin Marinasf668cd12012-03-05 11:49:30 +0000183 ((x)->e_flags & EF_ARM_EABI_MASK))
184
185#define compat_start_thread compat_start_thread
186#define COMPAT_SET_PERSONALITY(ex) set_thread_flag(TIF_32BIT);
187#define COMPAT_ARCH_DLINFO
188extern int aarch32_setup_vectors_page(struct linux_binprm *bprm,
189 int uses_interp);
190#define compat_arch_setup_additional_pages \
191 aarch32_setup_vectors_page
192
193#endif /* CONFIG_COMPAT */
194
Ard Biesheuvel4a2e0342016-01-11 17:08:26 +0100195#endif /* !__ASSEMBLY__ */
196
Catalin Marinasf668cd12012-03-05 11:49:30 +0000197#endif