blob: 5d2d3560f18694188cf057b376226d408cd3c56d [file] [log] [blame]
Catalin Marinas0be73202012-03-05 11:49:26 +00001/*
2 * Based on arch/arm/kernel/asm-offsets.c
3 *
4 * Copyright (C) 1995-2003 Russell King
5 * 2001-2002 Keith Owens
6 * Copyright (C) 2012 ARM Ltd.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program. If not, see <http://www.gnu.org/licenses/>.
19 */
20
21#include <linux/sched.h>
22#include <linux/mm.h>
23#include <linux/dma-mapping.h>
Marc Zyngierc3eb5b12013-07-04 13:34:32 +010024#include <linux/kvm_host.h>
James Morse82869ac2016-04-27 17:47:12 +010025#include <linux/suspend.h>
Suzuki K Poulose116c81f2016-09-09 14:07:16 +010026#include <asm/cpufeature.h>
Will Deacon5e54c4b2017-11-14 14:14:17 +000027#include <asm/fixmap.h>
Catalin Marinas0be73202012-03-05 11:49:26 +000028#include <asm/thread_info.h>
29#include <asm/memory.h>
Lorenzo Pieralisi95322522013-07-22 12:22:13 +010030#include <asm/smp_plat.h>
31#include <asm/suspend.h>
Catalin Marinas0be73202012-03-05 11:49:26 +000032#include <asm/vdso_datapage.h>
33#include <linux/kbuild.h>
Jens Wiklander14457452016-01-04 15:44:32 +010034#include <linux/arm-smccc.h>
Catalin Marinas0be73202012-03-05 11:49:26 +000035
36int main(void)
37{
38 DEFINE(TSK_ACTIVE_MM, offsetof(struct task_struct, active_mm));
39 BLANK();
Mark Rutland5b7e8f72016-11-03 20:23:13 +000040 DEFINE(TSK_TI_FLAGS, offsetof(struct task_struct, thread_info.flags));
41 DEFINE(TSK_TI_PREEMPT, offsetof(struct task_struct, thread_info.preempt_count));
42 DEFINE(TSK_TI_ADDR_LIMIT, offsetof(struct task_struct, thread_info.addr_limit));
Catalin Marinas005bf1a2016-07-01 16:53:00 +010043#ifdef CONFIG_ARM64_SW_TTBR0_PAN
Greg Hackmann70b330c2018-04-18 15:33:53 -070044 DEFINE(TSK_TI_TTBR0, offsetof(struct task_struct, thread_info.ttbr0));
Catalin Marinas005bf1a2016-07-01 16:53:00 +010045#endif
Mark Rutland5b7e8f72016-11-03 20:23:13 +000046 DEFINE(TSK_STACK, offsetof(struct task_struct, stack));
Catalin Marinas0be73202012-03-05 11:49:26 +000047 BLANK();
48 DEFINE(THREAD_CPU_CONTEXT, offsetof(struct task_struct, thread.cpu_context));
49 BLANK();
50 DEFINE(S_X0, offsetof(struct pt_regs, regs[0]));
51 DEFINE(S_X1, offsetof(struct pt_regs, regs[1]));
52 DEFINE(S_X2, offsetof(struct pt_regs, regs[2]));
53 DEFINE(S_X3, offsetof(struct pt_regs, regs[3]));
54 DEFINE(S_X4, offsetof(struct pt_regs, regs[4]));
55 DEFINE(S_X5, offsetof(struct pt_regs, regs[5]));
56 DEFINE(S_X6, offsetof(struct pt_regs, regs[6]));
57 DEFINE(S_X7, offsetof(struct pt_regs, regs[7]));
William Cohenda6a9122016-07-08 12:35:52 -040058 DEFINE(S_X8, offsetof(struct pt_regs, regs[8]));
59 DEFINE(S_X10, offsetof(struct pt_regs, regs[10]));
60 DEFINE(S_X12, offsetof(struct pt_regs, regs[12]));
61 DEFINE(S_X14, offsetof(struct pt_regs, regs[14]));
62 DEFINE(S_X16, offsetof(struct pt_regs, regs[16]));
63 DEFINE(S_X18, offsetof(struct pt_regs, regs[18]));
64 DEFINE(S_X20, offsetof(struct pt_regs, regs[20]));
65 DEFINE(S_X22, offsetof(struct pt_regs, regs[22]));
66 DEFINE(S_X24, offsetof(struct pt_regs, regs[24]));
67 DEFINE(S_X26, offsetof(struct pt_regs, regs[26]));
68 DEFINE(S_X28, offsetof(struct pt_regs, regs[28]));
Catalin Marinas0be73202012-03-05 11:49:26 +000069 DEFINE(S_LR, offsetof(struct pt_regs, regs[30]));
70 DEFINE(S_SP, offsetof(struct pt_regs, sp));
71#ifdef CONFIG_COMPAT
72 DEFINE(S_COMPAT_SP, offsetof(struct pt_regs, compat_sp));
73#endif
74 DEFINE(S_PSTATE, offsetof(struct pt_regs, pstate));
75 DEFINE(S_PC, offsetof(struct pt_regs, pc));
76 DEFINE(S_ORIG_X0, offsetof(struct pt_regs, orig_x0));
77 DEFINE(S_SYSCALLNO, offsetof(struct pt_regs, syscallno));
James Morsee19a6ee2016-06-20 18:28:01 +010078 DEFINE(S_ORIG_ADDR_LIMIT, offsetof(struct pt_regs, orig_addr_limit));
Catalin Marinas0be73202012-03-05 11:49:26 +000079 DEFINE(S_FRAME_SIZE, sizeof(struct pt_regs));
80 BLANK();
Will Deacon5aec7152015-10-06 18:46:24 +010081 DEFINE(MM_CONTEXT_ID, offsetof(struct mm_struct, context.id.counter));
Catalin Marinas0be73202012-03-05 11:49:26 +000082 BLANK();
83 DEFINE(VMA_VM_MM, offsetof(struct vm_area_struct, vm_mm));
84 DEFINE(VMA_VM_FLAGS, offsetof(struct vm_area_struct, vm_flags));
85 BLANK();
86 DEFINE(VM_EXEC, VM_EXEC);
87 BLANK();
88 DEFINE(PAGE_SZ, PAGE_SIZE);
89 BLANK();
Catalin Marinas0be73202012-03-05 11:49:26 +000090 DEFINE(DMA_BIDIRECTIONAL, DMA_BIDIRECTIONAL);
91 DEFINE(DMA_TO_DEVICE, DMA_TO_DEVICE);
92 DEFINE(DMA_FROM_DEVICE, DMA_FROM_DEVICE);
93 BLANK();
94 DEFINE(CLOCK_REALTIME, CLOCK_REALTIME);
95 DEFINE(CLOCK_MONOTONIC, CLOCK_MONOTONIC);
Kevin Brodsky49eea432016-07-12 11:24:00 +010096 DEFINE(CLOCK_MONOTONIC_RAW, CLOCK_MONOTONIC_RAW);
Catalin Marinas0be73202012-03-05 11:49:26 +000097 DEFINE(CLOCK_REALTIME_RES, MONOTONIC_RES_NSEC);
98 DEFINE(CLOCK_REALTIME_COARSE, CLOCK_REALTIME_COARSE);
99 DEFINE(CLOCK_MONOTONIC_COARSE,CLOCK_MONOTONIC_COARSE);
100 DEFINE(CLOCK_COARSE_RES, LOW_RES_NSEC);
101 DEFINE(NSEC_PER_SEC, NSEC_PER_SEC);
102 BLANK();
103 DEFINE(VDSO_CS_CYCLE_LAST, offsetof(struct vdso_data, cs_cycle_last));
Kevin Brodsky49eea432016-07-12 11:24:00 +0100104 DEFINE(VDSO_RAW_TIME_SEC, offsetof(struct vdso_data, raw_time_sec));
105 DEFINE(VDSO_RAW_TIME_NSEC, offsetof(struct vdso_data, raw_time_nsec));
Catalin Marinas0be73202012-03-05 11:49:26 +0000106 DEFINE(VDSO_XTIME_CLK_SEC, offsetof(struct vdso_data, xtime_clock_sec));
107 DEFINE(VDSO_XTIME_CLK_NSEC, offsetof(struct vdso_data, xtime_clock_nsec));
108 DEFINE(VDSO_XTIME_CRS_SEC, offsetof(struct vdso_data, xtime_coarse_sec));
109 DEFINE(VDSO_XTIME_CRS_NSEC, offsetof(struct vdso_data, xtime_coarse_nsec));
110 DEFINE(VDSO_WTM_CLK_SEC, offsetof(struct vdso_data, wtm_clock_sec));
111 DEFINE(VDSO_WTM_CLK_NSEC, offsetof(struct vdso_data, wtm_clock_nsec));
112 DEFINE(VDSO_TB_SEQ_COUNT, offsetof(struct vdso_data, tb_seq_count));
Kevin Brodsky49eea432016-07-12 11:24:00 +0100113 DEFINE(VDSO_CS_MONO_MULT, offsetof(struct vdso_data, cs_mono_mult));
114 DEFINE(VDSO_CS_RAW_MULT, offsetof(struct vdso_data, cs_raw_mult));
Catalin Marinas0be73202012-03-05 11:49:26 +0000115 DEFINE(VDSO_CS_SHIFT, offsetof(struct vdso_data, cs_shift));
116 DEFINE(VDSO_TZ_MINWEST, offsetof(struct vdso_data, tz_minuteswest));
117 DEFINE(VDSO_TZ_DSTTIME, offsetof(struct vdso_data, tz_dsttime));
118 DEFINE(VDSO_USE_SYSCALL, offsetof(struct vdso_data, use_syscall));
119 BLANK();
120 DEFINE(TVAL_TV_SEC, offsetof(struct timeval, tv_sec));
121 DEFINE(TVAL_TV_USEC, offsetof(struct timeval, tv_usec));
122 DEFINE(TSPEC_TV_SEC, offsetof(struct timespec, tv_sec));
123 DEFINE(TSPEC_TV_NSEC, offsetof(struct timespec, tv_nsec));
124 BLANK();
125 DEFINE(TZ_MINWEST, offsetof(struct timezone, tz_minuteswest));
126 DEFINE(TZ_DSTTIME, offsetof(struct timezone, tz_dsttime));
Marc Zyngier55c74012012-12-10 16:40:18 +0000127 BLANK();
Suzuki K Poulosebb905272016-02-23 10:31:42 +0000128 DEFINE(CPU_BOOT_STACK, offsetof(struct secondary_data, stack));
Mark Rutland5b7e8f72016-11-03 20:23:13 +0000129 DEFINE(CPU_BOOT_TASK, offsetof(struct secondary_data, task));
Suzuki K Poulosebb905272016-02-23 10:31:42 +0000130 BLANK();
Marc Zyngier55c74012012-12-10 16:40:18 +0000131#ifdef CONFIG_KVM_ARM_HOST
132 DEFINE(VCPU_CONTEXT, offsetof(struct kvm_vcpu, arch.ctxt));
133 DEFINE(CPU_GP_REGS, offsetof(struct kvm_cpu_context, gp_regs));
134 DEFINE(CPU_USER_PT_REGS, offsetof(struct kvm_regs, regs));
135 DEFINE(CPU_FP_REGS, offsetof(struct kvm_regs, fp_regs));
Marc Zyngier9d8415d2015-10-25 19:57:11 +0000136 DEFINE(VCPU_FPEXC32_EL2, offsetof(struct kvm_vcpu, arch.ctxt.sys_regs[FPEXC32_EL2]));
Marc Zyngier55c74012012-12-10 16:40:18 +0000137 DEFINE(VCPU_HOST_CONTEXT, offsetof(struct kvm_vcpu, arch.host_cpu_context));
Marc Zyngier55c74012012-12-10 16:40:18 +0000138#endif
Lorenzo Pieralisiaf3cfdb2015-01-26 18:33:44 +0000139#ifdef CONFIG_CPU_PM
Lorenzo Pieralisi95322522013-07-22 12:22:13 +0100140 DEFINE(CPU_SUSPEND_SZ, sizeof(struct cpu_suspend_ctx));
141 DEFINE(CPU_CTX_SP, offsetof(struct cpu_suspend_ctx, sp));
142 DEFINE(MPIDR_HASH_MASK, offsetof(struct mpidr_hash, mask));
143 DEFINE(MPIDR_HASH_SHIFTS, offsetof(struct mpidr_hash, shift_aff));
James Morseadc9b2d2016-04-27 17:47:06 +0100144 DEFINE(SLEEP_STACK_DATA_SYSTEM_REGS, offsetof(struct sleep_stack_data, system_regs));
145 DEFINE(SLEEP_STACK_DATA_CALLEE_REGS, offsetof(struct sleep_stack_data, callee_saved_regs));
Lorenzo Pieralisi95322522013-07-22 12:22:13 +0100146#endif
Andy Gross007f0a22017-04-04 19:32:31 +0000147 DEFINE(ARM_SMCCC_RES_X0_OFFS, offsetof(struct arm_smccc_res, a0));
148 DEFINE(ARM_SMCCC_RES_X2_OFFS, offsetof(struct arm_smccc_res, a2));
149 DEFINE(ARM_SMCCC_QUIRK_ID_OFFS, offsetof(struct arm_smccc_quirk, id));
150 DEFINE(ARM_SMCCC_QUIRK_STATE_OFFS, offsetof(struct arm_smccc_quirk, state));
James Morse82869ac2016-04-27 17:47:12 +0100151 BLANK();
152 DEFINE(HIBERN_PBE_ORIG, offsetof(struct pbe, orig_address));
153 DEFINE(HIBERN_PBE_ADDR, offsetof(struct pbe, address));
154 DEFINE(HIBERN_PBE_NEXT, offsetof(struct pbe, next));
Suzuki K Poulose116c81f2016-09-09 14:07:16 +0100155 DEFINE(ARM64_FTR_SYSVAL, offsetof(struct arm64_ftr_reg, sys_val));
Will Deacon5e54c4b2017-11-14 14:14:17 +0000156 BLANK();
157#ifdef CONFIG_UNMAP_KERNEL_AT_EL0
158 DEFINE(TRAMP_VALIAS, TRAMP_VALIAS);
159#endif
Catalin Marinas0be73202012-03-05 11:49:26 +0000160 return 0;
161}