| Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 1 | /* |
| Philippe De Muyter | 03cbc385 | 2010-08-19 19:04:58 +0200 | [diff] [blame^] | 2 | * intc-2.c |
| 3 | * |
| 4 | * General interrupt controller code for the many ColdFire version 2 cores |
| 5 | * that use the two region INTC interrupt controller. This includes the |
| 6 | * 523x family, 5270, 5271, 5274, 5275, and the 528x families. |
| Greg Ungerer | 2fba4f0 | 2009-04-27 15:38:03 +1000 | [diff] [blame] | 7 | * |
| 8 | * (C) Copyright 2009, Greg Ungerer <gerg@snapgear.com> |
| 9 | * |
| 10 | * This file is subject to the terms and conditions of the GNU General Public |
| 11 | * License. See the file COPYING in the main directory of this archive |
| 12 | * for more details. |
| 13 | */ |
| 14 | |
| 15 | #include <linux/types.h> |
| 16 | #include <linux/init.h> |
| 17 | #include <linux/kernel.h> |
| 18 | #include <linux/interrupt.h> |
| 19 | #include <linux/irq.h> |
| 20 | #include <linux/io.h> |
| 21 | #include <asm/coldfire.h> |
| 22 | #include <asm/mcfsim.h> |
| 23 | #include <asm/traps.h> |
| 24 | |
| 25 | /* |
| 26 | * Each vector needs a unique priority and level asscoiated with it. |
| 27 | * We don't really care so much what they are, we don't rely on the |
| 28 | * tranditional priority interrupt scheme of the m68k/ColdFire. |
| 29 | */ |
| 30 | static u8 intc_intpri = 0x36; |
| 31 | |
| 32 | static void intc_irq_mask(unsigned int irq) |
| 33 | { |
| 34 | if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) { |
| 35 | unsigned long imraddr; |
| 36 | u32 val, imrbit; |
| 37 | |
| 38 | irq -= MCFINT_VECBASE; |
| 39 | imraddr = MCF_IPSBAR; |
| 40 | imraddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; |
| 41 | imraddr += (irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL; |
| 42 | imrbit = 0x1 << (irq & 0x1f); |
| 43 | |
| 44 | val = __raw_readl(imraddr); |
| 45 | __raw_writel(val | imrbit, imraddr); |
| 46 | } |
| 47 | } |
| 48 | |
| 49 | static void intc_irq_unmask(unsigned int irq) |
| 50 | { |
| 51 | if ((irq >= MCFINT_VECBASE) && (irq <= MCFINT_VECBASE + 128)) { |
| 52 | unsigned long intaddr, imraddr, icraddr; |
| 53 | u32 val, imrbit; |
| 54 | |
| 55 | irq -= MCFINT_VECBASE; |
| 56 | intaddr = MCF_IPSBAR; |
| 57 | intaddr += (irq & 0x40) ? MCFICM_INTC1 : MCFICM_INTC0; |
| 58 | imraddr = intaddr + ((irq & 0x20) ? MCFINTC_IMRH : MCFINTC_IMRL); |
| 59 | icraddr = intaddr + MCFINTC_ICR0 + (irq & 0x3f); |
| 60 | imrbit = 0x1 << (irq & 0x1f); |
| 61 | |
| 62 | /* Don't set the "maskall" bit! */ |
| 63 | if ((irq & 0x20) == 0) |
| 64 | imrbit |= 0x1; |
| 65 | |
| 66 | if (__raw_readb(icraddr) == 0) |
| 67 | __raw_writeb(intc_intpri--, icraddr); |
| 68 | |
| 69 | val = __raw_readl(imraddr); |
| 70 | __raw_writel(val & ~imrbit, imraddr); |
| 71 | } |
| 72 | } |
| 73 | |
| 74 | static struct irq_chip intc_irq_chip = { |
| 75 | .name = "CF-INTC", |
| 76 | .mask = intc_irq_mask, |
| 77 | .unmask = intc_irq_unmask, |
| 78 | }; |
| 79 | |
| 80 | void __init init_IRQ(void) |
| 81 | { |
| 82 | int irq; |
| 83 | |
| 84 | init_vectors(); |
| 85 | |
| 86 | /* Mask all interrupt sources */ |
| 87 | __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC0 + MCFINTC_IMRL); |
| 88 | __raw_writel(0x1, MCF_IPSBAR + MCFICM_INTC1 + MCFINTC_IMRL); |
| 89 | |
| 90 | for (irq = 0; (irq < NR_IRQS); irq++) { |
| 91 | irq_desc[irq].status = IRQ_DISABLED; |
| 92 | irq_desc[irq].action = NULL; |
| 93 | irq_desc[irq].depth = 1; |
| 94 | irq_desc[irq].chip = &intc_irq_chip; |
| 95 | } |
| 96 | } |
| 97 | |