Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1 | /* |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 2 | * drivers/media/platform/samsung/mfc5/s5p_mfc_opr_v5.c |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 3 | * |
| 4 | * Samsung MFC (Multi Function Codec - FIMV) driver |
| 5 | * This file contains hw related functions. |
| 6 | * |
| 7 | * Kamil Debski, Copyright (c) 2011 Samsung Electronics |
| 8 | * http://www.samsung.com/ |
| 9 | * |
| 10 | * This program is free software; you can redistribute it and/or modify |
| 11 | * it under the terms of the GNU General Public License version 2 as |
| 12 | * published by the Free Software Foundation. |
| 13 | */ |
| 14 | |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 15 | #include "s5p_mfc_common.h" |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 16 | #include "s5p_mfc_cmd.h" |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 17 | #include "s5p_mfc_ctrl.h" |
| 18 | #include "s5p_mfc_debug.h" |
| 19 | #include "s5p_mfc_intr.h" |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 20 | #include "s5p_mfc_pm.h" |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 21 | #include "s5p_mfc_opr.h" |
| 22 | #include "s5p_mfc_opr_v5.h" |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 23 | #include <asm/cacheflush.h> |
| 24 | #include <linux/delay.h> |
| 25 | #include <linux/dma-mapping.h> |
| 26 | #include <linux/err.h> |
| 27 | #include <linux/firmware.h> |
| 28 | #include <linux/io.h> |
| 29 | #include <linux/jiffies.h> |
| 30 | #include <linux/mm.h> |
| 31 | #include <linux/sched.h> |
| 32 | |
| 33 | #define OFFSETA(x) (((x) - dev->bank1) >> MFC_OFFSET_SHIFT) |
| 34 | #define OFFSETB(x) (((x) - dev->bank2) >> MFC_OFFSET_SHIFT) |
| 35 | |
| 36 | /* Allocate temporary buffers for decoding */ |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 37 | static int s5p_mfc_alloc_dec_temp_buffers_v5(struct s5p_mfc_ctx *ctx) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 38 | { |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 39 | struct s5p_mfc_dev *dev = ctx->dev; |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 40 | struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv; |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 41 | int ret; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 42 | |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 43 | ctx->dsc.size = buf_size->dsc; |
| 44 | ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->dsc); |
| 45 | if (ret) { |
| 46 | mfc_err("Failed to allocate temporary buffer\n"); |
| 47 | return ret; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 48 | } |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 49 | |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 50 | BUG_ON(ctx->dsc.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 51 | memset(ctx->dsc.virt, 0, ctx->dsc.size); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 52 | wmb(); |
| 53 | return 0; |
| 54 | } |
| 55 | |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 56 | |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 57 | /* Release temporary buffers for decoding */ |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 58 | static void s5p_mfc_release_dec_desc_buffer_v5(struct s5p_mfc_ctx *ctx) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 59 | { |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 60 | s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->dsc); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 61 | } |
| 62 | |
| 63 | /* Allocate codec buffers */ |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 64 | static int s5p_mfc_alloc_codec_buffers_v5(struct s5p_mfc_ctx *ctx) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 65 | { |
| 66 | struct s5p_mfc_dev *dev = ctx->dev; |
| 67 | unsigned int enc_ref_y_size = 0; |
| 68 | unsigned int enc_ref_c_size = 0; |
| 69 | unsigned int guard_width, guard_height; |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 70 | int ret; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 71 | |
| 72 | if (ctx->type == MFCINST_DECODER) { |
| 73 | mfc_debug(2, "Luma size:%d Chroma size:%d MV size:%d\n", |
| 74 | ctx->luma_size, ctx->chroma_size, ctx->mv_size); |
| 75 | mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count); |
| 76 | } else if (ctx->type == MFCINST_ENCODER) { |
| 77 | enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) |
| 78 | * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); |
| 79 | enc_ref_y_size = ALIGN(enc_ref_y_size, S5P_FIMV_NV12MT_SALIGN); |
| 80 | |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 81 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) { |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 82 | enc_ref_c_size = ALIGN(ctx->img_width, |
| 83 | S5P_FIMV_NV12MT_HALIGN) |
| 84 | * ALIGN(ctx->img_height >> 1, |
| 85 | S5P_FIMV_NV12MT_VALIGN); |
| 86 | enc_ref_c_size = ALIGN(enc_ref_c_size, |
| 87 | S5P_FIMV_NV12MT_SALIGN); |
| 88 | } else { |
| 89 | guard_width = ALIGN(ctx->img_width + 16, |
| 90 | S5P_FIMV_NV12MT_HALIGN); |
| 91 | guard_height = ALIGN((ctx->img_height >> 1) + 4, |
| 92 | S5P_FIMV_NV12MT_VALIGN); |
| 93 | enc_ref_c_size = ALIGN(guard_width * guard_height, |
| 94 | S5P_FIMV_NV12MT_SALIGN); |
| 95 | } |
| 96 | mfc_debug(2, "recon luma size: %d chroma size: %d\n", |
| 97 | enc_ref_y_size, enc_ref_c_size); |
| 98 | } else { |
| 99 | return -EINVAL; |
| 100 | } |
| 101 | /* Codecs have different memory requirements */ |
| 102 | switch (ctx->codec_mode) { |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 103 | case S5P_MFC_CODEC_H264_DEC: |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 104 | ctx->bank1.size = |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 105 | ALIGN(S5P_FIMV_DEC_NB_IP_SIZE + |
| 106 | S5P_FIMV_DEC_VERT_NB_MV_SIZE, |
| 107 | S5P_FIMV_DEC_BUF_ALIGN); |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 108 | ctx->bank2.size = ctx->total_dpb_count * ctx->mv_size; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 109 | break; |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 110 | case S5P_MFC_CODEC_MPEG4_DEC: |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 111 | ctx->bank1.size = |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 112 | ALIGN(S5P_FIMV_DEC_NB_DCAC_SIZE + |
| 113 | S5P_FIMV_DEC_UPNB_MV_SIZE + |
| 114 | S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE + |
| 115 | S5P_FIMV_DEC_STX_PARSER_SIZE + |
| 116 | S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE, |
| 117 | S5P_FIMV_DEC_BUF_ALIGN); |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 118 | ctx->bank2.size = 0; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 119 | break; |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 120 | case S5P_MFC_CODEC_VC1RCV_DEC: |
| 121 | case S5P_MFC_CODEC_VC1_DEC: |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 122 | ctx->bank1.size = |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 123 | ALIGN(S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE + |
| 124 | S5P_FIMV_DEC_UPNB_MV_SIZE + |
| 125 | S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE + |
| 126 | S5P_FIMV_DEC_NB_DCAC_SIZE + |
| 127 | 3 * S5P_FIMV_DEC_VC1_BITPLANE_SIZE, |
| 128 | S5P_FIMV_DEC_BUF_ALIGN); |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 129 | ctx->bank2.size = 0; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 130 | break; |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 131 | case S5P_MFC_CODEC_MPEG2_DEC: |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 132 | ctx->bank1.size = 0; |
| 133 | ctx->bank2.size = 0; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 134 | break; |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 135 | case S5P_MFC_CODEC_H263_DEC: |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 136 | ctx->bank1.size = |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 137 | ALIGN(S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE + |
| 138 | S5P_FIMV_DEC_UPNB_MV_SIZE + |
| 139 | S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE + |
| 140 | S5P_FIMV_DEC_NB_DCAC_SIZE, |
| 141 | S5P_FIMV_DEC_BUF_ALIGN); |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 142 | ctx->bank2.size = 0; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 143 | break; |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 144 | case S5P_MFC_CODEC_H264_ENC: |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 145 | ctx->bank1.size = (enc_ref_y_size * 2) + |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 146 | S5P_FIMV_ENC_UPMV_SIZE + |
| 147 | S5P_FIMV_ENC_COLFLG_SIZE + |
| 148 | S5P_FIMV_ENC_INTRAMD_SIZE + |
| 149 | S5P_FIMV_ENC_NBORINFO_SIZE; |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 150 | ctx->bank2.size = (enc_ref_y_size * 2) + |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 151 | (enc_ref_c_size * 4) + |
| 152 | S5P_FIMV_ENC_INTRAPRED_SIZE; |
| 153 | break; |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 154 | case S5P_MFC_CODEC_MPEG4_ENC: |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 155 | ctx->bank1.size = (enc_ref_y_size * 2) + |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 156 | S5P_FIMV_ENC_UPMV_SIZE + |
| 157 | S5P_FIMV_ENC_COLFLG_SIZE + |
| 158 | S5P_FIMV_ENC_ACDCCOEF_SIZE; |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 159 | ctx->bank2.size = (enc_ref_y_size * 2) + |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 160 | (enc_ref_c_size * 4); |
| 161 | break; |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 162 | case S5P_MFC_CODEC_H263_ENC: |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 163 | ctx->bank1.size = (enc_ref_y_size * 2) + |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 164 | S5P_FIMV_ENC_UPMV_SIZE + |
| 165 | S5P_FIMV_ENC_ACDCCOEF_SIZE; |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 166 | ctx->bank2.size = (enc_ref_y_size * 2) + |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 167 | (enc_ref_c_size * 4); |
| 168 | break; |
| 169 | default: |
| 170 | break; |
| 171 | } |
| 172 | /* Allocate only if memory from bank 1 is necessary */ |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 173 | if (ctx->bank1.size > 0) { |
| 174 | |
| 175 | ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->bank1); |
| 176 | if (ret) { |
| 177 | mfc_err("Failed to allocate Bank1 temporary buffer\n"); |
| 178 | return ret; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 179 | } |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 180 | BUG_ON(ctx->bank1.dma & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 181 | } |
| 182 | /* Allocate only if memory from bank 2 is necessary */ |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 183 | if (ctx->bank2.size > 0) { |
| 184 | ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_r, &ctx->bank2); |
| 185 | if (ret) { |
| 186 | mfc_err("Failed to allocate Bank2 temporary buffer\n"); |
| 187 | s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1); |
| 188 | return ret; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 189 | } |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 190 | BUG_ON(ctx->bank2.dma & ((1 << MFC_BANK2_ALIGN_ORDER) - 1)); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 191 | } |
| 192 | return 0; |
| 193 | } |
| 194 | |
| 195 | /* Release buffers allocated for codec */ |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 196 | static void s5p_mfc_release_codec_buffers_v5(struct s5p_mfc_ctx *ctx) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 197 | { |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 198 | s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->bank1); |
| 199 | s5p_mfc_release_priv_buf(ctx->dev->mem_dev_r, &ctx->bank2); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 200 | } |
| 201 | |
| 202 | /* Allocate memory for instance data buffer */ |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 203 | static int s5p_mfc_alloc_instance_buffer_v5(struct s5p_mfc_ctx *ctx) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 204 | { |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 205 | struct s5p_mfc_dev *dev = ctx->dev; |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 206 | struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv; |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 207 | int ret; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 208 | |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 209 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || |
| 210 | ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) |
| 211 | ctx->ctx.size = buf_size->h264_ctx; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 212 | else |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 213 | ctx->ctx.size = buf_size->non_h264_ctx; |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 214 | |
| 215 | ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->ctx); |
| 216 | if (ret) { |
| 217 | mfc_err("Failed to allocate instance buffer\n"); |
| 218 | return ret; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 219 | } |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 220 | ctx->ctx.ofs = OFFSETA(ctx->ctx.dma); |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 221 | |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 222 | /* Zero content of the allocated memory */ |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 223 | memset(ctx->ctx.virt, 0, ctx->ctx.size); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 224 | wmb(); |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 225 | |
| 226 | /* Initialize shared memory */ |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 227 | ctx->shm.size = buf_size->shm; |
| 228 | ret = s5p_mfc_alloc_priv_buf(dev->mem_dev_l, &ctx->shm); |
| 229 | if (ret) { |
| 230 | mfc_err("Failed to allocate shared memory buffer\n"); |
Zhaowei Yuan | 6c5c680 | 2014-08-05 22:22:08 -0300 | [diff] [blame] | 231 | s5p_mfc_release_priv_buf(dev->mem_dev_l, &ctx->ctx); |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 232 | return ret; |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 233 | } |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 234 | |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 235 | /* shared memory offset only keeps the offset from base (port a) */ |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 236 | ctx->shm.ofs = ctx->shm.dma - dev->bank1; |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 237 | BUG_ON(ctx->shm.ofs & ((1 << MFC_BANK1_ALIGN_ORDER) - 1)); |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 238 | |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 239 | memset(ctx->shm.virt, 0, buf_size->shm); |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 240 | wmb(); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 241 | return 0; |
| 242 | } |
| 243 | |
| 244 | /* Release instance buffer */ |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 245 | static void s5p_mfc_release_instance_buffer_v5(struct s5p_mfc_ctx *ctx) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 246 | { |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 247 | s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->ctx); |
| 248 | s5p_mfc_release_priv_buf(ctx->dev->mem_dev_l, &ctx->shm); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 249 | } |
| 250 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 251 | static int s5p_mfc_alloc_dev_context_buffer_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 252 | { |
| 253 | /* NOP */ |
| 254 | |
| 255 | return 0; |
| 256 | } |
| 257 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 258 | static void s5p_mfc_release_dev_context_buffer_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 259 | { |
| 260 | /* NOP */ |
| 261 | } |
| 262 | |
| 263 | static void s5p_mfc_write_info_v5(struct s5p_mfc_ctx *ctx, unsigned int data, |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 264 | unsigned int ofs) |
| 265 | { |
Mauro Carvalho Chehab | d7fa7b0 | 2014-09-24 09:25:56 -0300 | [diff] [blame] | 266 | writel(data, (volatile void __iomem *)(ctx->shm.virt + ofs)); |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 267 | wmb(); |
| 268 | } |
| 269 | |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 270 | static unsigned int s5p_mfc_read_info_v5(struct s5p_mfc_ctx *ctx, |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 271 | unsigned int ofs) |
| 272 | { |
| 273 | rmb(); |
Mauro Carvalho Chehab | d7fa7b0 | 2014-09-24 09:25:56 -0300 | [diff] [blame] | 274 | return readl((volatile void __iomem *)(ctx->shm.virt + ofs)); |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 275 | } |
| 276 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 277 | static void s5p_mfc_dec_calc_dpb_size_v5(struct s5p_mfc_ctx *ctx) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 278 | { |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 279 | unsigned int guard_width, guard_height; |
| 280 | |
| 281 | ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN); |
| 282 | ctx->buf_height = ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); |
| 283 | mfc_debug(2, |
| 284 | "SEQ Done: Movie dimensions %dx%d, buffer dimensions: %dx%d\n", |
| 285 | ctx->img_width, ctx->img_height, ctx->buf_width, |
| 286 | ctx->buf_height); |
| 287 | |
| 288 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) { |
| 289 | ctx->luma_size = ALIGN(ctx->buf_width * ctx->buf_height, |
| 290 | S5P_FIMV_DEC_BUF_ALIGN); |
| 291 | ctx->chroma_size = ALIGN(ctx->buf_width * |
| 292 | ALIGN((ctx->img_height >> 1), |
| 293 | S5P_FIMV_NV12MT_VALIGN), |
| 294 | S5P_FIMV_DEC_BUF_ALIGN); |
| 295 | ctx->mv_size = ALIGN(ctx->buf_width * |
| 296 | ALIGN((ctx->buf_height >> 2), |
| 297 | S5P_FIMV_NV12MT_VALIGN), |
| 298 | S5P_FIMV_DEC_BUF_ALIGN); |
| 299 | } else { |
| 300 | guard_width = |
| 301 | ALIGN(ctx->img_width + 24, S5P_FIMV_NV12MT_HALIGN); |
| 302 | guard_height = |
| 303 | ALIGN(ctx->img_height + 16, S5P_FIMV_NV12MT_VALIGN); |
| 304 | ctx->luma_size = ALIGN(guard_width * guard_height, |
| 305 | S5P_FIMV_DEC_BUF_ALIGN); |
| 306 | |
| 307 | guard_width = |
| 308 | ALIGN(ctx->img_width + 16, S5P_FIMV_NV12MT_HALIGN); |
| 309 | guard_height = |
| 310 | ALIGN((ctx->img_height >> 1) + 4, |
| 311 | S5P_FIMV_NV12MT_VALIGN); |
| 312 | ctx->chroma_size = ALIGN(guard_width * guard_height, |
| 313 | S5P_FIMV_DEC_BUF_ALIGN); |
| 314 | |
| 315 | ctx->mv_size = 0; |
| 316 | } |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 317 | } |
| 318 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 319 | static void s5p_mfc_enc_calc_src_size_v5(struct s5p_mfc_ctx *ctx) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 320 | { |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 321 | if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) { |
| 322 | ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN); |
| 323 | |
| 324 | ctx->luma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN) |
| 325 | * ALIGN(ctx->img_height, S5P_FIMV_NV12M_LVALIGN); |
| 326 | ctx->chroma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12M_HALIGN) |
| 327 | * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12M_CVALIGN); |
| 328 | |
| 329 | ctx->luma_size = ALIGN(ctx->luma_size, S5P_FIMV_NV12M_SALIGN); |
| 330 | ctx->chroma_size = |
| 331 | ALIGN(ctx->chroma_size, S5P_FIMV_NV12M_SALIGN); |
| 332 | } else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) { |
| 333 | ctx->buf_width = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN); |
| 334 | |
| 335 | ctx->luma_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) |
| 336 | * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); |
| 337 | ctx->chroma_size = |
| 338 | ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) |
| 339 | * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN); |
| 340 | |
| 341 | ctx->luma_size = ALIGN(ctx->luma_size, S5P_FIMV_NV12MT_SALIGN); |
| 342 | ctx->chroma_size = |
| 343 | ALIGN(ctx->chroma_size, S5P_FIMV_NV12MT_SALIGN); |
| 344 | } |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 345 | } |
| 346 | |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 347 | /* Set registers for decoding temporary buffers */ |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 348 | static void s5p_mfc_set_dec_desc_buffer(struct s5p_mfc_ctx *ctx) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 349 | { |
| 350 | struct s5p_mfc_dev *dev = ctx->dev; |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 351 | struct s5p_mfc_buf_size_v5 *buf_size = dev->variant->buf_size->priv; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 352 | |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 353 | mfc_write(dev, OFFSETA(ctx->dsc.dma), S5P_FIMV_SI_CH0_DESC_ADR); |
| 354 | mfc_write(dev, buf_size->dsc, S5P_FIMV_SI_CH0_DESC_SIZE); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 355 | } |
| 356 | |
| 357 | /* Set registers for shared buffer */ |
Sachin Kamat | a13bba4 | 2012-05-10 03:32:01 -0300 | [diff] [blame] | 358 | static void s5p_mfc_set_shared_buffer(struct s5p_mfc_ctx *ctx) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 359 | { |
| 360 | struct s5p_mfc_dev *dev = ctx->dev; |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 361 | mfc_write(dev, ctx->shm.ofs, S5P_FIMV_SI_CH0_HOST_WR_ADR); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 362 | } |
| 363 | |
| 364 | /* Set registers for decoding stream buffer */ |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 365 | static int s5p_mfc_set_dec_stream_buffer_v5(struct s5p_mfc_ctx *ctx, |
| 366 | int buf_addr, unsigned int start_num_byte, |
| 367 | unsigned int buf_size) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 368 | { |
| 369 | struct s5p_mfc_dev *dev = ctx->dev; |
| 370 | |
| 371 | mfc_write(dev, OFFSETA(buf_addr), S5P_FIMV_SI_CH0_SB_ST_ADR); |
| 372 | mfc_write(dev, ctx->dec_src_buf_size, S5P_FIMV_SI_CH0_CPB_SIZE); |
| 373 | mfc_write(dev, buf_size, S5P_FIMV_SI_CH0_SB_FRM_SIZE); |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 374 | s5p_mfc_write_info_v5(ctx, start_num_byte, START_BYTE_NUM); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 375 | return 0; |
| 376 | } |
| 377 | |
| 378 | /* Set decoding frame buffer */ |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 379 | static int s5p_mfc_set_dec_frame_buffer_v5(struct s5p_mfc_ctx *ctx) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 380 | { |
Zhaowei Yuan | 9aee8b8 | 2014-09-03 23:28:43 -0300 | [diff] [blame] | 381 | unsigned int frame_size_lu, i; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 382 | unsigned int frame_size_ch, frame_size_mv; |
| 383 | struct s5p_mfc_dev *dev = ctx->dev; |
| 384 | unsigned int dpb; |
| 385 | size_t buf_addr1, buf_addr2; |
| 386 | int buf_size1, buf_size2; |
| 387 | |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 388 | buf_addr1 = ctx->bank1.dma; |
| 389 | buf_size1 = ctx->bank1.size; |
| 390 | buf_addr2 = ctx->bank2.dma; |
| 391 | buf_size2 = ctx->bank2.size; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 392 | dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) & |
| 393 | ~S5P_FIMV_DPB_COUNT_MASK; |
| 394 | mfc_write(dev, ctx->total_dpb_count | dpb, |
| 395 | S5P_FIMV_SI_CH0_DPB_CONF_CTRL); |
| 396 | s5p_mfc_set_shared_buffer(ctx); |
| 397 | switch (ctx->codec_mode) { |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 398 | case S5P_MFC_CODEC_H264_DEC: |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 399 | mfc_write(dev, OFFSETA(buf_addr1), |
| 400 | S5P_FIMV_H264_VERT_NB_MV_ADR); |
| 401 | buf_addr1 += S5P_FIMV_DEC_VERT_NB_MV_SIZE; |
| 402 | buf_size1 -= S5P_FIMV_DEC_VERT_NB_MV_SIZE; |
| 403 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H264_NB_IP_ADR); |
| 404 | buf_addr1 += S5P_FIMV_DEC_NB_IP_SIZE; |
| 405 | buf_size1 -= S5P_FIMV_DEC_NB_IP_SIZE; |
| 406 | break; |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 407 | case S5P_MFC_CODEC_MPEG4_DEC: |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 408 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_NB_DCAC_ADR); |
| 409 | buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE; |
| 410 | buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE; |
| 411 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_NB_MV_ADR); |
| 412 | buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE; |
| 413 | buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE; |
| 414 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SA_MV_ADR); |
| 415 | buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; |
| 416 | buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; |
| 417 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_SP_ADR); |
| 418 | buf_addr1 += S5P_FIMV_DEC_STX_PARSER_SIZE; |
| 419 | buf_size1 -= S5P_FIMV_DEC_STX_PARSER_SIZE; |
| 420 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_OT_LINE_ADR); |
| 421 | buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; |
| 422 | buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; |
| 423 | break; |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 424 | case S5P_MFC_CODEC_H263_DEC: |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 425 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_OT_LINE_ADR); |
| 426 | buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; |
| 427 | buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; |
| 428 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_UP_NB_MV_ADR); |
| 429 | buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE; |
| 430 | buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE; |
| 431 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_SA_MV_ADR); |
| 432 | buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; |
| 433 | buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; |
| 434 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_NB_DCAC_ADR); |
| 435 | buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE; |
| 436 | buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE; |
| 437 | break; |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 438 | case S5P_MFC_CODEC_VC1_DEC: |
| 439 | case S5P_MFC_CODEC_VC1RCV_DEC: |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 440 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_NB_DCAC_ADR); |
| 441 | buf_addr1 += S5P_FIMV_DEC_NB_DCAC_SIZE; |
| 442 | buf_size1 -= S5P_FIMV_DEC_NB_DCAC_SIZE; |
| 443 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_OT_LINE_ADR); |
| 444 | buf_addr1 += S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; |
| 445 | buf_size1 -= S5P_FIMV_DEC_OVERLAP_TRANSFORM_SIZE; |
| 446 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_UP_NB_MV_ADR); |
| 447 | buf_addr1 += S5P_FIMV_DEC_UPNB_MV_SIZE; |
| 448 | buf_size1 -= S5P_FIMV_DEC_UPNB_MV_SIZE; |
| 449 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_SA_MV_ADR); |
| 450 | buf_addr1 += S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; |
| 451 | buf_size1 -= S5P_FIMV_DEC_SUB_ANCHOR_MV_SIZE; |
| 452 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE3_ADR); |
| 453 | buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE; |
| 454 | buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE; |
| 455 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE2_ADR); |
| 456 | buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE; |
| 457 | buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE; |
| 458 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_VC1_BITPLANE1_ADR); |
| 459 | buf_addr1 += S5P_FIMV_DEC_VC1_BITPLANE_SIZE; |
| 460 | buf_size1 -= S5P_FIMV_DEC_VC1_BITPLANE_SIZE; |
| 461 | break; |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 462 | case S5P_MFC_CODEC_MPEG2_DEC: |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 463 | break; |
| 464 | default: |
| 465 | mfc_err("Unknown codec for decoding (%x)\n", |
| 466 | ctx->codec_mode); |
| 467 | return -EINVAL; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 468 | } |
Zhaowei Yuan | 9aee8b8 | 2014-09-03 23:28:43 -0300 | [diff] [blame] | 469 | frame_size_lu = ctx->luma_size; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 470 | frame_size_ch = ctx->chroma_size; |
| 471 | frame_size_mv = ctx->mv_size; |
Zhaowei Yuan | 9aee8b8 | 2014-09-03 23:28:43 -0300 | [diff] [blame] | 472 | mfc_debug(2, "Frm size: %d ch: %d mv: %d\n", frame_size_lu, frame_size_ch, |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 473 | frame_size_mv); |
| 474 | for (i = 0; i < ctx->total_dpb_count; i++) { |
| 475 | /* Bank2 */ |
Mauro Carvalho Chehab | e13f7d5 | 2014-09-24 18:32:54 -0300 | [diff] [blame] | 476 | mfc_debug(2, "Luma %d: %zx\n", i, |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 477 | ctx->dst_bufs[i].cookie.raw.luma); |
| 478 | mfc_write(dev, OFFSETB(ctx->dst_bufs[i].cookie.raw.luma), |
| 479 | S5P_FIMV_DEC_LUMA_ADR + i * 4); |
Mauro Carvalho Chehab | e13f7d5 | 2014-09-24 18:32:54 -0300 | [diff] [blame] | 480 | mfc_debug(2, "\tChroma %d: %zx\n", i, |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 481 | ctx->dst_bufs[i].cookie.raw.chroma); |
| 482 | mfc_write(dev, OFFSETA(ctx->dst_bufs[i].cookie.raw.chroma), |
| 483 | S5P_FIMV_DEC_CHROMA_ADR + i * 4); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 484 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) { |
Mauro Carvalho Chehab | e13f7d5 | 2014-09-24 18:32:54 -0300 | [diff] [blame] | 485 | mfc_debug(2, "\tBuf2: %zx, size: %d\n", |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 486 | buf_addr2, buf_size2); |
| 487 | mfc_write(dev, OFFSETB(buf_addr2), |
| 488 | S5P_FIMV_H264_MV_ADR + i * 4); |
| 489 | buf_addr2 += frame_size_mv; |
| 490 | buf_size2 -= frame_size_mv; |
| 491 | } |
| 492 | } |
Mauro Carvalho Chehab | e13f7d5 | 2014-09-24 18:32:54 -0300 | [diff] [blame] | 493 | mfc_debug(2, "Buf1: %zu, buf_size1: %d\n", buf_addr1, buf_size1); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 494 | mfc_debug(2, "Buf 1/2 size after: %d/%d (frames %d)\n", |
| 495 | buf_size1, buf_size2, ctx->total_dpb_count); |
| 496 | if (buf_size1 < 0 || buf_size2 < 0) { |
| 497 | mfc_debug(2, "Not enough memory has been allocated\n"); |
| 498 | return -ENOMEM; |
| 499 | } |
Zhaowei Yuan | 9aee8b8 | 2014-09-03 23:28:43 -0300 | [diff] [blame] | 500 | s5p_mfc_write_info_v5(ctx, frame_size_lu, ALLOC_LUMA_DPB_SIZE); |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 501 | s5p_mfc_write_info_v5(ctx, frame_size_ch, ALLOC_CHROMA_DPB_SIZE); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 502 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC) |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 503 | s5p_mfc_write_info_v5(ctx, frame_size_mv, ALLOC_MV_SIZE); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 504 | mfc_write(dev, ((S5P_FIMV_CH_INIT_BUFS & S5P_FIMV_CH_MASK) |
| 505 | << S5P_FIMV_CH_SHIFT) | (ctx->inst_no), |
| 506 | S5P_FIMV_SI_CH0_INST_ID); |
| 507 | return 0; |
| 508 | } |
| 509 | |
| 510 | /* Set registers for encoding stream buffer */ |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 511 | static int s5p_mfc_set_enc_stream_buffer_v5(struct s5p_mfc_ctx *ctx, |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 512 | unsigned long addr, unsigned int size) |
| 513 | { |
| 514 | struct s5p_mfc_dev *dev = ctx->dev; |
| 515 | |
| 516 | mfc_write(dev, OFFSETA(addr), S5P_FIMV_ENC_SI_CH0_SB_ADR); |
| 517 | mfc_write(dev, size, S5P_FIMV_ENC_SI_CH0_SB_SIZE); |
| 518 | return 0; |
| 519 | } |
| 520 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 521 | static void s5p_mfc_set_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx, |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 522 | unsigned long y_addr, unsigned long c_addr) |
| 523 | { |
| 524 | struct s5p_mfc_dev *dev = ctx->dev; |
| 525 | |
| 526 | mfc_write(dev, OFFSETB(y_addr), S5P_FIMV_ENC_SI_CH0_CUR_Y_ADR); |
| 527 | mfc_write(dev, OFFSETB(c_addr), S5P_FIMV_ENC_SI_CH0_CUR_C_ADR); |
| 528 | } |
| 529 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 530 | static void s5p_mfc_get_enc_frame_buffer_v5(struct s5p_mfc_ctx *ctx, |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 531 | unsigned long *y_addr, unsigned long *c_addr) |
| 532 | { |
| 533 | struct s5p_mfc_dev *dev = ctx->dev; |
| 534 | |
| 535 | *y_addr = dev->bank2 + (mfc_read(dev, S5P_FIMV_ENCODED_Y_ADDR) |
| 536 | << MFC_OFFSET_SHIFT); |
| 537 | *c_addr = dev->bank2 + (mfc_read(dev, S5P_FIMV_ENCODED_C_ADDR) |
| 538 | << MFC_OFFSET_SHIFT); |
| 539 | } |
| 540 | |
| 541 | /* Set encoding ref & codec buffer */ |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 542 | static int s5p_mfc_set_enc_ref_buffer_v5(struct s5p_mfc_ctx *ctx) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 543 | { |
| 544 | struct s5p_mfc_dev *dev = ctx->dev; |
| 545 | size_t buf_addr1, buf_addr2; |
| 546 | size_t buf_size1, buf_size2; |
| 547 | unsigned int enc_ref_y_size, enc_ref_c_size; |
| 548 | unsigned int guard_width, guard_height; |
| 549 | int i; |
| 550 | |
Kamil Debski | 317b4ca | 2013-01-03 07:06:04 -0300 | [diff] [blame] | 551 | buf_addr1 = ctx->bank1.dma; |
| 552 | buf_size1 = ctx->bank1.size; |
| 553 | buf_addr2 = ctx->bank2.dma; |
| 554 | buf_size2 = ctx->bank2.size; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 555 | enc_ref_y_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) |
| 556 | * ALIGN(ctx->img_height, S5P_FIMV_NV12MT_VALIGN); |
| 557 | enc_ref_y_size = ALIGN(enc_ref_y_size, S5P_FIMV_NV12MT_SALIGN); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 558 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) { |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 559 | enc_ref_c_size = ALIGN(ctx->img_width, S5P_FIMV_NV12MT_HALIGN) |
| 560 | * ALIGN((ctx->img_height >> 1), S5P_FIMV_NV12MT_VALIGN); |
| 561 | enc_ref_c_size = ALIGN(enc_ref_c_size, S5P_FIMV_NV12MT_SALIGN); |
| 562 | } else { |
| 563 | guard_width = ALIGN(ctx->img_width + 16, |
| 564 | S5P_FIMV_NV12MT_HALIGN); |
| 565 | guard_height = ALIGN((ctx->img_height >> 1) + 4, |
| 566 | S5P_FIMV_NV12MT_VALIGN); |
| 567 | enc_ref_c_size = ALIGN(guard_width * guard_height, |
| 568 | S5P_FIMV_NV12MT_SALIGN); |
| 569 | } |
Mauro Carvalho Chehab | 03ce781 | 2014-09-24 19:07:36 -0300 | [diff] [blame^] | 570 | mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n", buf_size1, buf_size2); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 571 | switch (ctx->codec_mode) { |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 572 | case S5P_MFC_CODEC_H264_ENC: |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 573 | for (i = 0; i < 2; i++) { |
| 574 | mfc_write(dev, OFFSETA(buf_addr1), |
| 575 | S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i)); |
| 576 | buf_addr1 += enc_ref_y_size; |
| 577 | buf_size1 -= enc_ref_y_size; |
| 578 | |
| 579 | mfc_write(dev, OFFSETB(buf_addr2), |
| 580 | S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i)); |
| 581 | buf_addr2 += enc_ref_y_size; |
| 582 | buf_size2 -= enc_ref_y_size; |
| 583 | } |
| 584 | for (i = 0; i < 4; i++) { |
| 585 | mfc_write(dev, OFFSETB(buf_addr2), |
| 586 | S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i)); |
| 587 | buf_addr2 += enc_ref_c_size; |
| 588 | buf_size2 -= enc_ref_c_size; |
| 589 | } |
| 590 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H264_UP_MV_ADR); |
| 591 | buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE; |
| 592 | buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE; |
| 593 | mfc_write(dev, OFFSETA(buf_addr1), |
| 594 | S5P_FIMV_H264_COZERO_FLAG_ADR); |
| 595 | buf_addr1 += S5P_FIMV_ENC_COLFLG_SIZE; |
| 596 | buf_size1 -= S5P_FIMV_ENC_COLFLG_SIZE; |
| 597 | mfc_write(dev, OFFSETA(buf_addr1), |
| 598 | S5P_FIMV_H264_UP_INTRA_MD_ADR); |
| 599 | buf_addr1 += S5P_FIMV_ENC_INTRAMD_SIZE; |
| 600 | buf_size1 -= S5P_FIMV_ENC_INTRAMD_SIZE; |
| 601 | mfc_write(dev, OFFSETB(buf_addr2), |
| 602 | S5P_FIMV_H264_UP_INTRA_PRED_ADR); |
| 603 | buf_addr2 += S5P_FIMV_ENC_INTRAPRED_SIZE; |
| 604 | buf_size2 -= S5P_FIMV_ENC_INTRAPRED_SIZE; |
| 605 | mfc_write(dev, OFFSETA(buf_addr1), |
| 606 | S5P_FIMV_H264_NBOR_INFO_ADR); |
| 607 | buf_addr1 += S5P_FIMV_ENC_NBORINFO_SIZE; |
| 608 | buf_size1 -= S5P_FIMV_ENC_NBORINFO_SIZE; |
Mauro Carvalho Chehab | 03ce781 | 2014-09-24 19:07:36 -0300 | [diff] [blame^] | 609 | mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n", |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 610 | buf_size1, buf_size2); |
| 611 | break; |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 612 | case S5P_MFC_CODEC_MPEG4_ENC: |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 613 | for (i = 0; i < 2; i++) { |
| 614 | mfc_write(dev, OFFSETA(buf_addr1), |
| 615 | S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i)); |
| 616 | buf_addr1 += enc_ref_y_size; |
| 617 | buf_size1 -= enc_ref_y_size; |
| 618 | mfc_write(dev, OFFSETB(buf_addr2), |
| 619 | S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i)); |
| 620 | buf_addr2 += enc_ref_y_size; |
| 621 | buf_size2 -= enc_ref_y_size; |
| 622 | } |
| 623 | for (i = 0; i < 4; i++) { |
| 624 | mfc_write(dev, OFFSETB(buf_addr2), |
| 625 | S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i)); |
| 626 | buf_addr2 += enc_ref_c_size; |
| 627 | buf_size2 -= enc_ref_c_size; |
| 628 | } |
| 629 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_MPEG4_UP_MV_ADR); |
| 630 | buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE; |
| 631 | buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE; |
| 632 | mfc_write(dev, OFFSETA(buf_addr1), |
| 633 | S5P_FIMV_MPEG4_COZERO_FLAG_ADR); |
| 634 | buf_addr1 += S5P_FIMV_ENC_COLFLG_SIZE; |
| 635 | buf_size1 -= S5P_FIMV_ENC_COLFLG_SIZE; |
| 636 | mfc_write(dev, OFFSETA(buf_addr1), |
| 637 | S5P_FIMV_MPEG4_ACDC_COEF_ADR); |
| 638 | buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE; |
| 639 | buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE; |
Mauro Carvalho Chehab | 03ce781 | 2014-09-24 19:07:36 -0300 | [diff] [blame^] | 640 | mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n", |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 641 | buf_size1, buf_size2); |
| 642 | break; |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 643 | case S5P_MFC_CODEC_H263_ENC: |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 644 | for (i = 0; i < 2; i++) { |
| 645 | mfc_write(dev, OFFSETA(buf_addr1), |
| 646 | S5P_FIMV_ENC_REF0_LUMA_ADR + (4 * i)); |
| 647 | buf_addr1 += enc_ref_y_size; |
| 648 | buf_size1 -= enc_ref_y_size; |
| 649 | mfc_write(dev, OFFSETB(buf_addr2), |
| 650 | S5P_FIMV_ENC_REF2_LUMA_ADR + (4 * i)); |
| 651 | buf_addr2 += enc_ref_y_size; |
| 652 | buf_size2 -= enc_ref_y_size; |
| 653 | } |
| 654 | for (i = 0; i < 4; i++) { |
| 655 | mfc_write(dev, OFFSETB(buf_addr2), |
| 656 | S5P_FIMV_ENC_REF0_CHROMA_ADR + (4 * i)); |
| 657 | buf_addr2 += enc_ref_c_size; |
| 658 | buf_size2 -= enc_ref_c_size; |
| 659 | } |
| 660 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_UP_MV_ADR); |
| 661 | buf_addr1 += S5P_FIMV_ENC_UPMV_SIZE; |
| 662 | buf_size1 -= S5P_FIMV_ENC_UPMV_SIZE; |
| 663 | mfc_write(dev, OFFSETA(buf_addr1), S5P_FIMV_H263_ACDC_COEF_ADR); |
| 664 | buf_addr1 += S5P_FIMV_ENC_ACDCCOEF_SIZE; |
| 665 | buf_size1 -= S5P_FIMV_ENC_ACDCCOEF_SIZE; |
Mauro Carvalho Chehab | 03ce781 | 2014-09-24 19:07:36 -0300 | [diff] [blame^] | 666 | mfc_debug(2, "buf_size1: %zu, buf_size2: %zu\n", |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 667 | buf_size1, buf_size2); |
| 668 | break; |
| 669 | default: |
| 670 | mfc_err("Unknown codec set for encoding: %d\n", |
| 671 | ctx->codec_mode); |
| 672 | return -EINVAL; |
| 673 | } |
| 674 | return 0; |
| 675 | } |
| 676 | |
| 677 | static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx) |
| 678 | { |
| 679 | struct s5p_mfc_dev *dev = ctx->dev; |
| 680 | struct s5p_mfc_enc_params *p = &ctx->enc_params; |
| 681 | unsigned int reg; |
| 682 | unsigned int shm; |
| 683 | |
| 684 | /* width */ |
| 685 | mfc_write(dev, ctx->img_width, S5P_FIMV_ENC_HSIZE_PX); |
| 686 | /* height */ |
| 687 | mfc_write(dev, ctx->img_height, S5P_FIMV_ENC_VSIZE_PX); |
| 688 | /* pictype : enable, IDR period */ |
| 689 | reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); |
| 690 | reg |= (1 << 18); |
| 691 | reg &= ~(0xFFFF); |
| 692 | reg |= p->gop_size; |
| 693 | mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); |
| 694 | mfc_write(dev, 0, S5P_FIMV_ENC_B_RECON_WRITE_ON); |
| 695 | /* multi-slice control */ |
| 696 | /* multi-slice MB number or bit size */ |
| 697 | mfc_write(dev, p->slice_mode, S5P_FIMV_ENC_MSLICE_CTRL); |
| 698 | if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB) { |
| 699 | mfc_write(dev, p->slice_mb, S5P_FIMV_ENC_MSLICE_MB); |
| 700 | } else if (p->slice_mode == V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES) { |
| 701 | mfc_write(dev, p->slice_bit, S5P_FIMV_ENC_MSLICE_BIT); |
| 702 | } else { |
| 703 | mfc_write(dev, 0, S5P_FIMV_ENC_MSLICE_MB); |
| 704 | mfc_write(dev, 0, S5P_FIMV_ENC_MSLICE_BIT); |
| 705 | } |
| 706 | /* cyclic intra refresh */ |
| 707 | mfc_write(dev, p->intra_refresh_mb, S5P_FIMV_ENC_CIR_CTRL); |
| 708 | /* memory structure cur. frame */ |
| 709 | if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) |
| 710 | mfc_write(dev, 0, S5P_FIMV_ENC_MAP_FOR_CUR); |
| 711 | else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) |
| 712 | mfc_write(dev, 3, S5P_FIMV_ENC_MAP_FOR_CUR); |
| 713 | /* padding control & value */ |
| 714 | reg = mfc_read(dev, S5P_FIMV_ENC_PADDING_CTRL); |
| 715 | if (p->pad) { |
| 716 | /** enable */ |
| 717 | reg |= (1 << 31); |
| 718 | /** cr value */ |
| 719 | reg &= ~(0xFF << 16); |
| 720 | reg |= (p->pad_cr << 16); |
| 721 | /** cb value */ |
| 722 | reg &= ~(0xFF << 8); |
| 723 | reg |= (p->pad_cb << 8); |
| 724 | /** y value */ |
| 725 | reg &= ~(0xFF); |
| 726 | reg |= (p->pad_luma); |
| 727 | } else { |
| 728 | /** disable & all value clear */ |
| 729 | reg = 0; |
| 730 | } |
| 731 | mfc_write(dev, reg, S5P_FIMV_ENC_PADDING_CTRL); |
| 732 | /* rate control config. */ |
| 733 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); |
| 734 | /** frame-level rate control */ |
| 735 | reg &= ~(0x1 << 9); |
| 736 | reg |= (p->rc_frame << 9); |
| 737 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); |
| 738 | /* bit rate */ |
| 739 | if (p->rc_frame) |
| 740 | mfc_write(dev, p->rc_bitrate, |
| 741 | S5P_FIMV_ENC_RC_BIT_RATE); |
| 742 | else |
| 743 | mfc_write(dev, 0, S5P_FIMV_ENC_RC_BIT_RATE); |
| 744 | /* reaction coefficient */ |
| 745 | if (p->rc_frame) |
| 746 | mfc_write(dev, p->rc_reaction_coeff, S5P_FIMV_ENC_RC_RPARA); |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 747 | shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 748 | /* seq header ctrl */ |
| 749 | shm &= ~(0x1 << 3); |
| 750 | shm |= (p->seq_hdr_mode << 3); |
| 751 | /* frame skip mode */ |
| 752 | shm &= ~(0x3 << 1); |
| 753 | shm |= (p->frame_skip_mode << 1); |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 754 | s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 755 | /* fixed target bit */ |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 756 | s5p_mfc_write_info_v5(ctx, p->fixed_target_bit, RC_CONTROL_CONFIG); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 757 | return 0; |
| 758 | } |
| 759 | |
| 760 | static int s5p_mfc_set_enc_params_h264(struct s5p_mfc_ctx *ctx) |
| 761 | { |
| 762 | struct s5p_mfc_dev *dev = ctx->dev; |
| 763 | struct s5p_mfc_enc_params *p = &ctx->enc_params; |
| 764 | struct s5p_mfc_h264_enc_params *p_264 = &p->codec.h264; |
| 765 | unsigned int reg; |
| 766 | unsigned int shm; |
| 767 | |
| 768 | s5p_mfc_set_enc_params(ctx); |
| 769 | /* pictype : number of B */ |
| 770 | reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); |
| 771 | /* num_b_frame - 0 ~ 2 */ |
| 772 | reg &= ~(0x3 << 16); |
| 773 | reg |= (p->num_b_frame << 16); |
| 774 | mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); |
| 775 | /* profile & level */ |
| 776 | reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE); |
| 777 | /* level */ |
| 778 | reg &= ~(0xFF << 8); |
| 779 | reg |= (p_264->level << 8); |
| 780 | /* profile - 0 ~ 2 */ |
| 781 | reg &= ~(0x3F); |
| 782 | reg |= p_264->profile; |
| 783 | mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE); |
| 784 | /* interlace */ |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 785 | mfc_write(dev, p_264->interlace, S5P_FIMV_ENC_PIC_STRUCT); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 786 | /* height */ |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 787 | if (p_264->interlace) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 788 | mfc_write(dev, ctx->img_height >> 1, S5P_FIMV_ENC_VSIZE_PX); |
| 789 | /* loopfilter ctrl */ |
| 790 | mfc_write(dev, p_264->loop_filter_mode, S5P_FIMV_ENC_LF_CTRL); |
| 791 | /* loopfilter alpha offset */ |
| 792 | if (p_264->loop_filter_alpha < 0) { |
| 793 | reg = 0x10; |
| 794 | reg |= (0xFF - p_264->loop_filter_alpha) + 1; |
| 795 | } else { |
| 796 | reg = 0x00; |
| 797 | reg |= (p_264->loop_filter_alpha & 0xF); |
| 798 | } |
| 799 | mfc_write(dev, reg, S5P_FIMV_ENC_ALPHA_OFF); |
| 800 | /* loopfilter beta offset */ |
| 801 | if (p_264->loop_filter_beta < 0) { |
| 802 | reg = 0x10; |
| 803 | reg |= (0xFF - p_264->loop_filter_beta) + 1; |
| 804 | } else { |
| 805 | reg = 0x00; |
| 806 | reg |= (p_264->loop_filter_beta & 0xF); |
| 807 | } |
| 808 | mfc_write(dev, reg, S5P_FIMV_ENC_BETA_OFF); |
| 809 | /* entropy coding mode */ |
| 810 | if (p_264->entropy_mode == V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC) |
| 811 | mfc_write(dev, 1, S5P_FIMV_ENC_H264_ENTROPY_MODE); |
| 812 | else |
| 813 | mfc_write(dev, 0, S5P_FIMV_ENC_H264_ENTROPY_MODE); |
| 814 | /* number of ref. picture */ |
| 815 | reg = mfc_read(dev, S5P_FIMV_ENC_H264_NUM_OF_REF); |
| 816 | /* num of ref. pictures of P */ |
| 817 | reg &= ~(0x3 << 5); |
| 818 | reg |= (p_264->num_ref_pic_4p << 5); |
| 819 | /* max number of ref. pictures */ |
| 820 | reg &= ~(0x1F); |
| 821 | reg |= p_264->max_ref_pic; |
| 822 | mfc_write(dev, reg, S5P_FIMV_ENC_H264_NUM_OF_REF); |
| 823 | /* 8x8 transform enable */ |
| 824 | mfc_write(dev, p_264->_8x8_transform, S5P_FIMV_ENC_H264_TRANS_FLAG); |
| 825 | /* rate control config. */ |
| 826 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); |
| 827 | /* macroblock level rate control */ |
| 828 | reg &= ~(0x1 << 8); |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 829 | reg |= (p->rc_mb << 8); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 830 | /* frame QP */ |
| 831 | reg &= ~(0x3F); |
| 832 | reg |= p_264->rc_frame_qp; |
| 833 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); |
| 834 | /* frame rate */ |
| 835 | if (p->rc_frame && p->rc_framerate_denom) |
| 836 | mfc_write(dev, p->rc_framerate_num * 1000 |
| 837 | / p->rc_framerate_denom, S5P_FIMV_ENC_RC_FRAME_RATE); |
| 838 | else |
| 839 | mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE); |
| 840 | /* max & min value of QP */ |
| 841 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); |
| 842 | /* max QP */ |
| 843 | reg &= ~(0x3F << 8); |
| 844 | reg |= (p_264->rc_max_qp << 8); |
| 845 | /* min QP */ |
| 846 | reg &= ~(0x3F); |
| 847 | reg |= p_264->rc_min_qp; |
| 848 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); |
| 849 | /* macroblock adaptive scaling features */ |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 850 | if (p->rc_mb) { |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 851 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_MB_CTRL); |
| 852 | /* dark region */ |
| 853 | reg &= ~(0x1 << 3); |
| 854 | reg |= (p_264->rc_mb_dark << 3); |
| 855 | /* smooth region */ |
| 856 | reg &= ~(0x1 << 2); |
| 857 | reg |= (p_264->rc_mb_smooth << 2); |
| 858 | /* static region */ |
| 859 | reg &= ~(0x1 << 1); |
| 860 | reg |= (p_264->rc_mb_static << 1); |
| 861 | /* high activity region */ |
| 862 | reg &= ~(0x1); |
| 863 | reg |= p_264->rc_mb_activity; |
| 864 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_MB_CTRL); |
| 865 | } |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 866 | if (!p->rc_frame && !p->rc_mb) { |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 867 | shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 868 | shm &= ~(0xFFF); |
| 869 | shm |= ((p_264->rc_b_frame_qp & 0x3F) << 6); |
| 870 | shm |= (p_264->rc_p_frame_qp & 0x3F); |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 871 | s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 872 | } |
| 873 | /* extended encoder ctrl */ |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 874 | shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 875 | /* AR VUI control */ |
| 876 | shm &= ~(0x1 << 15); |
| 877 | shm |= (p_264->vui_sar << 1); |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 878 | s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 879 | if (p_264->vui_sar) { |
| 880 | /* aspect ration IDC */ |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 881 | shm = s5p_mfc_read_info_v5(ctx, SAMPLE_ASPECT_RATIO_IDC); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 882 | shm &= ~(0xFF); |
| 883 | shm |= p_264->vui_sar_idc; |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 884 | s5p_mfc_write_info_v5(ctx, shm, SAMPLE_ASPECT_RATIO_IDC); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 885 | if (p_264->vui_sar_idc == 0xFF) { |
| 886 | /* sample AR info */ |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 887 | shm = s5p_mfc_read_info_v5(ctx, EXTENDED_SAR); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 888 | shm &= ~(0xFFFFFFFF); |
| 889 | shm |= p_264->vui_ext_sar_width << 16; |
| 890 | shm |= p_264->vui_ext_sar_height; |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 891 | s5p_mfc_write_info_v5(ctx, shm, EXTENDED_SAR); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 892 | } |
| 893 | } |
| 894 | /* intra picture period for H.264 */ |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 895 | shm = s5p_mfc_read_info_v5(ctx, H264_I_PERIOD); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 896 | /* control */ |
| 897 | shm &= ~(0x1 << 16); |
| 898 | shm |= (p_264->open_gop << 16); |
| 899 | /* value */ |
| 900 | if (p_264->open_gop) { |
| 901 | shm &= ~(0xFFFF); |
| 902 | shm |= p_264->open_gop_size; |
| 903 | } |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 904 | s5p_mfc_write_info_v5(ctx, shm, H264_I_PERIOD); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 905 | /* extended encoder ctrl */ |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 906 | shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 907 | /* vbv buffer size */ |
| 908 | if (p->frame_skip_mode == |
| 909 | V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { |
| 910 | shm &= ~(0xFFFF << 16); |
| 911 | shm |= (p_264->cpb_size << 16); |
| 912 | } |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 913 | s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 914 | return 0; |
| 915 | } |
| 916 | |
| 917 | static int s5p_mfc_set_enc_params_mpeg4(struct s5p_mfc_ctx *ctx) |
| 918 | { |
| 919 | struct s5p_mfc_dev *dev = ctx->dev; |
| 920 | struct s5p_mfc_enc_params *p = &ctx->enc_params; |
| 921 | struct s5p_mfc_mpeg4_enc_params *p_mpeg4 = &p->codec.mpeg4; |
| 922 | unsigned int reg; |
| 923 | unsigned int shm; |
| 924 | unsigned int framerate; |
| 925 | |
| 926 | s5p_mfc_set_enc_params(ctx); |
| 927 | /* pictype : number of B */ |
| 928 | reg = mfc_read(dev, S5P_FIMV_ENC_PIC_TYPE_CTRL); |
| 929 | /* num_b_frame - 0 ~ 2 */ |
| 930 | reg &= ~(0x3 << 16); |
| 931 | reg |= (p->num_b_frame << 16); |
| 932 | mfc_write(dev, reg, S5P_FIMV_ENC_PIC_TYPE_CTRL); |
| 933 | /* profile & level */ |
| 934 | reg = mfc_read(dev, S5P_FIMV_ENC_PROFILE); |
| 935 | /* level */ |
| 936 | reg &= ~(0xFF << 8); |
| 937 | reg |= (p_mpeg4->level << 8); |
| 938 | /* profile - 0 ~ 2 */ |
| 939 | reg &= ~(0x3F); |
| 940 | reg |= p_mpeg4->profile; |
| 941 | mfc_write(dev, reg, S5P_FIMV_ENC_PROFILE); |
| 942 | /* quarter_pixel */ |
| 943 | mfc_write(dev, p_mpeg4->quarter_pixel, S5P_FIMV_ENC_MPEG4_QUART_PXL); |
| 944 | /* qp */ |
| 945 | if (!p->rc_frame) { |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 946 | shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 947 | shm &= ~(0xFFF); |
| 948 | shm |= ((p_mpeg4->rc_b_frame_qp & 0x3F) << 6); |
| 949 | shm |= (p_mpeg4->rc_p_frame_qp & 0x3F); |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 950 | s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 951 | } |
| 952 | /* frame rate */ |
| 953 | if (p->rc_frame) { |
| 954 | if (p->rc_framerate_denom > 0) { |
| 955 | framerate = p->rc_framerate_num * 1000 / |
| 956 | p->rc_framerate_denom; |
| 957 | mfc_write(dev, framerate, |
| 958 | S5P_FIMV_ENC_RC_FRAME_RATE); |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 959 | shm = s5p_mfc_read_info_v5(ctx, RC_VOP_TIMING); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 960 | shm &= ~(0xFFFFFFFF); |
| 961 | shm |= (1 << 31); |
| 962 | shm |= ((p->rc_framerate_num & 0x7FFF) << 16); |
| 963 | shm |= (p->rc_framerate_denom & 0xFFFF); |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 964 | s5p_mfc_write_info_v5(ctx, shm, RC_VOP_TIMING); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 965 | } |
| 966 | } else { |
| 967 | mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE); |
| 968 | } |
| 969 | /* rate control config. */ |
| 970 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); |
| 971 | /* frame QP */ |
| 972 | reg &= ~(0x3F); |
| 973 | reg |= p_mpeg4->rc_frame_qp; |
| 974 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); |
| 975 | /* max & min value of QP */ |
| 976 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); |
| 977 | /* max QP */ |
| 978 | reg &= ~(0x3F << 8); |
| 979 | reg |= (p_mpeg4->rc_max_qp << 8); |
| 980 | /* min QP */ |
| 981 | reg &= ~(0x3F); |
| 982 | reg |= p_mpeg4->rc_min_qp; |
| 983 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); |
| 984 | /* extended encoder ctrl */ |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 985 | shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 986 | /* vbv buffer size */ |
| 987 | if (p->frame_skip_mode == |
| 988 | V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { |
| 989 | shm &= ~(0xFFFF << 16); |
| 990 | shm |= (p->vbv_size << 16); |
| 991 | } |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 992 | s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 993 | return 0; |
| 994 | } |
| 995 | |
| 996 | static int s5p_mfc_set_enc_params_h263(struct s5p_mfc_ctx *ctx) |
| 997 | { |
| 998 | struct s5p_mfc_dev *dev = ctx->dev; |
| 999 | struct s5p_mfc_enc_params *p = &ctx->enc_params; |
| 1000 | struct s5p_mfc_mpeg4_enc_params *p_h263 = &p->codec.mpeg4; |
| 1001 | unsigned int reg; |
| 1002 | unsigned int shm; |
| 1003 | |
| 1004 | s5p_mfc_set_enc_params(ctx); |
| 1005 | /* qp */ |
| 1006 | if (!p->rc_frame) { |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 1007 | shm = s5p_mfc_read_info_v5(ctx, P_B_FRAME_QP); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1008 | shm &= ~(0xFFF); |
| 1009 | shm |= (p_h263->rc_p_frame_qp & 0x3F); |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 1010 | s5p_mfc_write_info_v5(ctx, shm, P_B_FRAME_QP); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1011 | } |
| 1012 | /* frame rate */ |
| 1013 | if (p->rc_frame && p->rc_framerate_denom) |
| 1014 | mfc_write(dev, p->rc_framerate_num * 1000 |
| 1015 | / p->rc_framerate_denom, S5P_FIMV_ENC_RC_FRAME_RATE); |
| 1016 | else |
| 1017 | mfc_write(dev, 0, S5P_FIMV_ENC_RC_FRAME_RATE); |
| 1018 | /* rate control config. */ |
| 1019 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_CONFIG); |
| 1020 | /* frame QP */ |
| 1021 | reg &= ~(0x3F); |
| 1022 | reg |= p_h263->rc_frame_qp; |
| 1023 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_CONFIG); |
| 1024 | /* max & min value of QP */ |
| 1025 | reg = mfc_read(dev, S5P_FIMV_ENC_RC_QBOUND); |
| 1026 | /* max QP */ |
| 1027 | reg &= ~(0x3F << 8); |
| 1028 | reg |= (p_h263->rc_max_qp << 8); |
| 1029 | /* min QP */ |
| 1030 | reg &= ~(0x3F); |
| 1031 | reg |= p_h263->rc_min_qp; |
| 1032 | mfc_write(dev, reg, S5P_FIMV_ENC_RC_QBOUND); |
| 1033 | /* extended encoder ctrl */ |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 1034 | shm = s5p_mfc_read_info_v5(ctx, EXT_ENC_CONTROL); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1035 | /* vbv buffer size */ |
| 1036 | if (p->frame_skip_mode == |
| 1037 | V4L2_MPEG_MFC51_VIDEO_FRAME_SKIP_MODE_BUF_LIMIT) { |
| 1038 | shm &= ~(0xFFFF << 16); |
| 1039 | shm |= (p->vbv_size << 16); |
| 1040 | } |
Arun Kumar K | 77a788f | 2012-10-03 22:19:07 -0300 | [diff] [blame] | 1041 | s5p_mfc_write_info_v5(ctx, shm, EXT_ENC_CONTROL); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1042 | return 0; |
| 1043 | } |
| 1044 | |
| 1045 | /* Initialize decoding */ |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1046 | static int s5p_mfc_init_decode_v5(struct s5p_mfc_ctx *ctx) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1047 | { |
| 1048 | struct s5p_mfc_dev *dev = ctx->dev; |
| 1049 | |
| 1050 | s5p_mfc_set_shared_buffer(ctx); |
| 1051 | /* Setup loop filter, for decoding this is only valid for MPEG4 */ |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1052 | if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_DEC) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1053 | mfc_write(dev, ctx->loop_filter_mpeg4, S5P_FIMV_ENC_LF_CTRL); |
| 1054 | else |
| 1055 | mfc_write(dev, 0, S5P_FIMV_ENC_LF_CTRL); |
| 1056 | mfc_write(dev, ((ctx->slice_interface & S5P_FIMV_SLICE_INT_MASK) << |
| 1057 | S5P_FIMV_SLICE_INT_SHIFT) | (ctx->display_delay_enable << |
| 1058 | S5P_FIMV_DDELAY_ENA_SHIFT) | ((ctx->display_delay & |
| 1059 | S5P_FIMV_DDELAY_VAL_MASK) << S5P_FIMV_DDELAY_VAL_SHIFT), |
| 1060 | S5P_FIMV_SI_CH0_DPB_CONF_CTRL); |
| 1061 | mfc_write(dev, |
| 1062 | ((S5P_FIMV_CH_SEQ_HEADER & S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT) |
| 1063 | | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); |
| 1064 | return 0; |
| 1065 | } |
| 1066 | |
| 1067 | static void s5p_mfc_set_flush(struct s5p_mfc_ctx *ctx, int flush) |
| 1068 | { |
| 1069 | struct s5p_mfc_dev *dev = ctx->dev; |
| 1070 | unsigned int dpb; |
| 1071 | |
| 1072 | if (flush) |
| 1073 | dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) | ( |
| 1074 | S5P_FIMV_DPB_FLUSH_MASK << S5P_FIMV_DPB_FLUSH_SHIFT); |
| 1075 | else |
| 1076 | dpb = mfc_read(dev, S5P_FIMV_SI_CH0_DPB_CONF_CTRL) & |
| 1077 | ~(S5P_FIMV_DPB_FLUSH_MASK << S5P_FIMV_DPB_FLUSH_SHIFT); |
| 1078 | mfc_write(dev, dpb, S5P_FIMV_SI_CH0_DPB_CONF_CTRL); |
| 1079 | } |
| 1080 | |
| 1081 | /* Decode a single frame */ |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1082 | static int s5p_mfc_decode_one_frame_v5(struct s5p_mfc_ctx *ctx, |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1083 | enum s5p_mfc_decode_arg last_frame) |
| 1084 | { |
| 1085 | struct s5p_mfc_dev *dev = ctx->dev; |
| 1086 | |
| 1087 | mfc_write(dev, ctx->dec_dst_flag, S5P_FIMV_SI_CH0_RELEASE_BUF); |
| 1088 | s5p_mfc_set_shared_buffer(ctx); |
| 1089 | s5p_mfc_set_flush(ctx, ctx->dpb_flush_flag); |
| 1090 | /* Issue different commands to instance basing on whether it |
| 1091 | * is the last frame or not. */ |
| 1092 | switch (last_frame) { |
| 1093 | case MFC_DEC_FRAME: |
| 1094 | mfc_write(dev, ((S5P_FIMV_CH_FRAME_START & S5P_FIMV_CH_MASK) << |
| 1095 | S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); |
| 1096 | break; |
| 1097 | case MFC_DEC_LAST_FRAME: |
| 1098 | mfc_write(dev, ((S5P_FIMV_CH_LAST_FRAME & S5P_FIMV_CH_MASK) << |
| 1099 | S5P_FIMV_CH_SHIFT) | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); |
| 1100 | break; |
| 1101 | case MFC_DEC_RES_CHANGE: |
| 1102 | mfc_write(dev, ((S5P_FIMV_CH_FRAME_START_REALLOC & |
| 1103 | S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT) | (ctx->inst_no), |
| 1104 | S5P_FIMV_SI_CH0_INST_ID); |
| 1105 | break; |
| 1106 | } |
| 1107 | mfc_debug(2, "Decoding a usual frame\n"); |
| 1108 | return 0; |
| 1109 | } |
| 1110 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1111 | static int s5p_mfc_init_encode_v5(struct s5p_mfc_ctx *ctx) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1112 | { |
| 1113 | struct s5p_mfc_dev *dev = ctx->dev; |
| 1114 | |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1115 | if (ctx->codec_mode == S5P_MFC_CODEC_H264_ENC) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1116 | s5p_mfc_set_enc_params_h264(ctx); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1117 | else if (ctx->codec_mode == S5P_MFC_CODEC_MPEG4_ENC) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1118 | s5p_mfc_set_enc_params_mpeg4(ctx); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1119 | else if (ctx->codec_mode == S5P_MFC_CODEC_H263_ENC) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1120 | s5p_mfc_set_enc_params_h263(ctx); |
| 1121 | else { |
| 1122 | mfc_err("Unknown codec for encoding (%x)\n", |
| 1123 | ctx->codec_mode); |
| 1124 | return -EINVAL; |
| 1125 | } |
| 1126 | s5p_mfc_set_shared_buffer(ctx); |
| 1127 | mfc_write(dev, ((S5P_FIMV_CH_SEQ_HEADER << 16) & 0x70000) | |
| 1128 | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); |
| 1129 | return 0; |
| 1130 | } |
| 1131 | |
| 1132 | /* Encode a single frame */ |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1133 | static int s5p_mfc_encode_one_frame_v5(struct s5p_mfc_ctx *ctx) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1134 | { |
| 1135 | struct s5p_mfc_dev *dev = ctx->dev; |
Andrzej Hajda | f9f715a | 2012-08-21 08:05:32 -0300 | [diff] [blame] | 1136 | int cmd; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1137 | /* memory structure cur. frame */ |
| 1138 | if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12M) |
| 1139 | mfc_write(dev, 0, S5P_FIMV_ENC_MAP_FOR_CUR); |
| 1140 | else if (ctx->src_fmt->fourcc == V4L2_PIX_FMT_NV12MT) |
| 1141 | mfc_write(dev, 3, S5P_FIMV_ENC_MAP_FOR_CUR); |
| 1142 | s5p_mfc_set_shared_buffer(ctx); |
Andrzej Hajda | f9f715a | 2012-08-21 08:05:32 -0300 | [diff] [blame] | 1143 | |
| 1144 | if (ctx->state == MFCINST_FINISHING) |
| 1145 | cmd = S5P_FIMV_CH_LAST_FRAME; |
| 1146 | else |
| 1147 | cmd = S5P_FIMV_CH_FRAME_START; |
| 1148 | mfc_write(dev, ((cmd & S5P_FIMV_CH_MASK) << S5P_FIMV_CH_SHIFT) |
| 1149 | | (ctx->inst_no), S5P_FIMV_SI_CH0_INST_ID); |
| 1150 | |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1151 | return 0; |
| 1152 | } |
| 1153 | |
| 1154 | static int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev) |
| 1155 | { |
| 1156 | unsigned long flags; |
| 1157 | int new_ctx; |
| 1158 | int cnt; |
| 1159 | |
| 1160 | spin_lock_irqsave(&dev->condlock, flags); |
| 1161 | new_ctx = (dev->curr_ctx + 1) % MFC_NUM_CONTEXTS; |
| 1162 | cnt = 0; |
| 1163 | while (!test_bit(new_ctx, &dev->ctx_work_bits)) { |
| 1164 | new_ctx = (new_ctx + 1) % MFC_NUM_CONTEXTS; |
| 1165 | if (++cnt > MFC_NUM_CONTEXTS) { |
| 1166 | /* No contexts to run */ |
| 1167 | spin_unlock_irqrestore(&dev->condlock, flags); |
| 1168 | return -EAGAIN; |
| 1169 | } |
| 1170 | } |
| 1171 | spin_unlock_irqrestore(&dev->condlock, flags); |
| 1172 | return new_ctx; |
| 1173 | } |
| 1174 | |
| 1175 | static void s5p_mfc_run_res_change(struct s5p_mfc_ctx *ctx) |
| 1176 | { |
| 1177 | struct s5p_mfc_dev *dev = ctx->dev; |
| 1178 | |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1179 | s5p_mfc_set_dec_stream_buffer_v5(ctx, 0, 0, 0); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1180 | dev->curr_ctx = ctx->num; |
| 1181 | s5p_mfc_clean_ctx_int_flags(ctx); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1182 | s5p_mfc_decode_one_frame_v5(ctx, MFC_DEC_RES_CHANGE); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1183 | } |
| 1184 | |
| 1185 | static int s5p_mfc_run_dec_frame(struct s5p_mfc_ctx *ctx, int last_frame) |
| 1186 | { |
| 1187 | struct s5p_mfc_dev *dev = ctx->dev; |
| 1188 | struct s5p_mfc_buf *temp_vb; |
| 1189 | unsigned long flags; |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1190 | |
Kamil Debski | a34026e | 2013-01-11 12:29:33 -0300 | [diff] [blame] | 1191 | if (ctx->state == MFCINST_FINISHING) { |
| 1192 | last_frame = MFC_DEC_LAST_FRAME; |
| 1193 | s5p_mfc_set_dec_stream_buffer_v5(ctx, 0, 0, 0); |
| 1194 | dev->curr_ctx = ctx->num; |
| 1195 | s5p_mfc_clean_ctx_int_flags(ctx); |
| 1196 | s5p_mfc_decode_one_frame_v5(ctx, last_frame); |
| 1197 | return 0; |
| 1198 | } |
| 1199 | |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1200 | spin_lock_irqsave(&dev->irqlock, flags); |
| 1201 | /* Frames are being decoded */ |
| 1202 | if (list_empty(&ctx->src_queue)) { |
| 1203 | mfc_debug(2, "No src buffers\n"); |
| 1204 | spin_unlock_irqrestore(&dev->irqlock, flags); |
| 1205 | return -EAGAIN; |
| 1206 | } |
| 1207 | /* Get the next source buffer */ |
| 1208 | temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); |
Andrzej Hajda | f9f715a | 2012-08-21 08:05:32 -0300 | [diff] [blame] | 1209 | temp_vb->flags |= MFC_BUF_FLAG_USED; |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1210 | s5p_mfc_set_dec_stream_buffer_v5(ctx, |
| 1211 | vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), |
| 1212 | ctx->consumed_stream, temp_vb->b->v4l2_planes[0].bytesused); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1213 | spin_unlock_irqrestore(&dev->irqlock, flags); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1214 | dev->curr_ctx = ctx->num; |
| 1215 | s5p_mfc_clean_ctx_int_flags(ctx); |
| 1216 | if (temp_vb->b->v4l2_planes[0].bytesused == 0) { |
| 1217 | last_frame = MFC_DEC_LAST_FRAME; |
| 1218 | mfc_debug(2, "Setting ctx->state to FINISHING\n"); |
| 1219 | ctx->state = MFCINST_FINISHING; |
| 1220 | } |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1221 | s5p_mfc_decode_one_frame_v5(ctx, last_frame); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1222 | return 0; |
| 1223 | } |
| 1224 | |
| 1225 | static int s5p_mfc_run_enc_frame(struct s5p_mfc_ctx *ctx) |
| 1226 | { |
| 1227 | struct s5p_mfc_dev *dev = ctx->dev; |
| 1228 | unsigned long flags; |
| 1229 | struct s5p_mfc_buf *dst_mb; |
| 1230 | struct s5p_mfc_buf *src_mb; |
| 1231 | unsigned long src_y_addr, src_c_addr, dst_addr; |
| 1232 | unsigned int dst_size; |
| 1233 | |
| 1234 | spin_lock_irqsave(&dev->irqlock, flags); |
Andrzej Hajda | f9f715a | 2012-08-21 08:05:32 -0300 | [diff] [blame] | 1235 | if (list_empty(&ctx->src_queue) && ctx->state != MFCINST_FINISHING) { |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1236 | mfc_debug(2, "no src buffers\n"); |
| 1237 | spin_unlock_irqrestore(&dev->irqlock, flags); |
| 1238 | return -EAGAIN; |
| 1239 | } |
| 1240 | if (list_empty(&ctx->dst_queue)) { |
| 1241 | mfc_debug(2, "no dst buffers\n"); |
| 1242 | spin_unlock_irqrestore(&dev->irqlock, flags); |
| 1243 | return -EAGAIN; |
| 1244 | } |
Andrzej Hajda | f9f715a | 2012-08-21 08:05:32 -0300 | [diff] [blame] | 1245 | if (list_empty(&ctx->src_queue)) { |
| 1246 | /* send null frame */ |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1247 | s5p_mfc_set_enc_frame_buffer_v5(ctx, dev->bank2, dev->bank2); |
Andrzej Hajda | f9f715a | 2012-08-21 08:05:32 -0300 | [diff] [blame] | 1248 | src_mb = NULL; |
| 1249 | } else { |
| 1250 | src_mb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, |
| 1251 | list); |
| 1252 | src_mb->flags |= MFC_BUF_FLAG_USED; |
| 1253 | if (src_mb->b->v4l2_planes[0].bytesused == 0) { |
| 1254 | /* send null frame */ |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1255 | s5p_mfc_set_enc_frame_buffer_v5(ctx, dev->bank2, |
Andrzej Hajda | f9f715a | 2012-08-21 08:05:32 -0300 | [diff] [blame] | 1256 | dev->bank2); |
| 1257 | ctx->state = MFCINST_FINISHING; |
| 1258 | } else { |
| 1259 | src_y_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, |
| 1260 | 0); |
| 1261 | src_c_addr = vb2_dma_contig_plane_dma_addr(src_mb->b, |
| 1262 | 1); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1263 | s5p_mfc_set_enc_frame_buffer_v5(ctx, src_y_addr, |
Andrzej Hajda | f9f715a | 2012-08-21 08:05:32 -0300 | [diff] [blame] | 1264 | src_c_addr); |
| 1265 | if (src_mb->flags & MFC_BUF_FLAG_EOS) |
| 1266 | ctx->state = MFCINST_FINISHING; |
| 1267 | } |
| 1268 | } |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1269 | dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); |
Andrzej Hajda | f9f715a | 2012-08-21 08:05:32 -0300 | [diff] [blame] | 1270 | dst_mb->flags |= MFC_BUF_FLAG_USED; |
Marek Szyprowski | ba7fcb0 | 2011-08-29 03:20:56 -0300 | [diff] [blame] | 1271 | dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1272 | dst_size = vb2_plane_size(dst_mb->b, 0); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1273 | s5p_mfc_set_enc_stream_buffer_v5(ctx, dst_addr, dst_size); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1274 | spin_unlock_irqrestore(&dev->irqlock, flags); |
| 1275 | dev->curr_ctx = ctx->num; |
| 1276 | s5p_mfc_clean_ctx_int_flags(ctx); |
Andrzej Hajda | 4130eab | 2013-05-28 03:26:16 -0300 | [diff] [blame] | 1277 | mfc_debug(2, "encoding buffer with index=%d state=%d\n", |
| 1278 | src_mb ? src_mb->b->v4l2_buf.index : -1, ctx->state); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1279 | s5p_mfc_encode_one_frame_v5(ctx); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1280 | return 0; |
| 1281 | } |
| 1282 | |
| 1283 | static void s5p_mfc_run_init_dec(struct s5p_mfc_ctx *ctx) |
| 1284 | { |
| 1285 | struct s5p_mfc_dev *dev = ctx->dev; |
| 1286 | unsigned long flags; |
| 1287 | struct s5p_mfc_buf *temp_vb; |
| 1288 | |
| 1289 | /* Initializing decoding - parsing header */ |
| 1290 | spin_lock_irqsave(&dev->irqlock, flags); |
| 1291 | mfc_debug(2, "Preparing to init decoding\n"); |
| 1292 | temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); |
| 1293 | s5p_mfc_set_dec_desc_buffer(ctx); |
| 1294 | mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1295 | s5p_mfc_set_dec_stream_buffer_v5(ctx, |
Marek Szyprowski | ba7fcb0 | 2011-08-29 03:20:56 -0300 | [diff] [blame] | 1296 | vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1297 | 0, temp_vb->b->v4l2_planes[0].bytesused); |
| 1298 | spin_unlock_irqrestore(&dev->irqlock, flags); |
| 1299 | dev->curr_ctx = ctx->num; |
| 1300 | s5p_mfc_clean_ctx_int_flags(ctx); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1301 | s5p_mfc_init_decode_v5(ctx); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1302 | } |
| 1303 | |
| 1304 | static void s5p_mfc_run_init_enc(struct s5p_mfc_ctx *ctx) |
| 1305 | { |
| 1306 | struct s5p_mfc_dev *dev = ctx->dev; |
| 1307 | unsigned long flags; |
| 1308 | struct s5p_mfc_buf *dst_mb; |
| 1309 | unsigned long dst_addr; |
| 1310 | unsigned int dst_size; |
| 1311 | |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1312 | s5p_mfc_set_enc_ref_buffer_v5(ctx); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1313 | spin_lock_irqsave(&dev->irqlock, flags); |
| 1314 | dst_mb = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf, list); |
Marek Szyprowski | ba7fcb0 | 2011-08-29 03:20:56 -0300 | [diff] [blame] | 1315 | dst_addr = vb2_dma_contig_plane_dma_addr(dst_mb->b, 0); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1316 | dst_size = vb2_plane_size(dst_mb->b, 0); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1317 | s5p_mfc_set_enc_stream_buffer_v5(ctx, dst_addr, dst_size); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1318 | spin_unlock_irqrestore(&dev->irqlock, flags); |
| 1319 | dev->curr_ctx = ctx->num; |
| 1320 | s5p_mfc_clean_ctx_int_flags(ctx); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1321 | s5p_mfc_init_encode_v5(ctx); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1322 | } |
| 1323 | |
| 1324 | static int s5p_mfc_run_init_dec_buffers(struct s5p_mfc_ctx *ctx) |
| 1325 | { |
| 1326 | struct s5p_mfc_dev *dev = ctx->dev; |
| 1327 | unsigned long flags; |
| 1328 | struct s5p_mfc_buf *temp_vb; |
| 1329 | int ret; |
| 1330 | |
| 1331 | /* |
| 1332 | * Header was parsed now starting processing |
| 1333 | * First set the output frame buffers |
| 1334 | */ |
| 1335 | if (ctx->capture_state != QUEUE_BUFS_MMAPED) { |
| 1336 | mfc_err("It seems that not all destionation buffers were " |
| 1337 | "mmaped\nMFC requires that all destination are mmaped " |
| 1338 | "before starting processing\n"); |
| 1339 | return -EAGAIN; |
| 1340 | } |
| 1341 | spin_lock_irqsave(&dev->irqlock, flags); |
| 1342 | if (list_empty(&ctx->src_queue)) { |
| 1343 | mfc_err("Header has been deallocated in the middle of" |
| 1344 | " initialization\n"); |
| 1345 | spin_unlock_irqrestore(&dev->irqlock, flags); |
| 1346 | return -EIO; |
| 1347 | } |
| 1348 | temp_vb = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list); |
| 1349 | mfc_debug(2, "Header size: %d\n", temp_vb->b->v4l2_planes[0].bytesused); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1350 | s5p_mfc_set_dec_stream_buffer_v5(ctx, |
Marek Szyprowski | ba7fcb0 | 2011-08-29 03:20:56 -0300 | [diff] [blame] | 1351 | vb2_dma_contig_plane_dma_addr(temp_vb->b, 0), |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1352 | 0, temp_vb->b->v4l2_planes[0].bytesused); |
| 1353 | spin_unlock_irqrestore(&dev->irqlock, flags); |
| 1354 | dev->curr_ctx = ctx->num; |
| 1355 | s5p_mfc_clean_ctx_int_flags(ctx); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1356 | ret = s5p_mfc_set_dec_frame_buffer_v5(ctx); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1357 | if (ret) { |
| 1358 | mfc_err("Failed to alloc frame mem\n"); |
| 1359 | ctx->state = MFCINST_ERROR; |
| 1360 | } |
| 1361 | return ret; |
| 1362 | } |
| 1363 | |
| 1364 | /* Try running an operation on hardware */ |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1365 | static void s5p_mfc_try_run_v5(struct s5p_mfc_dev *dev) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1366 | { |
| 1367 | struct s5p_mfc_ctx *ctx; |
| 1368 | int new_ctx; |
| 1369 | unsigned int ret = 0; |
| 1370 | |
| 1371 | if (test_bit(0, &dev->enter_suspend)) { |
| 1372 | mfc_debug(1, "Entering suspend so do not schedule any jobs\n"); |
| 1373 | return; |
| 1374 | } |
| 1375 | /* Check whether hardware is not running */ |
| 1376 | if (test_and_set_bit(0, &dev->hw_lock) != 0) { |
| 1377 | /* This is perfectly ok, the scheduled ctx should wait */ |
| 1378 | mfc_debug(1, "Couldn't lock HW\n"); |
| 1379 | return; |
| 1380 | } |
| 1381 | /* Choose the context to run */ |
| 1382 | new_ctx = s5p_mfc_get_new_ctx(dev); |
| 1383 | if (new_ctx < 0) { |
| 1384 | /* No contexts to run */ |
| 1385 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) { |
| 1386 | mfc_err("Failed to unlock hardware\n"); |
| 1387 | return; |
| 1388 | } |
| 1389 | mfc_debug(1, "No ctx is scheduled to be run\n"); |
| 1390 | return; |
| 1391 | } |
| 1392 | ctx = dev->ctx[new_ctx]; |
| 1393 | /* Got context to run in ctx */ |
| 1394 | /* |
| 1395 | * Last frame has already been sent to MFC. |
| 1396 | * Now obtaining frames from MFC buffer |
| 1397 | */ |
| 1398 | s5p_mfc_clock_on(); |
| 1399 | if (ctx->type == MFCINST_DECODER) { |
| 1400 | s5p_mfc_set_dec_desc_buffer(ctx); |
| 1401 | switch (ctx->state) { |
| 1402 | case MFCINST_FINISHING: |
| 1403 | s5p_mfc_run_dec_frame(ctx, MFC_DEC_LAST_FRAME); |
| 1404 | break; |
| 1405 | case MFCINST_RUNNING: |
| 1406 | ret = s5p_mfc_run_dec_frame(ctx, MFC_DEC_FRAME); |
| 1407 | break; |
| 1408 | case MFCINST_INIT: |
| 1409 | s5p_mfc_clean_ctx_int_flags(ctx); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1410 | ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd, |
| 1411 | ctx); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1412 | break; |
| 1413 | case MFCINST_RETURN_INST: |
| 1414 | s5p_mfc_clean_ctx_int_flags(ctx); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1415 | ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd, |
| 1416 | ctx); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1417 | break; |
| 1418 | case MFCINST_GOT_INST: |
| 1419 | s5p_mfc_run_init_dec(ctx); |
| 1420 | break; |
| 1421 | case MFCINST_HEAD_PARSED: |
| 1422 | ret = s5p_mfc_run_init_dec_buffers(ctx); |
| 1423 | mfc_debug(1, "head parsed\n"); |
| 1424 | break; |
| 1425 | case MFCINST_RES_CHANGE_INIT: |
| 1426 | s5p_mfc_run_res_change(ctx); |
| 1427 | break; |
| 1428 | case MFCINST_RES_CHANGE_FLUSH: |
| 1429 | s5p_mfc_run_dec_frame(ctx, MFC_DEC_FRAME); |
| 1430 | break; |
| 1431 | case MFCINST_RES_CHANGE_END: |
| 1432 | mfc_debug(2, "Finished remaining frames after resolution change\n"); |
| 1433 | ctx->capture_state = QUEUE_FREE; |
| 1434 | mfc_debug(2, "Will re-init the codec\n"); |
| 1435 | s5p_mfc_run_init_dec(ctx); |
| 1436 | break; |
| 1437 | default: |
| 1438 | ret = -EAGAIN; |
| 1439 | } |
| 1440 | } else if (ctx->type == MFCINST_ENCODER) { |
| 1441 | switch (ctx->state) { |
| 1442 | case MFCINST_FINISHING: |
| 1443 | case MFCINST_RUNNING: |
| 1444 | ret = s5p_mfc_run_enc_frame(ctx); |
| 1445 | break; |
| 1446 | case MFCINST_INIT: |
| 1447 | s5p_mfc_clean_ctx_int_flags(ctx); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1448 | ret = s5p_mfc_hw_call(dev->mfc_cmds, open_inst_cmd, |
| 1449 | ctx); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1450 | break; |
| 1451 | case MFCINST_RETURN_INST: |
| 1452 | s5p_mfc_clean_ctx_int_flags(ctx); |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1453 | ret = s5p_mfc_hw_call(dev->mfc_cmds, close_inst_cmd, |
| 1454 | ctx); |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1455 | break; |
| 1456 | case MFCINST_GOT_INST: |
| 1457 | s5p_mfc_run_init_enc(ctx); |
| 1458 | break; |
| 1459 | default: |
| 1460 | ret = -EAGAIN; |
| 1461 | } |
| 1462 | } else { |
| 1463 | mfc_err("Invalid context type: %d\n", ctx->type); |
| 1464 | ret = -EAGAIN; |
| 1465 | } |
| 1466 | |
| 1467 | if (ret) { |
| 1468 | /* Free hardware lock */ |
| 1469 | if (test_and_clear_bit(0, &dev->hw_lock) == 0) |
| 1470 | mfc_err("Failed to unlock hardware\n"); |
| 1471 | |
| 1472 | /* This is in deed imporant, as no operation has been |
| 1473 | * scheduled, reduce the clock count as no one will |
| 1474 | * ever do this, because no interrupt related to this try_run |
| 1475 | * will ever come from hardware. */ |
| 1476 | s5p_mfc_clock_off(); |
| 1477 | } |
| 1478 | } |
| 1479 | |
| 1480 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1481 | static void s5p_mfc_cleanup_queue_v5(struct list_head *lh, struct vb2_queue *vq) |
Kamil Debski | af93574 | 2011-06-21 10:51:26 -0300 | [diff] [blame] | 1482 | { |
| 1483 | struct s5p_mfc_buf *b; |
| 1484 | int i; |
| 1485 | |
| 1486 | while (!list_empty(lh)) { |
| 1487 | b = list_entry(lh->next, struct s5p_mfc_buf, list); |
| 1488 | for (i = 0; i < b->b->num_planes; i++) |
| 1489 | vb2_set_plane_payload(b->b, i, 0); |
| 1490 | vb2_buffer_done(b->b, VB2_BUF_STATE_ERROR); |
| 1491 | list_del(&b->list); |
| 1492 | } |
| 1493 | } |
| 1494 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1495 | static void s5p_mfc_clear_int_flags_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1496 | { |
| 1497 | mfc_write(dev, 0, S5P_FIMV_RISC_HOST_INT); |
| 1498 | mfc_write(dev, 0, S5P_FIMV_RISC2HOST_CMD); |
| 1499 | mfc_write(dev, 0xffff, S5P_FIMV_SI_RTN_CHID); |
| 1500 | } |
| 1501 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1502 | static int s5p_mfc_get_dspl_y_adr_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1503 | { |
| 1504 | return mfc_read(dev, S5P_FIMV_SI_DISPLAY_Y_ADR) << MFC_OFFSET_SHIFT; |
| 1505 | } |
| 1506 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1507 | static int s5p_mfc_get_dec_y_adr_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1508 | { |
| 1509 | return mfc_read(dev, S5P_FIMV_SI_DECODE_Y_ADR) << MFC_OFFSET_SHIFT; |
| 1510 | } |
| 1511 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1512 | static int s5p_mfc_get_dspl_status_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1513 | { |
| 1514 | return mfc_read(dev, S5P_FIMV_SI_DISPLAY_STATUS); |
| 1515 | } |
| 1516 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1517 | static int s5p_mfc_get_dec_status_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1518 | { |
| 1519 | return mfc_read(dev, S5P_FIMV_SI_DECODE_STATUS); |
| 1520 | } |
| 1521 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1522 | static int s5p_mfc_get_dec_frame_type_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1523 | { |
| 1524 | return mfc_read(dev, S5P_FIMV_DECODE_FRAME_TYPE) & |
| 1525 | S5P_FIMV_DECODE_FRAME_MASK; |
| 1526 | } |
| 1527 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1528 | static int s5p_mfc_get_disp_frame_type_v5(struct s5p_mfc_ctx *ctx) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1529 | { |
Arun Kumar K | 8f532a7 | 2012-10-03 22:19:09 -0300 | [diff] [blame] | 1530 | return (s5p_mfc_read_info_v5(ctx, DISP_PIC_FRAME_TYPE) >> |
| 1531 | S5P_FIMV_SHARED_DISP_FRAME_TYPE_SHIFT) & |
| 1532 | S5P_FIMV_DECODE_FRAME_MASK; |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1533 | } |
| 1534 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1535 | static int s5p_mfc_get_consumed_stream_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1536 | { |
| 1537 | return mfc_read(dev, S5P_FIMV_SI_CONSUMED_BYTES); |
| 1538 | } |
| 1539 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1540 | static int s5p_mfc_get_int_reason_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1541 | { |
| 1542 | int reason; |
| 1543 | reason = mfc_read(dev, S5P_FIMV_RISC2HOST_CMD) & |
| 1544 | S5P_FIMV_RISC2HOST_CMD_MASK; |
| 1545 | switch (reason) { |
| 1546 | case S5P_FIMV_R2H_CMD_OPEN_INSTANCE_RET: |
| 1547 | reason = S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET; |
| 1548 | break; |
| 1549 | case S5P_FIMV_R2H_CMD_CLOSE_INSTANCE_RET: |
| 1550 | reason = S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET; |
| 1551 | break; |
| 1552 | case S5P_FIMV_R2H_CMD_SEQ_DONE_RET: |
| 1553 | reason = S5P_MFC_R2H_CMD_SEQ_DONE_RET; |
| 1554 | break; |
| 1555 | case S5P_FIMV_R2H_CMD_FRAME_DONE_RET: |
| 1556 | reason = S5P_MFC_R2H_CMD_FRAME_DONE_RET; |
| 1557 | break; |
| 1558 | case S5P_FIMV_R2H_CMD_SLICE_DONE_RET: |
| 1559 | reason = S5P_MFC_R2H_CMD_SLICE_DONE_RET; |
| 1560 | break; |
| 1561 | case S5P_FIMV_R2H_CMD_SYS_INIT_RET: |
| 1562 | reason = S5P_MFC_R2H_CMD_SYS_INIT_RET; |
| 1563 | break; |
| 1564 | case S5P_FIMV_R2H_CMD_FW_STATUS_RET: |
| 1565 | reason = S5P_MFC_R2H_CMD_FW_STATUS_RET; |
| 1566 | break; |
| 1567 | case S5P_FIMV_R2H_CMD_SLEEP_RET: |
| 1568 | reason = S5P_MFC_R2H_CMD_SLEEP_RET; |
| 1569 | break; |
| 1570 | case S5P_FIMV_R2H_CMD_WAKEUP_RET: |
| 1571 | reason = S5P_MFC_R2H_CMD_WAKEUP_RET; |
| 1572 | break; |
| 1573 | case S5P_FIMV_R2H_CMD_INIT_BUFFERS_RET: |
| 1574 | reason = S5P_MFC_R2H_CMD_INIT_BUFFERS_RET; |
| 1575 | break; |
| 1576 | case S5P_FIMV_R2H_CMD_ENC_COMPLETE_RET: |
| 1577 | reason = S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET; |
| 1578 | break; |
| 1579 | case S5P_FIMV_R2H_CMD_ERR_RET: |
| 1580 | reason = S5P_MFC_R2H_CMD_ERR_RET; |
| 1581 | break; |
| 1582 | default: |
| 1583 | reason = S5P_MFC_R2H_CMD_EMPTY; |
Joe Perches | 2028c71 | 2013-10-08 20:29:08 -0300 | [diff] [blame] | 1584 | } |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1585 | return reason; |
| 1586 | } |
| 1587 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1588 | static int s5p_mfc_get_int_err_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1589 | { |
| 1590 | return mfc_read(dev, S5P_FIMV_RISC2HOST_ARG2); |
| 1591 | } |
| 1592 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1593 | static int s5p_mfc_err_dec_v5(unsigned int err) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1594 | { |
| 1595 | return (err & S5P_FIMV_ERR_DEC_MASK) >> S5P_FIMV_ERR_DEC_SHIFT; |
| 1596 | } |
| 1597 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1598 | static int s5p_mfc_err_dspl_v5(unsigned int err) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1599 | { |
| 1600 | return (err & S5P_FIMV_ERR_DSPL_MASK) >> S5P_FIMV_ERR_DSPL_SHIFT; |
| 1601 | } |
| 1602 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1603 | static int s5p_mfc_get_img_width_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1604 | { |
| 1605 | return mfc_read(dev, S5P_FIMV_SI_HRESOL); |
| 1606 | } |
| 1607 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1608 | static int s5p_mfc_get_img_height_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1609 | { |
| 1610 | return mfc_read(dev, S5P_FIMV_SI_VRESOL); |
| 1611 | } |
| 1612 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1613 | static int s5p_mfc_get_dpb_count_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1614 | { |
| 1615 | return mfc_read(dev, S5P_FIMV_SI_BUF_NUMBER); |
| 1616 | } |
| 1617 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1618 | static int s5p_mfc_get_mv_count_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1619 | { |
| 1620 | /* NOP */ |
| 1621 | return -1; |
| 1622 | } |
| 1623 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1624 | static int s5p_mfc_get_inst_no_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1625 | { |
| 1626 | return mfc_read(dev, S5P_FIMV_RISC2HOST_ARG1); |
| 1627 | } |
| 1628 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1629 | static int s5p_mfc_get_enc_strm_size_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1630 | { |
| 1631 | return mfc_read(dev, S5P_FIMV_ENC_SI_STRM_SIZE); |
| 1632 | } |
| 1633 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1634 | static int s5p_mfc_get_enc_slice_type_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1635 | { |
| 1636 | return mfc_read(dev, S5P_FIMV_ENC_SI_SLICE_TYPE); |
| 1637 | } |
| 1638 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1639 | static int s5p_mfc_get_enc_dpb_count_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1640 | { |
| 1641 | return -1; |
| 1642 | } |
| 1643 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1644 | static int s5p_mfc_get_enc_pic_count_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1645 | { |
| 1646 | return mfc_read(dev, S5P_FIMV_ENC_SI_PIC_CNT); |
| 1647 | } |
| 1648 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1649 | static int s5p_mfc_get_sei_avail_status_v5(struct s5p_mfc_ctx *ctx) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1650 | { |
| 1651 | return s5p_mfc_read_info_v5(ctx, FRAME_PACK_SEI_AVAIL); |
| 1652 | } |
| 1653 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1654 | static int s5p_mfc_get_mvc_num_views_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1655 | { |
| 1656 | return -1; |
| 1657 | } |
| 1658 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1659 | static int s5p_mfc_get_mvc_view_id_v5(struct s5p_mfc_dev *dev) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1660 | { |
| 1661 | return -1; |
| 1662 | } |
| 1663 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1664 | static unsigned int s5p_mfc_get_pic_type_top_v5(struct s5p_mfc_ctx *ctx) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1665 | { |
| 1666 | return s5p_mfc_read_info_v5(ctx, PIC_TIME_TOP); |
| 1667 | } |
| 1668 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1669 | static unsigned int s5p_mfc_get_pic_type_bot_v5(struct s5p_mfc_ctx *ctx) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1670 | { |
| 1671 | return s5p_mfc_read_info_v5(ctx, PIC_TIME_BOT); |
| 1672 | } |
| 1673 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1674 | static unsigned int s5p_mfc_get_crop_info_h_v5(struct s5p_mfc_ctx *ctx) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1675 | { |
| 1676 | return s5p_mfc_read_info_v5(ctx, CROP_INFO_H); |
| 1677 | } |
| 1678 | |
Sachin Kamat | 3c75a2e | 2013-03-02 07:50:14 -0300 | [diff] [blame] | 1679 | static unsigned int s5p_mfc_get_crop_info_v_v5(struct s5p_mfc_ctx *ctx) |
Arun Kumar K | 43a1ea1 | 2012-10-03 22:19:08 -0300 | [diff] [blame] | 1680 | { |
| 1681 | return s5p_mfc_read_info_v5(ctx, CROP_INFO_V); |
| 1682 | } |
| 1683 | |
| 1684 | /* Initialize opr function pointers for MFC v5 */ |
| 1685 | static struct s5p_mfc_hw_ops s5p_mfc_ops_v5 = { |
| 1686 | .alloc_dec_temp_buffers = s5p_mfc_alloc_dec_temp_buffers_v5, |
| 1687 | .release_dec_desc_buffer = s5p_mfc_release_dec_desc_buffer_v5, |
| 1688 | .alloc_codec_buffers = s5p_mfc_alloc_codec_buffers_v5, |
| 1689 | .release_codec_buffers = s5p_mfc_release_codec_buffers_v5, |
| 1690 | .alloc_instance_buffer = s5p_mfc_alloc_instance_buffer_v5, |
| 1691 | .release_instance_buffer = s5p_mfc_release_instance_buffer_v5, |
| 1692 | .alloc_dev_context_buffer = s5p_mfc_alloc_dev_context_buffer_v5, |
| 1693 | .release_dev_context_buffer = s5p_mfc_release_dev_context_buffer_v5, |
| 1694 | .dec_calc_dpb_size = s5p_mfc_dec_calc_dpb_size_v5, |
| 1695 | .enc_calc_src_size = s5p_mfc_enc_calc_src_size_v5, |
| 1696 | .set_dec_stream_buffer = s5p_mfc_set_dec_stream_buffer_v5, |
| 1697 | .set_dec_frame_buffer = s5p_mfc_set_dec_frame_buffer_v5, |
| 1698 | .set_enc_stream_buffer = s5p_mfc_set_enc_stream_buffer_v5, |
| 1699 | .set_enc_frame_buffer = s5p_mfc_set_enc_frame_buffer_v5, |
| 1700 | .get_enc_frame_buffer = s5p_mfc_get_enc_frame_buffer_v5, |
| 1701 | .set_enc_ref_buffer = s5p_mfc_set_enc_ref_buffer_v5, |
| 1702 | .init_decode = s5p_mfc_init_decode_v5, |
| 1703 | .init_encode = s5p_mfc_init_encode_v5, |
| 1704 | .encode_one_frame = s5p_mfc_encode_one_frame_v5, |
| 1705 | .try_run = s5p_mfc_try_run_v5, |
| 1706 | .cleanup_queue = s5p_mfc_cleanup_queue_v5, |
| 1707 | .clear_int_flags = s5p_mfc_clear_int_flags_v5, |
| 1708 | .write_info = s5p_mfc_write_info_v5, |
| 1709 | .read_info = s5p_mfc_read_info_v5, |
| 1710 | .get_dspl_y_adr = s5p_mfc_get_dspl_y_adr_v5, |
| 1711 | .get_dec_y_adr = s5p_mfc_get_dec_y_adr_v5, |
| 1712 | .get_dspl_status = s5p_mfc_get_dspl_status_v5, |
| 1713 | .get_dec_status = s5p_mfc_get_dec_status_v5, |
| 1714 | .get_dec_frame_type = s5p_mfc_get_dec_frame_type_v5, |
| 1715 | .get_disp_frame_type = s5p_mfc_get_disp_frame_type_v5, |
| 1716 | .get_consumed_stream = s5p_mfc_get_consumed_stream_v5, |
| 1717 | .get_int_reason = s5p_mfc_get_int_reason_v5, |
| 1718 | .get_int_err = s5p_mfc_get_int_err_v5, |
| 1719 | .err_dec = s5p_mfc_err_dec_v5, |
| 1720 | .err_dspl = s5p_mfc_err_dspl_v5, |
| 1721 | .get_img_width = s5p_mfc_get_img_width_v5, |
| 1722 | .get_img_height = s5p_mfc_get_img_height_v5, |
| 1723 | .get_dpb_count = s5p_mfc_get_dpb_count_v5, |
| 1724 | .get_mv_count = s5p_mfc_get_mv_count_v5, |
| 1725 | .get_inst_no = s5p_mfc_get_inst_no_v5, |
| 1726 | .get_enc_strm_size = s5p_mfc_get_enc_strm_size_v5, |
| 1727 | .get_enc_slice_type = s5p_mfc_get_enc_slice_type_v5, |
| 1728 | .get_enc_dpb_count = s5p_mfc_get_enc_dpb_count_v5, |
| 1729 | .get_enc_pic_count = s5p_mfc_get_enc_pic_count_v5, |
| 1730 | .get_sei_avail_status = s5p_mfc_get_sei_avail_status_v5, |
| 1731 | .get_mvc_num_views = s5p_mfc_get_mvc_num_views_v5, |
| 1732 | .get_mvc_view_id = s5p_mfc_get_mvc_view_id_v5, |
| 1733 | .get_pic_type_top = s5p_mfc_get_pic_type_top_v5, |
| 1734 | .get_pic_type_bot = s5p_mfc_get_pic_type_bot_v5, |
| 1735 | .get_crop_info_h = s5p_mfc_get_crop_info_h_v5, |
| 1736 | .get_crop_info_v = s5p_mfc_get_crop_info_v_v5, |
| 1737 | }; |
| 1738 | |
| 1739 | struct s5p_mfc_hw_ops *s5p_mfc_init_hw_ops_v5(void) |
| 1740 | { |
| 1741 | return &s5p_mfc_ops_v5; |
| 1742 | } |