| Marc Gonzalez | cad008b | 2015-12-15 10:39:19 +0100 | [diff] [blame] | 1 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
| 2 | |
| 3 | / { |
| 4 | cpus { |
| 5 | #address-cells = <1>; |
| 6 | #size-cells = <0>; |
| 7 | enable-method = "sigma,tango4-smp"; |
| 8 | |
| 9 | cpu0: cpu@0 { |
| 10 | compatible = "arm,cortex-a9"; |
| 11 | next-level-cache = <&l2cc>; |
| 12 | device_type = "cpu"; |
| 13 | reg = <0>; |
| 14 | }; |
| 15 | |
| 16 | cpu1: cpu@1 { |
| 17 | compatible = "arm,cortex-a9"; |
| 18 | next-level-cache = <&l2cc>; |
| 19 | device_type = "cpu"; |
| 20 | reg = <1>; |
| 21 | }; |
| 22 | }; |
| 23 | |
| 24 | pmu { |
| 25 | compatible = "arm,cortex-a9-pmu"; |
| 26 | interrupt-affinity = <&cpu0>, <&cpu1>; |
| 27 | interrupts = |
| 28 | <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, |
| 29 | <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| 30 | }; |
| 31 | }; |