Lars-Peter Clausen | 61bfbdb | 2010-07-15 20:06:04 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> |
| 3 | * JZ4740 SD/MMC controller driver |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License as published by the |
| 7 | * Free Software Foundation; either version 2 of the License, or (at your |
| 8 | * option) any later version. |
| 9 | * |
| 10 | * You should have received a copy of the GNU General Public License along |
| 11 | * with this program; if not, write to the Free Software Foundation, Inc., |
| 12 | * 675 Mass Ave, Cambridge, MA 02139, USA. |
| 13 | * |
| 14 | */ |
| 15 | |
| 16 | #include <linux/mmc/host.h> |
Jamie Iles | 3119cbd | 2011-01-11 12:43:50 +0000 | [diff] [blame] | 17 | #include <linux/err.h> |
Lars-Peter Clausen | 61bfbdb | 2010-07-15 20:06:04 +0000 | [diff] [blame] | 18 | #include <linux/io.h> |
| 19 | #include <linux/irq.h> |
| 20 | #include <linux/interrupt.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/platform_device.h> |
| 23 | #include <linux/delay.h> |
| 24 | #include <linux/scatterlist.h> |
| 25 | #include <linux/clk.h> |
| 26 | |
| 27 | #include <linux/bitops.h> |
| 28 | #include <linux/gpio.h> |
| 29 | #include <asm/mach-jz4740/gpio.h> |
| 30 | #include <asm/cacheflush.h> |
| 31 | #include <linux/dma-mapping.h> |
| 32 | |
| 33 | #include <asm/mach-jz4740/jz4740_mmc.h> |
| 34 | |
| 35 | #define JZ_REG_MMC_STRPCL 0x00 |
| 36 | #define JZ_REG_MMC_STATUS 0x04 |
| 37 | #define JZ_REG_MMC_CLKRT 0x08 |
| 38 | #define JZ_REG_MMC_CMDAT 0x0C |
| 39 | #define JZ_REG_MMC_RESTO 0x10 |
| 40 | #define JZ_REG_MMC_RDTO 0x14 |
| 41 | #define JZ_REG_MMC_BLKLEN 0x18 |
| 42 | #define JZ_REG_MMC_NOB 0x1C |
| 43 | #define JZ_REG_MMC_SNOB 0x20 |
| 44 | #define JZ_REG_MMC_IMASK 0x24 |
| 45 | #define JZ_REG_MMC_IREG 0x28 |
| 46 | #define JZ_REG_MMC_CMD 0x2C |
| 47 | #define JZ_REG_MMC_ARG 0x30 |
| 48 | #define JZ_REG_MMC_RESP_FIFO 0x34 |
| 49 | #define JZ_REG_MMC_RXFIFO 0x38 |
| 50 | #define JZ_REG_MMC_TXFIFO 0x3C |
| 51 | |
| 52 | #define JZ_MMC_STRPCL_EXIT_MULTIPLE BIT(7) |
| 53 | #define JZ_MMC_STRPCL_EXIT_TRANSFER BIT(6) |
| 54 | #define JZ_MMC_STRPCL_START_READWAIT BIT(5) |
| 55 | #define JZ_MMC_STRPCL_STOP_READWAIT BIT(4) |
| 56 | #define JZ_MMC_STRPCL_RESET BIT(3) |
| 57 | #define JZ_MMC_STRPCL_START_OP BIT(2) |
| 58 | #define JZ_MMC_STRPCL_CLOCK_CONTROL (BIT(1) | BIT(0)) |
| 59 | #define JZ_MMC_STRPCL_CLOCK_STOP BIT(0) |
| 60 | #define JZ_MMC_STRPCL_CLOCK_START BIT(1) |
| 61 | |
| 62 | |
| 63 | #define JZ_MMC_STATUS_IS_RESETTING BIT(15) |
| 64 | #define JZ_MMC_STATUS_SDIO_INT_ACTIVE BIT(14) |
| 65 | #define JZ_MMC_STATUS_PRG_DONE BIT(13) |
| 66 | #define JZ_MMC_STATUS_DATA_TRAN_DONE BIT(12) |
| 67 | #define JZ_MMC_STATUS_END_CMD_RES BIT(11) |
| 68 | #define JZ_MMC_STATUS_DATA_FIFO_AFULL BIT(10) |
| 69 | #define JZ_MMC_STATUS_IS_READWAIT BIT(9) |
| 70 | #define JZ_MMC_STATUS_CLK_EN BIT(8) |
| 71 | #define JZ_MMC_STATUS_DATA_FIFO_FULL BIT(7) |
| 72 | #define JZ_MMC_STATUS_DATA_FIFO_EMPTY BIT(6) |
| 73 | #define JZ_MMC_STATUS_CRC_RES_ERR BIT(5) |
| 74 | #define JZ_MMC_STATUS_CRC_READ_ERROR BIT(4) |
| 75 | #define JZ_MMC_STATUS_TIMEOUT_WRITE BIT(3) |
| 76 | #define JZ_MMC_STATUS_CRC_WRITE_ERROR BIT(2) |
| 77 | #define JZ_MMC_STATUS_TIMEOUT_RES BIT(1) |
| 78 | #define JZ_MMC_STATUS_TIMEOUT_READ BIT(0) |
| 79 | |
| 80 | #define JZ_MMC_STATUS_READ_ERROR_MASK (BIT(4) | BIT(0)) |
| 81 | #define JZ_MMC_STATUS_WRITE_ERROR_MASK (BIT(3) | BIT(2)) |
| 82 | |
| 83 | |
| 84 | #define JZ_MMC_CMDAT_IO_ABORT BIT(11) |
| 85 | #define JZ_MMC_CMDAT_BUS_WIDTH_4BIT BIT(10) |
| 86 | #define JZ_MMC_CMDAT_DMA_EN BIT(8) |
| 87 | #define JZ_MMC_CMDAT_INIT BIT(7) |
| 88 | #define JZ_MMC_CMDAT_BUSY BIT(6) |
| 89 | #define JZ_MMC_CMDAT_STREAM BIT(5) |
| 90 | #define JZ_MMC_CMDAT_WRITE BIT(4) |
| 91 | #define JZ_MMC_CMDAT_DATA_EN BIT(3) |
| 92 | #define JZ_MMC_CMDAT_RESPONSE_FORMAT (BIT(2) | BIT(1) | BIT(0)) |
| 93 | #define JZ_MMC_CMDAT_RSP_R1 1 |
| 94 | #define JZ_MMC_CMDAT_RSP_R2 2 |
| 95 | #define JZ_MMC_CMDAT_RSP_R3 3 |
| 96 | |
| 97 | #define JZ_MMC_IRQ_SDIO BIT(7) |
| 98 | #define JZ_MMC_IRQ_TXFIFO_WR_REQ BIT(6) |
| 99 | #define JZ_MMC_IRQ_RXFIFO_RD_REQ BIT(5) |
| 100 | #define JZ_MMC_IRQ_END_CMD_RES BIT(2) |
| 101 | #define JZ_MMC_IRQ_PRG_DONE BIT(1) |
| 102 | #define JZ_MMC_IRQ_DATA_TRAN_DONE BIT(0) |
| 103 | |
| 104 | |
| 105 | #define JZ_MMC_CLK_RATE 24000000 |
| 106 | |
| 107 | enum jz4740_mmc_state { |
| 108 | JZ4740_MMC_STATE_READ_RESPONSE, |
| 109 | JZ4740_MMC_STATE_TRANSFER_DATA, |
| 110 | JZ4740_MMC_STATE_SEND_STOP, |
| 111 | JZ4740_MMC_STATE_DONE, |
| 112 | }; |
| 113 | |
| 114 | struct jz4740_mmc_host { |
| 115 | struct mmc_host *mmc; |
| 116 | struct platform_device *pdev; |
| 117 | struct jz4740_mmc_platform_data *pdata; |
| 118 | struct clk *clk; |
| 119 | |
| 120 | int irq; |
| 121 | int card_detect_irq; |
| 122 | |
| 123 | struct resource *mem; |
| 124 | void __iomem *base; |
| 125 | struct mmc_request *req; |
| 126 | struct mmc_command *cmd; |
| 127 | |
| 128 | unsigned long waiting; |
| 129 | |
| 130 | uint32_t cmdat; |
| 131 | |
| 132 | uint16_t irq_mask; |
| 133 | |
| 134 | spinlock_t lock; |
| 135 | |
| 136 | struct timer_list timeout_timer; |
| 137 | struct sg_mapping_iter miter; |
| 138 | enum jz4740_mmc_state state; |
| 139 | }; |
| 140 | |
| 141 | static void jz4740_mmc_set_irq_enabled(struct jz4740_mmc_host *host, |
| 142 | unsigned int irq, bool enabled) |
| 143 | { |
| 144 | unsigned long flags; |
| 145 | |
| 146 | spin_lock_irqsave(&host->lock, flags); |
| 147 | if (enabled) |
| 148 | host->irq_mask &= ~irq; |
| 149 | else |
| 150 | host->irq_mask |= irq; |
| 151 | spin_unlock_irqrestore(&host->lock, flags); |
| 152 | |
| 153 | writew(host->irq_mask, host->base + JZ_REG_MMC_IMASK); |
| 154 | } |
| 155 | |
| 156 | static void jz4740_mmc_clock_enable(struct jz4740_mmc_host *host, |
| 157 | bool start_transfer) |
| 158 | { |
| 159 | uint16_t val = JZ_MMC_STRPCL_CLOCK_START; |
| 160 | |
| 161 | if (start_transfer) |
| 162 | val |= JZ_MMC_STRPCL_START_OP; |
| 163 | |
| 164 | writew(val, host->base + JZ_REG_MMC_STRPCL); |
| 165 | } |
| 166 | |
| 167 | static void jz4740_mmc_clock_disable(struct jz4740_mmc_host *host) |
| 168 | { |
| 169 | uint32_t status; |
| 170 | unsigned int timeout = 1000; |
| 171 | |
| 172 | writew(JZ_MMC_STRPCL_CLOCK_STOP, host->base + JZ_REG_MMC_STRPCL); |
| 173 | do { |
| 174 | status = readl(host->base + JZ_REG_MMC_STATUS); |
| 175 | } while (status & JZ_MMC_STATUS_CLK_EN && --timeout); |
| 176 | } |
| 177 | |
| 178 | static void jz4740_mmc_reset(struct jz4740_mmc_host *host) |
| 179 | { |
| 180 | uint32_t status; |
| 181 | unsigned int timeout = 1000; |
| 182 | |
| 183 | writew(JZ_MMC_STRPCL_RESET, host->base + JZ_REG_MMC_STRPCL); |
| 184 | udelay(10); |
| 185 | do { |
| 186 | status = readl(host->base + JZ_REG_MMC_STATUS); |
| 187 | } while (status & JZ_MMC_STATUS_IS_RESETTING && --timeout); |
| 188 | } |
| 189 | |
| 190 | static void jz4740_mmc_request_done(struct jz4740_mmc_host *host) |
| 191 | { |
| 192 | struct mmc_request *req; |
| 193 | |
| 194 | req = host->req; |
| 195 | host->req = NULL; |
| 196 | |
| 197 | mmc_request_done(host->mmc, req); |
| 198 | } |
| 199 | |
| 200 | static unsigned int jz4740_mmc_poll_irq(struct jz4740_mmc_host *host, |
| 201 | unsigned int irq) |
| 202 | { |
| 203 | unsigned int timeout = 0x800; |
| 204 | uint16_t status; |
| 205 | |
| 206 | do { |
| 207 | status = readw(host->base + JZ_REG_MMC_IREG); |
| 208 | } while (!(status & irq) && --timeout); |
| 209 | |
| 210 | if (timeout == 0) { |
| 211 | set_bit(0, &host->waiting); |
| 212 | mod_timer(&host->timeout_timer, jiffies + 5*HZ); |
| 213 | jz4740_mmc_set_irq_enabled(host, irq, true); |
| 214 | return true; |
| 215 | } |
| 216 | |
| 217 | return false; |
| 218 | } |
| 219 | |
| 220 | static void jz4740_mmc_transfer_check_state(struct jz4740_mmc_host *host, |
| 221 | struct mmc_data *data) |
| 222 | { |
| 223 | int status; |
| 224 | |
| 225 | status = readl(host->base + JZ_REG_MMC_STATUS); |
| 226 | if (status & JZ_MMC_STATUS_WRITE_ERROR_MASK) { |
| 227 | if (status & (JZ_MMC_STATUS_TIMEOUT_WRITE)) { |
| 228 | host->req->cmd->error = -ETIMEDOUT; |
| 229 | data->error = -ETIMEDOUT; |
| 230 | } else { |
| 231 | host->req->cmd->error = -EIO; |
| 232 | data->error = -EIO; |
| 233 | } |
| 234 | } |
| 235 | } |
| 236 | |
| 237 | static bool jz4740_mmc_write_data(struct jz4740_mmc_host *host, |
| 238 | struct mmc_data *data) |
| 239 | { |
| 240 | struct sg_mapping_iter *miter = &host->miter; |
| 241 | void __iomem *fifo_addr = host->base + JZ_REG_MMC_TXFIFO; |
| 242 | uint32_t *buf; |
| 243 | bool timeout; |
| 244 | size_t i, j; |
| 245 | |
| 246 | while (sg_miter_next(miter)) { |
| 247 | buf = miter->addr; |
| 248 | i = miter->length / 4; |
| 249 | j = i / 8; |
| 250 | i = i & 0x7; |
| 251 | while (j) { |
| 252 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); |
| 253 | if (unlikely(timeout)) |
| 254 | goto poll_timeout; |
| 255 | |
| 256 | writel(buf[0], fifo_addr); |
| 257 | writel(buf[1], fifo_addr); |
| 258 | writel(buf[2], fifo_addr); |
| 259 | writel(buf[3], fifo_addr); |
| 260 | writel(buf[4], fifo_addr); |
| 261 | writel(buf[5], fifo_addr); |
| 262 | writel(buf[6], fifo_addr); |
| 263 | writel(buf[7], fifo_addr); |
| 264 | buf += 8; |
| 265 | --j; |
| 266 | } |
| 267 | if (unlikely(i)) { |
| 268 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_TXFIFO_WR_REQ); |
| 269 | if (unlikely(timeout)) |
| 270 | goto poll_timeout; |
| 271 | |
| 272 | while (i) { |
| 273 | writel(*buf, fifo_addr); |
| 274 | ++buf; |
| 275 | --i; |
| 276 | } |
| 277 | } |
| 278 | data->bytes_xfered += miter->length; |
| 279 | } |
| 280 | sg_miter_stop(miter); |
| 281 | |
| 282 | return false; |
| 283 | |
| 284 | poll_timeout: |
| 285 | miter->consumed = (void *)buf - miter->addr; |
| 286 | data->bytes_xfered += miter->consumed; |
| 287 | sg_miter_stop(miter); |
| 288 | |
| 289 | return true; |
| 290 | } |
| 291 | |
| 292 | static bool jz4740_mmc_read_data(struct jz4740_mmc_host *host, |
| 293 | struct mmc_data *data) |
| 294 | { |
| 295 | struct sg_mapping_iter *miter = &host->miter; |
| 296 | void __iomem *fifo_addr = host->base + JZ_REG_MMC_RXFIFO; |
| 297 | uint32_t *buf; |
| 298 | uint32_t d; |
| 299 | uint16_t status; |
| 300 | size_t i, j; |
| 301 | unsigned int timeout; |
| 302 | |
| 303 | while (sg_miter_next(miter)) { |
| 304 | buf = miter->addr; |
| 305 | i = miter->length; |
| 306 | j = i / 32; |
| 307 | i = i & 0x1f; |
| 308 | while (j) { |
| 309 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); |
| 310 | if (unlikely(timeout)) |
| 311 | goto poll_timeout; |
| 312 | |
| 313 | buf[0] = readl(fifo_addr); |
| 314 | buf[1] = readl(fifo_addr); |
| 315 | buf[2] = readl(fifo_addr); |
| 316 | buf[3] = readl(fifo_addr); |
| 317 | buf[4] = readl(fifo_addr); |
| 318 | buf[5] = readl(fifo_addr); |
| 319 | buf[6] = readl(fifo_addr); |
| 320 | buf[7] = readl(fifo_addr); |
| 321 | |
| 322 | buf += 8; |
| 323 | --j; |
| 324 | } |
| 325 | |
| 326 | if (unlikely(i)) { |
| 327 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_RXFIFO_RD_REQ); |
| 328 | if (unlikely(timeout)) |
| 329 | goto poll_timeout; |
| 330 | |
| 331 | while (i >= 4) { |
| 332 | *buf++ = readl(fifo_addr); |
| 333 | i -= 4; |
| 334 | } |
| 335 | if (unlikely(i > 0)) { |
| 336 | d = readl(fifo_addr); |
| 337 | memcpy(buf, &d, i); |
| 338 | } |
| 339 | } |
| 340 | data->bytes_xfered += miter->length; |
| 341 | |
| 342 | /* This can go away once MIPS implements |
| 343 | * flush_kernel_dcache_page */ |
| 344 | flush_dcache_page(miter->page); |
| 345 | } |
| 346 | sg_miter_stop(miter); |
| 347 | |
| 348 | /* For whatever reason there is sometime one word more in the fifo then |
| 349 | * requested */ |
| 350 | timeout = 1000; |
| 351 | status = readl(host->base + JZ_REG_MMC_STATUS); |
| 352 | while (!(status & JZ_MMC_STATUS_DATA_FIFO_EMPTY) && --timeout) { |
| 353 | d = readl(fifo_addr); |
| 354 | status = readl(host->base + JZ_REG_MMC_STATUS); |
| 355 | } |
| 356 | |
| 357 | return false; |
| 358 | |
| 359 | poll_timeout: |
| 360 | miter->consumed = (void *)buf - miter->addr; |
| 361 | data->bytes_xfered += miter->consumed; |
| 362 | sg_miter_stop(miter); |
| 363 | |
| 364 | return true; |
| 365 | } |
| 366 | |
| 367 | static void jz4740_mmc_timeout(unsigned long data) |
| 368 | { |
| 369 | struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)data; |
| 370 | |
| 371 | if (!test_and_clear_bit(0, &host->waiting)) |
| 372 | return; |
| 373 | |
| 374 | jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, false); |
| 375 | |
| 376 | host->req->cmd->error = -ETIMEDOUT; |
| 377 | jz4740_mmc_request_done(host); |
| 378 | } |
| 379 | |
| 380 | static void jz4740_mmc_read_response(struct jz4740_mmc_host *host, |
| 381 | struct mmc_command *cmd) |
| 382 | { |
| 383 | int i; |
| 384 | uint16_t tmp; |
| 385 | void __iomem *fifo_addr = host->base + JZ_REG_MMC_RESP_FIFO; |
| 386 | |
| 387 | if (cmd->flags & MMC_RSP_136) { |
| 388 | tmp = readw(fifo_addr); |
| 389 | for (i = 0; i < 4; ++i) { |
| 390 | cmd->resp[i] = tmp << 24; |
| 391 | tmp = readw(fifo_addr); |
| 392 | cmd->resp[i] |= tmp << 8; |
| 393 | tmp = readw(fifo_addr); |
| 394 | cmd->resp[i] |= tmp >> 8; |
| 395 | } |
| 396 | } else { |
| 397 | cmd->resp[0] = readw(fifo_addr) << 24; |
| 398 | cmd->resp[0] |= readw(fifo_addr) << 8; |
| 399 | cmd->resp[0] |= readw(fifo_addr) & 0xff; |
| 400 | } |
| 401 | } |
| 402 | |
| 403 | static void jz4740_mmc_send_command(struct jz4740_mmc_host *host, |
| 404 | struct mmc_command *cmd) |
| 405 | { |
| 406 | uint32_t cmdat = host->cmdat; |
| 407 | |
| 408 | host->cmdat &= ~JZ_MMC_CMDAT_INIT; |
| 409 | jz4740_mmc_clock_disable(host); |
| 410 | |
| 411 | host->cmd = cmd; |
| 412 | |
| 413 | if (cmd->flags & MMC_RSP_BUSY) |
| 414 | cmdat |= JZ_MMC_CMDAT_BUSY; |
| 415 | |
| 416 | switch (mmc_resp_type(cmd)) { |
| 417 | case MMC_RSP_R1B: |
| 418 | case MMC_RSP_R1: |
| 419 | cmdat |= JZ_MMC_CMDAT_RSP_R1; |
| 420 | break; |
| 421 | case MMC_RSP_R2: |
| 422 | cmdat |= JZ_MMC_CMDAT_RSP_R2; |
| 423 | break; |
| 424 | case MMC_RSP_R3: |
| 425 | cmdat |= JZ_MMC_CMDAT_RSP_R3; |
| 426 | break; |
| 427 | default: |
| 428 | break; |
| 429 | } |
| 430 | |
| 431 | if (cmd->data) { |
| 432 | cmdat |= JZ_MMC_CMDAT_DATA_EN; |
| 433 | if (cmd->data->flags & MMC_DATA_WRITE) |
| 434 | cmdat |= JZ_MMC_CMDAT_WRITE; |
| 435 | if (cmd->data->flags & MMC_DATA_STREAM) |
| 436 | cmdat |= JZ_MMC_CMDAT_STREAM; |
| 437 | |
| 438 | writew(cmd->data->blksz, host->base + JZ_REG_MMC_BLKLEN); |
| 439 | writew(cmd->data->blocks, host->base + JZ_REG_MMC_NOB); |
| 440 | } |
| 441 | |
| 442 | writeb(cmd->opcode, host->base + JZ_REG_MMC_CMD); |
| 443 | writel(cmd->arg, host->base + JZ_REG_MMC_ARG); |
| 444 | writel(cmdat, host->base + JZ_REG_MMC_CMDAT); |
| 445 | |
| 446 | jz4740_mmc_clock_enable(host, 1); |
| 447 | } |
| 448 | |
| 449 | static void jz_mmc_prepare_data_transfer(struct jz4740_mmc_host *host) |
| 450 | { |
| 451 | struct mmc_command *cmd = host->req->cmd; |
| 452 | struct mmc_data *data = cmd->data; |
| 453 | int direction; |
| 454 | |
| 455 | if (data->flags & MMC_DATA_READ) |
| 456 | direction = SG_MITER_TO_SG; |
| 457 | else |
| 458 | direction = SG_MITER_FROM_SG; |
| 459 | |
| 460 | sg_miter_start(&host->miter, data->sg, data->sg_len, direction); |
| 461 | } |
| 462 | |
| 463 | |
| 464 | static irqreturn_t jz_mmc_irq_worker(int irq, void *devid) |
| 465 | { |
| 466 | struct jz4740_mmc_host *host = (struct jz4740_mmc_host *)devid; |
| 467 | struct mmc_command *cmd = host->req->cmd; |
| 468 | struct mmc_request *req = host->req; |
| 469 | bool timeout = false; |
| 470 | |
| 471 | if (cmd->error) |
| 472 | host->state = JZ4740_MMC_STATE_DONE; |
| 473 | |
| 474 | switch (host->state) { |
| 475 | case JZ4740_MMC_STATE_READ_RESPONSE: |
| 476 | if (cmd->flags & MMC_RSP_PRESENT) |
| 477 | jz4740_mmc_read_response(host, cmd); |
| 478 | |
| 479 | if (!cmd->data) |
| 480 | break; |
| 481 | |
| 482 | jz_mmc_prepare_data_transfer(host); |
| 483 | |
| 484 | case JZ4740_MMC_STATE_TRANSFER_DATA: |
| 485 | if (cmd->data->flags & MMC_DATA_READ) |
| 486 | timeout = jz4740_mmc_read_data(host, cmd->data); |
| 487 | else |
| 488 | timeout = jz4740_mmc_write_data(host, cmd->data); |
| 489 | |
| 490 | if (unlikely(timeout)) { |
| 491 | host->state = JZ4740_MMC_STATE_TRANSFER_DATA; |
| 492 | break; |
| 493 | } |
| 494 | |
| 495 | jz4740_mmc_transfer_check_state(host, cmd->data); |
| 496 | |
| 497 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_DATA_TRAN_DONE); |
| 498 | if (unlikely(timeout)) { |
| 499 | host->state = JZ4740_MMC_STATE_SEND_STOP; |
| 500 | break; |
| 501 | } |
| 502 | writew(JZ_MMC_IRQ_DATA_TRAN_DONE, host->base + JZ_REG_MMC_IREG); |
| 503 | |
| 504 | case JZ4740_MMC_STATE_SEND_STOP: |
| 505 | if (!req->stop) |
| 506 | break; |
| 507 | |
| 508 | jz4740_mmc_send_command(host, req->stop); |
| 509 | |
| 510 | timeout = jz4740_mmc_poll_irq(host, JZ_MMC_IRQ_PRG_DONE); |
| 511 | if (timeout) { |
| 512 | host->state = JZ4740_MMC_STATE_DONE; |
| 513 | break; |
| 514 | } |
| 515 | case JZ4740_MMC_STATE_DONE: |
| 516 | break; |
| 517 | } |
| 518 | |
| 519 | if (!timeout) |
| 520 | jz4740_mmc_request_done(host); |
| 521 | |
| 522 | return IRQ_HANDLED; |
| 523 | } |
| 524 | |
| 525 | static irqreturn_t jz_mmc_irq(int irq, void *devid) |
| 526 | { |
| 527 | struct jz4740_mmc_host *host = devid; |
| 528 | struct mmc_command *cmd = host->cmd; |
| 529 | uint16_t irq_reg, status, tmp; |
| 530 | |
| 531 | irq_reg = readw(host->base + JZ_REG_MMC_IREG); |
| 532 | |
| 533 | tmp = irq_reg; |
| 534 | irq_reg &= ~host->irq_mask; |
| 535 | |
| 536 | tmp &= ~(JZ_MMC_IRQ_TXFIFO_WR_REQ | JZ_MMC_IRQ_RXFIFO_RD_REQ | |
| 537 | JZ_MMC_IRQ_PRG_DONE | JZ_MMC_IRQ_DATA_TRAN_DONE); |
| 538 | |
| 539 | if (tmp != irq_reg) |
| 540 | writew(tmp & ~irq_reg, host->base + JZ_REG_MMC_IREG); |
| 541 | |
| 542 | if (irq_reg & JZ_MMC_IRQ_SDIO) { |
| 543 | writew(JZ_MMC_IRQ_SDIO, host->base + JZ_REG_MMC_IREG); |
| 544 | mmc_signal_sdio_irq(host->mmc); |
| 545 | irq_reg &= ~JZ_MMC_IRQ_SDIO; |
| 546 | } |
| 547 | |
| 548 | if (host->req && cmd && irq_reg) { |
| 549 | if (test_and_clear_bit(0, &host->waiting)) { |
| 550 | del_timer(&host->timeout_timer); |
| 551 | |
| 552 | status = readl(host->base + JZ_REG_MMC_STATUS); |
| 553 | |
| 554 | if (status & JZ_MMC_STATUS_TIMEOUT_RES) { |
| 555 | cmd->error = -ETIMEDOUT; |
| 556 | } else if (status & JZ_MMC_STATUS_CRC_RES_ERR) { |
| 557 | cmd->error = -EIO; |
| 558 | } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR | |
| 559 | JZ_MMC_STATUS_CRC_WRITE_ERROR)) { |
| 560 | if (cmd->data) |
| 561 | cmd->data->error = -EIO; |
| 562 | cmd->error = -EIO; |
| 563 | } else if (status & (JZ_MMC_STATUS_CRC_READ_ERROR | |
| 564 | JZ_MMC_STATUS_CRC_WRITE_ERROR)) { |
| 565 | if (cmd->data) |
| 566 | cmd->data->error = -EIO; |
| 567 | cmd->error = -EIO; |
| 568 | } |
| 569 | |
| 570 | jz4740_mmc_set_irq_enabled(host, irq_reg, false); |
| 571 | writew(irq_reg, host->base + JZ_REG_MMC_IREG); |
| 572 | |
| 573 | return IRQ_WAKE_THREAD; |
| 574 | } |
| 575 | } |
| 576 | |
| 577 | return IRQ_HANDLED; |
| 578 | } |
| 579 | |
| 580 | static int jz4740_mmc_set_clock_rate(struct jz4740_mmc_host *host, int rate) |
| 581 | { |
| 582 | int div = 0; |
| 583 | int real_rate; |
| 584 | |
| 585 | jz4740_mmc_clock_disable(host); |
| 586 | clk_set_rate(host->clk, JZ_MMC_CLK_RATE); |
| 587 | |
| 588 | real_rate = clk_get_rate(host->clk); |
| 589 | |
| 590 | while (real_rate > rate && div < 7) { |
| 591 | ++div; |
| 592 | real_rate >>= 1; |
| 593 | } |
| 594 | |
| 595 | writew(div, host->base + JZ_REG_MMC_CLKRT); |
| 596 | return real_rate; |
| 597 | } |
| 598 | |
| 599 | static void jz4740_mmc_request(struct mmc_host *mmc, struct mmc_request *req) |
| 600 | { |
| 601 | struct jz4740_mmc_host *host = mmc_priv(mmc); |
| 602 | |
| 603 | host->req = req; |
| 604 | |
| 605 | writew(0xffff, host->base + JZ_REG_MMC_IREG); |
| 606 | |
| 607 | writew(JZ_MMC_IRQ_END_CMD_RES, host->base + JZ_REG_MMC_IREG); |
| 608 | jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_END_CMD_RES, true); |
| 609 | |
| 610 | host->state = JZ4740_MMC_STATE_READ_RESPONSE; |
| 611 | set_bit(0, &host->waiting); |
| 612 | mod_timer(&host->timeout_timer, jiffies + 5*HZ); |
| 613 | jz4740_mmc_send_command(host, req->cmd); |
| 614 | } |
| 615 | |
| 616 | static void jz4740_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
| 617 | { |
| 618 | struct jz4740_mmc_host *host = mmc_priv(mmc); |
| 619 | if (ios->clock) |
| 620 | jz4740_mmc_set_clock_rate(host, ios->clock); |
| 621 | |
| 622 | switch (ios->power_mode) { |
| 623 | case MMC_POWER_UP: |
| 624 | jz4740_mmc_reset(host); |
| 625 | if (gpio_is_valid(host->pdata->gpio_power)) |
| 626 | gpio_set_value(host->pdata->gpio_power, |
| 627 | !host->pdata->power_active_low); |
| 628 | host->cmdat |= JZ_MMC_CMDAT_INIT; |
| 629 | clk_enable(host->clk); |
| 630 | break; |
| 631 | case MMC_POWER_ON: |
| 632 | break; |
| 633 | default: |
| 634 | if (gpio_is_valid(host->pdata->gpio_power)) |
| 635 | gpio_set_value(host->pdata->gpio_power, |
| 636 | host->pdata->power_active_low); |
| 637 | clk_disable(host->clk); |
| 638 | break; |
| 639 | } |
| 640 | |
| 641 | switch (ios->bus_width) { |
| 642 | case MMC_BUS_WIDTH_1: |
| 643 | host->cmdat &= ~JZ_MMC_CMDAT_BUS_WIDTH_4BIT; |
| 644 | break; |
| 645 | case MMC_BUS_WIDTH_4: |
| 646 | host->cmdat |= JZ_MMC_CMDAT_BUS_WIDTH_4BIT; |
| 647 | break; |
| 648 | default: |
| 649 | break; |
| 650 | } |
| 651 | } |
| 652 | |
| 653 | static int jz4740_mmc_get_ro(struct mmc_host *mmc) |
| 654 | { |
| 655 | struct jz4740_mmc_host *host = mmc_priv(mmc); |
| 656 | if (!gpio_is_valid(host->pdata->gpio_read_only)) |
| 657 | return -ENOSYS; |
| 658 | |
| 659 | return gpio_get_value(host->pdata->gpio_read_only) ^ |
| 660 | host->pdata->read_only_active_low; |
| 661 | } |
| 662 | |
| 663 | static int jz4740_mmc_get_cd(struct mmc_host *mmc) |
| 664 | { |
| 665 | struct jz4740_mmc_host *host = mmc_priv(mmc); |
| 666 | if (!gpio_is_valid(host->pdata->gpio_card_detect)) |
| 667 | return -ENOSYS; |
| 668 | |
| 669 | return gpio_get_value(host->pdata->gpio_card_detect) ^ |
| 670 | host->pdata->card_detect_active_low; |
| 671 | } |
| 672 | |
| 673 | static irqreturn_t jz4740_mmc_card_detect_irq(int irq, void *devid) |
| 674 | { |
| 675 | struct jz4740_mmc_host *host = devid; |
| 676 | |
| 677 | mmc_detect_change(host->mmc, HZ / 2); |
| 678 | |
| 679 | return IRQ_HANDLED; |
| 680 | } |
| 681 | |
| 682 | static void jz4740_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) |
| 683 | { |
| 684 | struct jz4740_mmc_host *host = mmc_priv(mmc); |
| 685 | jz4740_mmc_set_irq_enabled(host, JZ_MMC_IRQ_SDIO, enable); |
| 686 | } |
| 687 | |
| 688 | static const struct mmc_host_ops jz4740_mmc_ops = { |
| 689 | .request = jz4740_mmc_request, |
| 690 | .set_ios = jz4740_mmc_set_ios, |
| 691 | .get_ro = jz4740_mmc_get_ro, |
| 692 | .get_cd = jz4740_mmc_get_cd, |
| 693 | .enable_sdio_irq = jz4740_mmc_enable_sdio_irq, |
| 694 | }; |
| 695 | |
| 696 | static const struct jz_gpio_bulk_request jz4740_mmc_pins[] = { |
| 697 | JZ_GPIO_BULK_PIN(MSC_CMD), |
| 698 | JZ_GPIO_BULK_PIN(MSC_CLK), |
| 699 | JZ_GPIO_BULK_PIN(MSC_DATA0), |
| 700 | JZ_GPIO_BULK_PIN(MSC_DATA1), |
| 701 | JZ_GPIO_BULK_PIN(MSC_DATA2), |
| 702 | JZ_GPIO_BULK_PIN(MSC_DATA3), |
| 703 | }; |
| 704 | |
| 705 | static int __devinit jz4740_mmc_request_gpio(struct device *dev, int gpio, |
| 706 | const char *name, bool output, int value) |
| 707 | { |
| 708 | int ret; |
| 709 | |
| 710 | if (!gpio_is_valid(gpio)) |
| 711 | return 0; |
| 712 | |
| 713 | ret = gpio_request(gpio, name); |
| 714 | if (ret) { |
| 715 | dev_err(dev, "Failed to request %s gpio: %d\n", name, ret); |
| 716 | return ret; |
| 717 | } |
| 718 | |
| 719 | if (output) |
| 720 | gpio_direction_output(gpio, value); |
| 721 | else |
| 722 | gpio_direction_input(gpio); |
| 723 | |
| 724 | return 0; |
| 725 | } |
| 726 | |
| 727 | static int __devinit jz4740_mmc_request_gpios(struct platform_device *pdev) |
| 728 | { |
| 729 | int ret; |
| 730 | struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; |
| 731 | |
| 732 | if (!pdata) |
| 733 | return 0; |
| 734 | |
| 735 | ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_card_detect, |
| 736 | "MMC detect change", false, 0); |
| 737 | if (ret) |
| 738 | goto err; |
| 739 | |
| 740 | ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_read_only, |
| 741 | "MMC read only", false, 0); |
| 742 | if (ret) |
| 743 | goto err_free_gpio_card_detect; |
| 744 | |
| 745 | ret = jz4740_mmc_request_gpio(&pdev->dev, pdata->gpio_power, |
| 746 | "MMC read only", true, pdata->power_active_low); |
| 747 | if (ret) |
| 748 | goto err_free_gpio_read_only; |
| 749 | |
| 750 | return 0; |
| 751 | |
| 752 | err_free_gpio_read_only: |
| 753 | if (gpio_is_valid(pdata->gpio_read_only)) |
| 754 | gpio_free(pdata->gpio_read_only); |
| 755 | err_free_gpio_card_detect: |
| 756 | if (gpio_is_valid(pdata->gpio_card_detect)) |
| 757 | gpio_free(pdata->gpio_card_detect); |
| 758 | err: |
| 759 | return ret; |
| 760 | } |
| 761 | |
| 762 | static int __devinit jz4740_mmc_request_cd_irq(struct platform_device *pdev, |
| 763 | struct jz4740_mmc_host *host) |
| 764 | { |
| 765 | struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; |
| 766 | |
| 767 | if (!gpio_is_valid(pdata->gpio_card_detect)) |
| 768 | return 0; |
| 769 | |
| 770 | host->card_detect_irq = gpio_to_irq(pdata->gpio_card_detect); |
| 771 | if (host->card_detect_irq < 0) { |
| 772 | dev_warn(&pdev->dev, "Failed to get card detect irq\n"); |
| 773 | return 0; |
| 774 | } |
| 775 | |
| 776 | return request_irq(host->card_detect_irq, jz4740_mmc_card_detect_irq, |
| 777 | IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING, |
| 778 | "MMC card detect", host); |
| 779 | } |
| 780 | |
| 781 | static void jz4740_mmc_free_gpios(struct platform_device *pdev) |
| 782 | { |
| 783 | struct jz4740_mmc_platform_data *pdata = pdev->dev.platform_data; |
| 784 | |
| 785 | if (!pdata) |
| 786 | return; |
| 787 | |
| 788 | if (gpio_is_valid(pdata->gpio_power)) |
| 789 | gpio_free(pdata->gpio_power); |
| 790 | if (gpio_is_valid(pdata->gpio_read_only)) |
| 791 | gpio_free(pdata->gpio_read_only); |
| 792 | if (gpio_is_valid(pdata->gpio_card_detect)) |
| 793 | gpio_free(pdata->gpio_card_detect); |
| 794 | } |
| 795 | |
| 796 | static inline size_t jz4740_mmc_num_pins(struct jz4740_mmc_host *host) |
| 797 | { |
| 798 | size_t num_pins = ARRAY_SIZE(jz4740_mmc_pins); |
| 799 | if (host->pdata && host->pdata->data_1bit) |
| 800 | num_pins -= 3; |
| 801 | |
| 802 | return num_pins; |
| 803 | } |
| 804 | |
| 805 | static int __devinit jz4740_mmc_probe(struct platform_device* pdev) |
| 806 | { |
| 807 | int ret; |
| 808 | struct mmc_host *mmc; |
| 809 | struct jz4740_mmc_host *host; |
| 810 | struct jz4740_mmc_platform_data *pdata; |
| 811 | |
| 812 | pdata = pdev->dev.platform_data; |
| 813 | |
| 814 | mmc = mmc_alloc_host(sizeof(struct jz4740_mmc_host), &pdev->dev); |
| 815 | if (!mmc) { |
| 816 | dev_err(&pdev->dev, "Failed to alloc mmc host structure\n"); |
| 817 | return -ENOMEM; |
| 818 | } |
| 819 | |
| 820 | host = mmc_priv(mmc); |
| 821 | host->pdata = pdata; |
| 822 | |
| 823 | host->irq = platform_get_irq(pdev, 0); |
| 824 | if (host->irq < 0) { |
| 825 | ret = host->irq; |
| 826 | dev_err(&pdev->dev, "Failed to get platform irq: %d\n", ret); |
| 827 | goto err_free_host; |
| 828 | } |
| 829 | |
| 830 | host->clk = clk_get(&pdev->dev, "mmc"); |
Jamie Iles | 3119cbd | 2011-01-11 12:43:50 +0000 | [diff] [blame] | 831 | if (IS_ERR(host->clk)) { |
| 832 | ret = PTR_ERR(host->clk); |
Lars-Peter Clausen | 61bfbdb | 2010-07-15 20:06:04 +0000 | [diff] [blame] | 833 | dev_err(&pdev->dev, "Failed to get mmc clock\n"); |
| 834 | goto err_free_host; |
| 835 | } |
| 836 | |
| 837 | host->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
| 838 | if (!host->mem) { |
| 839 | ret = -ENOENT; |
| 840 | dev_err(&pdev->dev, "Failed to get base platform memory\n"); |
| 841 | goto err_clk_put; |
| 842 | } |
| 843 | |
| 844 | host->mem = request_mem_region(host->mem->start, |
| 845 | resource_size(host->mem), pdev->name); |
| 846 | if (!host->mem) { |
| 847 | ret = -EBUSY; |
| 848 | dev_err(&pdev->dev, "Failed to request base memory region\n"); |
| 849 | goto err_clk_put; |
| 850 | } |
| 851 | |
| 852 | host->base = ioremap_nocache(host->mem->start, resource_size(host->mem)); |
| 853 | if (!host->base) { |
| 854 | ret = -EBUSY; |
| 855 | dev_err(&pdev->dev, "Failed to ioremap base memory\n"); |
| 856 | goto err_release_mem_region; |
| 857 | } |
| 858 | |
| 859 | ret = jz_gpio_bulk_request(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); |
| 860 | if (ret) { |
| 861 | dev_err(&pdev->dev, "Failed to request mmc pins: %d\n", ret); |
| 862 | goto err_iounmap; |
| 863 | } |
| 864 | |
| 865 | ret = jz4740_mmc_request_gpios(pdev); |
| 866 | if (ret) |
| 867 | goto err_gpio_bulk_free; |
| 868 | |
| 869 | mmc->ops = &jz4740_mmc_ops; |
| 870 | mmc->f_min = JZ_MMC_CLK_RATE / 128; |
| 871 | mmc->f_max = JZ_MMC_CLK_RATE; |
| 872 | mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; |
| 873 | mmc->caps = (pdata && pdata->data_1bit) ? 0 : MMC_CAP_4_BIT_DATA; |
| 874 | mmc->caps |= MMC_CAP_SDIO_IRQ; |
| 875 | |
| 876 | mmc->max_blk_size = (1 << 10) - 1; |
| 877 | mmc->max_blk_count = (1 << 15) - 1; |
| 878 | mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count; |
| 879 | |
Martin K. Petersen | a36274e | 2010-09-10 01:33:59 -0400 | [diff] [blame] | 880 | mmc->max_segs = 128; |
Lars-Peter Clausen | 61bfbdb | 2010-07-15 20:06:04 +0000 | [diff] [blame] | 881 | mmc->max_seg_size = mmc->max_req_size; |
| 882 | |
| 883 | host->mmc = mmc; |
| 884 | host->pdev = pdev; |
| 885 | spin_lock_init(&host->lock); |
| 886 | host->irq_mask = 0xffff; |
| 887 | |
| 888 | ret = jz4740_mmc_request_cd_irq(pdev, host); |
| 889 | if (ret) { |
| 890 | dev_err(&pdev->dev, "Failed to request card detect irq\n"); |
| 891 | goto err_free_gpios; |
| 892 | } |
| 893 | |
| 894 | ret = request_threaded_irq(host->irq, jz_mmc_irq, jz_mmc_irq_worker, 0, |
| 895 | dev_name(&pdev->dev), host); |
| 896 | if (ret) { |
| 897 | dev_err(&pdev->dev, "Failed to request irq: %d\n", ret); |
| 898 | goto err_free_card_detect_irq; |
| 899 | } |
| 900 | |
| 901 | jz4740_mmc_reset(host); |
| 902 | jz4740_mmc_clock_disable(host); |
| 903 | setup_timer(&host->timeout_timer, jz4740_mmc_timeout, |
| 904 | (unsigned long)host); |
| 905 | /* It is not important when it times out, it just needs to timeout. */ |
| 906 | set_timer_slack(&host->timeout_timer, HZ); |
| 907 | |
| 908 | platform_set_drvdata(pdev, host); |
| 909 | ret = mmc_add_host(mmc); |
| 910 | |
| 911 | if (ret) { |
| 912 | dev_err(&pdev->dev, "Failed to add mmc host: %d\n", ret); |
| 913 | goto err_free_irq; |
| 914 | } |
| 915 | dev_info(&pdev->dev, "JZ SD/MMC card driver registered\n"); |
| 916 | |
| 917 | return 0; |
| 918 | |
| 919 | err_free_irq: |
| 920 | free_irq(host->irq, host); |
| 921 | err_free_card_detect_irq: |
| 922 | if (host->card_detect_irq >= 0) |
| 923 | free_irq(host->card_detect_irq, host); |
| 924 | err_free_gpios: |
| 925 | jz4740_mmc_free_gpios(pdev); |
| 926 | err_gpio_bulk_free: |
| 927 | jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); |
| 928 | err_iounmap: |
| 929 | iounmap(host->base); |
| 930 | err_release_mem_region: |
| 931 | release_mem_region(host->mem->start, resource_size(host->mem)); |
| 932 | err_clk_put: |
| 933 | clk_put(host->clk); |
| 934 | err_free_host: |
| 935 | platform_set_drvdata(pdev, NULL); |
| 936 | mmc_free_host(mmc); |
| 937 | |
| 938 | return ret; |
| 939 | } |
| 940 | |
| 941 | static int __devexit jz4740_mmc_remove(struct platform_device *pdev) |
| 942 | { |
| 943 | struct jz4740_mmc_host *host = platform_get_drvdata(pdev); |
| 944 | |
| 945 | del_timer_sync(&host->timeout_timer); |
| 946 | jz4740_mmc_set_irq_enabled(host, 0xff, false); |
| 947 | jz4740_mmc_reset(host); |
| 948 | |
| 949 | mmc_remove_host(host->mmc); |
| 950 | |
| 951 | free_irq(host->irq, host); |
| 952 | if (host->card_detect_irq >= 0) |
| 953 | free_irq(host->card_detect_irq, host); |
| 954 | |
| 955 | jz4740_mmc_free_gpios(pdev); |
| 956 | jz_gpio_bulk_free(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); |
| 957 | |
| 958 | iounmap(host->base); |
| 959 | release_mem_region(host->mem->start, resource_size(host->mem)); |
| 960 | |
| 961 | clk_put(host->clk); |
| 962 | |
| 963 | platform_set_drvdata(pdev, NULL); |
| 964 | mmc_free_host(host->mmc); |
| 965 | |
| 966 | return 0; |
| 967 | } |
| 968 | |
| 969 | #ifdef CONFIG_PM |
| 970 | |
| 971 | static int jz4740_mmc_suspend(struct device *dev) |
| 972 | { |
| 973 | struct jz4740_mmc_host *host = dev_get_drvdata(dev); |
| 974 | |
| 975 | mmc_suspend_host(host->mmc); |
| 976 | |
| 977 | jz_gpio_bulk_suspend(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); |
| 978 | |
| 979 | return 0; |
| 980 | } |
| 981 | |
| 982 | static int jz4740_mmc_resume(struct device *dev) |
| 983 | { |
| 984 | struct jz4740_mmc_host *host = dev_get_drvdata(dev); |
| 985 | |
| 986 | jz_gpio_bulk_resume(jz4740_mmc_pins, jz4740_mmc_num_pins(host)); |
| 987 | |
| 988 | mmc_resume_host(host->mmc); |
| 989 | |
| 990 | return 0; |
| 991 | } |
| 992 | |
| 993 | const struct dev_pm_ops jz4740_mmc_pm_ops = { |
| 994 | .suspend = jz4740_mmc_suspend, |
| 995 | .resume = jz4740_mmc_resume, |
| 996 | .poweroff = jz4740_mmc_suspend, |
| 997 | .restore = jz4740_mmc_resume, |
| 998 | }; |
| 999 | |
| 1000 | #define JZ4740_MMC_PM_OPS (&jz4740_mmc_pm_ops) |
| 1001 | #else |
| 1002 | #define JZ4740_MMC_PM_OPS NULL |
| 1003 | #endif |
| 1004 | |
| 1005 | static struct platform_driver jz4740_mmc_driver = { |
| 1006 | .probe = jz4740_mmc_probe, |
Bill Pemberton | 0433c14 | 2012-11-19 13:20:26 -0500 | [diff] [blame^] | 1007 | .remove = jz4740_mmc_remove, |
Lars-Peter Clausen | 61bfbdb | 2010-07-15 20:06:04 +0000 | [diff] [blame] | 1008 | .driver = { |
| 1009 | .name = "jz4740-mmc", |
| 1010 | .owner = THIS_MODULE, |
| 1011 | .pm = JZ4740_MMC_PM_OPS, |
| 1012 | }, |
| 1013 | }; |
| 1014 | |
Axel Lin | d1f81a6 | 2011-11-26 12:55:43 +0800 | [diff] [blame] | 1015 | module_platform_driver(jz4740_mmc_driver); |
Lars-Peter Clausen | 61bfbdb | 2010-07-15 20:06:04 +0000 | [diff] [blame] | 1016 | |
| 1017 | MODULE_DESCRIPTION("JZ4740 SD/MMC controller driver"); |
| 1018 | MODULE_LICENSE("GPL"); |
| 1019 | MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>"); |