blob: c7c391bc116a6a22ed830a64be2a48514e114eb9 [file] [log] [blame]
Jesse Barnes79e53942008-11-07 14:24:08 -08001/*
2 * Copyright © 2007 Dave Mueller
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Dave Mueller <dave.mueller@gmx.ch>
25 *
26 */
27
28#include "dvo.h"
29
30/* register definitions according to the TFP410 data sheet */
31#define TFP410_VID 0x014C
32#define TFP410_DID 0x0410
33
34#define TFP410_VID_LO 0x00
35#define TFP410_VID_HI 0x01
36#define TFP410_DID_LO 0x02
37#define TFP410_DID_HI 0x03
38#define TFP410_REV 0x04
39
40#define TFP410_CTL_1 0x08
41#define TFP410_CTL_1_TDIS (1<<6)
42#define TFP410_CTL_1_VEN (1<<5)
43#define TFP410_CTL_1_HEN (1<<4)
44#define TFP410_CTL_1_DSEL (1<<3)
45#define TFP410_CTL_1_BSEL (1<<2)
46#define TFP410_CTL_1_EDGE (1<<1)
47#define TFP410_CTL_1_PD (1<<0)
48
49#define TFP410_CTL_2 0x09
50#define TFP410_CTL_2_VLOW (1<<7)
51#define TFP410_CTL_2_MSEL_MASK (0x7<<4)
52#define TFP410_CTL_2_MSEL (1<<4)
53#define TFP410_CTL_2_TSEL (1<<3)
54#define TFP410_CTL_2_RSEN (1<<2)
55#define TFP410_CTL_2_HTPLG (1<<1)
56#define TFP410_CTL_2_MDI (1<<0)
57
58#define TFP410_CTL_3 0x0A
59#define TFP410_CTL_3_DK_MASK (0x7<<5)
60#define TFP410_CTL_3_DK (1<<5)
61#define TFP410_CTL_3_DKEN (1<<4)
62#define TFP410_CTL_3_CTL_MASK (0x7<<1)
63#define TFP410_CTL_3_CTL (1<<1)
64
65#define TFP410_USERCFG 0x0B
66
67#define TFP410_DE_DLY 0x32
68
69#define TFP410_DE_CTL 0x33
70#define TFP410_DE_CTL_DEGEN (1<<6)
71#define TFP410_DE_CTL_VSPOL (1<<5)
72#define TFP410_DE_CTL_HSPOL (1<<4)
73#define TFP410_DE_CTL_DEDLY8 (1<<0)
74
75#define TFP410_DE_TOP 0x34
76
77#define TFP410_DE_CNT_LO 0x36
78#define TFP410_DE_CNT_HI 0x37
79
80#define TFP410_DE_LIN_LO 0x38
81#define TFP410_DE_LIN_HI 0x39
82
83#define TFP410_H_RES_LO 0x3A
84#define TFP410_H_RES_HI 0x3B
85
86#define TFP410_V_RES_LO 0x3C
87#define TFP410_V_RES_HI 0x3D
88
89struct tfp410_save_rec {
90 uint8_t ctl1;
91 uint8_t ctl2;
92};
93
94struct tfp410_priv {
95 bool quiet;
96
97 struct tfp410_save_rec saved_reg;
98 struct tfp410_save_rec mode_reg;
99};
100
101static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, uint8_t *ch)
102{
103 struct tfp410_priv *tfp = dvo->dev_priv;
Keith Packardf9c10a92009-05-30 12:16:25 -0700104 struct i2c_adapter *adapter = dvo->i2c_bus;
105 struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
Jesse Barnes79e53942008-11-07 14:24:08 -0800106 u8 out_buf[2];
107 u8 in_buf[2];
108
109 struct i2c_msg msgs[] = {
110 {
Keith Packardf9c10a92009-05-30 12:16:25 -0700111 .addr = dvo->slave_addr,
Jesse Barnes79e53942008-11-07 14:24:08 -0800112 .flags = 0,
113 .len = 1,
114 .buf = out_buf,
115 },
116 {
Keith Packardf9c10a92009-05-30 12:16:25 -0700117 .addr = dvo->slave_addr,
Jesse Barnes79e53942008-11-07 14:24:08 -0800118 .flags = I2C_M_RD,
119 .len = 1,
120 .buf = in_buf,
121 }
122 };
123
124 out_buf[0] = addr;
125 out_buf[1] = 0;
126
127 if (i2c_transfer(&i2cbus->adapter, msgs, 2) == 2) {
128 *ch = in_buf[0];
129 return true;
130 };
131
132 if (!tfp->quiet) {
Zhao Yakuid0c3b042009-10-09 11:39:43 +0800133 DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
Keith Packardf9c10a92009-05-30 12:16:25 -0700134 addr, i2cbus->adapter.name, dvo->slave_addr);
Jesse Barnes79e53942008-11-07 14:24:08 -0800135 }
136 return false;
137}
138
139static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, uint8_t ch)
140{
141 struct tfp410_priv *tfp = dvo->dev_priv;
Keith Packardf9c10a92009-05-30 12:16:25 -0700142 struct i2c_adapter *adapter = dvo->i2c_bus;
143 struct intel_i2c_chan *i2cbus = container_of(adapter, struct intel_i2c_chan, adapter);
Jesse Barnes79e53942008-11-07 14:24:08 -0800144 uint8_t out_buf[2];
145 struct i2c_msg msg = {
Keith Packardf9c10a92009-05-30 12:16:25 -0700146 .addr = dvo->slave_addr,
Jesse Barnes79e53942008-11-07 14:24:08 -0800147 .flags = 0,
148 .len = 2,
149 .buf = out_buf,
150 };
151
152 out_buf[0] = addr;
153 out_buf[1] = ch;
154
155 if (i2c_transfer(&i2cbus->adapter, &msg, 1) == 1)
156 return true;
157
158 if (!tfp->quiet) {
Zhao Yakuid0c3b042009-10-09 11:39:43 +0800159 DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
Keith Packardf9c10a92009-05-30 12:16:25 -0700160 addr, i2cbus->adapter.name, dvo->slave_addr);
Jesse Barnes79e53942008-11-07 14:24:08 -0800161 }
162
163 return false;
164}
165
166static int tfp410_getid(struct intel_dvo_device *dvo, int addr)
167{
168 uint8_t ch1, ch2;
169
170 if (tfp410_readb(dvo, addr+0, &ch1) &&
171 tfp410_readb(dvo, addr+1, &ch2))
172 return ((ch2 << 8) & 0xFF00) | (ch1 & 0x00FF);
173
174 return -1;
175}
176
177/* Ti TFP410 driver for chip on i2c bus */
178static bool tfp410_init(struct intel_dvo_device *dvo,
Keith Packardf9c10a92009-05-30 12:16:25 -0700179 struct i2c_adapter *adapter)
Jesse Barnes79e53942008-11-07 14:24:08 -0800180{
181 /* this will detect the tfp410 chip on the specified i2c bus */
182 struct tfp410_priv *tfp;
183 int id;
184
185 tfp = kzalloc(sizeof(struct tfp410_priv), GFP_KERNEL);
186 if (tfp == NULL)
187 return false;
188
Keith Packardf9c10a92009-05-30 12:16:25 -0700189 dvo->i2c_bus = adapter;
Jesse Barnes79e53942008-11-07 14:24:08 -0800190 dvo->dev_priv = tfp;
191 tfp->quiet = true;
192
193 if ((id = tfp410_getid(dvo, TFP410_VID_LO)) != TFP410_VID) {
Zhao Yakuid0c3b042009-10-09 11:39:43 +0800194 DRM_DEBUG_KMS("tfp410 not detected got VID %X: from %s "
195 "Slave %d.\n",
Keith Packardf9c10a92009-05-30 12:16:25 -0700196 id, adapter->name, dvo->slave_addr);
Jesse Barnes79e53942008-11-07 14:24:08 -0800197 goto out;
198 }
199
200 if ((id = tfp410_getid(dvo, TFP410_DID_LO)) != TFP410_DID) {
Zhao Yakuid0c3b042009-10-09 11:39:43 +0800201 DRM_DEBUG_KMS("tfp410 not detected got DID %X: from %s "
202 "Slave %d.\n",
Keith Packardf9c10a92009-05-30 12:16:25 -0700203 id, adapter->name, dvo->slave_addr);
Jesse Barnes79e53942008-11-07 14:24:08 -0800204 goto out;
205 }
206 tfp->quiet = false;
207 return true;
208out:
209 kfree(tfp);
210 return false;
211}
212
213static enum drm_connector_status tfp410_detect(struct intel_dvo_device *dvo)
214{
215 enum drm_connector_status ret = connector_status_disconnected;
216 uint8_t ctl2;
217
218 if (tfp410_readb(dvo, TFP410_CTL_2, &ctl2)) {
219 if (ctl2 & TFP410_CTL_2_HTPLG)
220 ret = connector_status_connected;
221 else
222 ret = connector_status_disconnected;
223 }
224
225 return ret;
226}
227
228static enum drm_mode_status tfp410_mode_valid(struct intel_dvo_device *dvo,
229 struct drm_display_mode *mode)
230{
231 return MODE_OK;
232}
233
234static void tfp410_mode_set(struct intel_dvo_device *dvo,
235 struct drm_display_mode *mode,
236 struct drm_display_mode *adjusted_mode)
237{
238 /* As long as the basics are set up, since we don't have clock dependencies
239 * in the mode setup, we can just leave the registers alone and everything
240 * will work fine.
241 */
242 /* don't do much */
243 return;
244}
245
246/* set the tfp410 power state */
247static void tfp410_dpms(struct intel_dvo_device *dvo, int mode)
248{
249 uint8_t ctl1;
250
251 if (!tfp410_readb(dvo, TFP410_CTL_1, &ctl1))
252 return;
253
254 if (mode == DRM_MODE_DPMS_ON)
255 ctl1 |= TFP410_CTL_1_PD;
256 else
257 ctl1 &= ~TFP410_CTL_1_PD;
258
259 tfp410_writeb(dvo, TFP410_CTL_1, ctl1);
260}
261
262static void tfp410_dump_regs(struct intel_dvo_device *dvo)
263{
264 uint8_t val, val2;
265
266 tfp410_readb(dvo, TFP410_REV, &val);
Zhao Yakuid0c3b042009-10-09 11:39:43 +0800267 DRM_LOG_KMS("TFP410_REV: 0x%02X\n", val);
Jesse Barnes79e53942008-11-07 14:24:08 -0800268 tfp410_readb(dvo, TFP410_CTL_1, &val);
Zhao Yakuid0c3b042009-10-09 11:39:43 +0800269 DRM_LOG_KMS("TFP410_CTL1: 0x%02X\n", val);
Jesse Barnes79e53942008-11-07 14:24:08 -0800270 tfp410_readb(dvo, TFP410_CTL_2, &val);
Zhao Yakuid0c3b042009-10-09 11:39:43 +0800271 DRM_LOG_KMS("TFP410_CTL2: 0x%02X\n", val);
Jesse Barnes79e53942008-11-07 14:24:08 -0800272 tfp410_readb(dvo, TFP410_CTL_3, &val);
Zhao Yakuid0c3b042009-10-09 11:39:43 +0800273 DRM_LOG_KMS("TFP410_CTL3: 0x%02X\n", val);
Jesse Barnes79e53942008-11-07 14:24:08 -0800274 tfp410_readb(dvo, TFP410_USERCFG, &val);
Zhao Yakuid0c3b042009-10-09 11:39:43 +0800275 DRM_LOG_KMS("TFP410_USERCFG: 0x%02X\n", val);
Jesse Barnes79e53942008-11-07 14:24:08 -0800276 tfp410_readb(dvo, TFP410_DE_DLY, &val);
Zhao Yakuid0c3b042009-10-09 11:39:43 +0800277 DRM_LOG_KMS("TFP410_DE_DLY: 0x%02X\n", val);
Jesse Barnes79e53942008-11-07 14:24:08 -0800278 tfp410_readb(dvo, TFP410_DE_CTL, &val);
Zhao Yakuid0c3b042009-10-09 11:39:43 +0800279 DRM_LOG_KMS("TFP410_DE_CTL: 0x%02X\n", val);
Jesse Barnes79e53942008-11-07 14:24:08 -0800280 tfp410_readb(dvo, TFP410_DE_TOP, &val);
Zhao Yakuid0c3b042009-10-09 11:39:43 +0800281 DRM_LOG_KMS("TFP410_DE_TOP: 0x%02X\n", val);
Jesse Barnes79e53942008-11-07 14:24:08 -0800282 tfp410_readb(dvo, TFP410_DE_CNT_LO, &val);
283 tfp410_readb(dvo, TFP410_DE_CNT_HI, &val2);
Zhao Yakuid0c3b042009-10-09 11:39:43 +0800284 DRM_LOG_KMS("TFP410_DE_CNT: 0x%02X%02X\n", val2, val);
Jesse Barnes79e53942008-11-07 14:24:08 -0800285 tfp410_readb(dvo, TFP410_DE_LIN_LO, &val);
286 tfp410_readb(dvo, TFP410_DE_LIN_HI, &val2);
Zhao Yakuid0c3b042009-10-09 11:39:43 +0800287 DRM_LOG_KMS("TFP410_DE_LIN: 0x%02X%02X\n", val2, val);
Jesse Barnes79e53942008-11-07 14:24:08 -0800288 tfp410_readb(dvo, TFP410_H_RES_LO, &val);
289 tfp410_readb(dvo, TFP410_H_RES_HI, &val2);
Zhao Yakuid0c3b042009-10-09 11:39:43 +0800290 DRM_LOG_KMS("TFP410_H_RES: 0x%02X%02X\n", val2, val);
Jesse Barnes79e53942008-11-07 14:24:08 -0800291 tfp410_readb(dvo, TFP410_V_RES_LO, &val);
292 tfp410_readb(dvo, TFP410_V_RES_HI, &val2);
Zhao Yakuid0c3b042009-10-09 11:39:43 +0800293 DRM_LOG_KMS("TFP410_V_RES: 0x%02X%02X\n", val2, val);
Jesse Barnes79e53942008-11-07 14:24:08 -0800294}
295
296static void tfp410_save(struct intel_dvo_device *dvo)
297{
298 struct tfp410_priv *tfp = dvo->dev_priv;
299
300 if (!tfp410_readb(dvo, TFP410_CTL_1, &tfp->saved_reg.ctl1))
301 return;
302
303 if (!tfp410_readb(dvo, TFP410_CTL_2, &tfp->saved_reg.ctl2))
304 return;
305}
306
307static void tfp410_restore(struct intel_dvo_device *dvo)
308{
309 struct tfp410_priv *tfp = dvo->dev_priv;
310
311 /* Restore it powered down initially */
312 tfp410_writeb(dvo, TFP410_CTL_1, tfp->saved_reg.ctl1 & ~0x1);
313
314 tfp410_writeb(dvo, TFP410_CTL_2, tfp->saved_reg.ctl2);
315 tfp410_writeb(dvo, TFP410_CTL_1, tfp->saved_reg.ctl1);
316}
317
318static void tfp410_destroy(struct intel_dvo_device *dvo)
319{
320 struct tfp410_priv *tfp = dvo->dev_priv;
321
322 if (tfp) {
323 kfree(tfp);
324 dvo->dev_priv = NULL;
325 }
326}
327
328struct intel_dvo_dev_ops tfp410_ops = {
329 .init = tfp410_init,
330 .detect = tfp410_detect,
331 .mode_valid = tfp410_mode_valid,
332 .mode_set = tfp410_mode_set,
333 .dpms = tfp410_dpms,
334 .dump_regs = tfp410_dump_regs,
335 .save = tfp410_save,
336 .restore = tfp410_restore,
337 .destroy = tfp410_destroy,
338};