Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright(c) 2007 Atheros Corporation. All rights reserved. |
| 3 | * |
| 4 | * Derived from Intel e1000 driver |
| 5 | * Copyright(c) 1999 - 2005 Intel Corporation. All rights reserved. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify it |
| 8 | * under the terms of the GNU General Public License as published by the Free |
| 9 | * Software Foundation; either version 2 of the License, or (at your option) |
| 10 | * any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 13 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 14 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 15 | * more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License along with |
| 18 | * this program; if not, write to the Free Software Foundation, Inc., 59 |
| 19 | * Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| 20 | */ |
| 21 | #include <linux/pci.h> |
| 22 | #include <linux/delay.h> |
| 23 | #include <linux/mii.h> |
| 24 | #include <linux/crc32.h> |
| 25 | |
| 26 | #include "atl1c.h" |
| 27 | |
| 28 | /* |
| 29 | * check_eeprom_exist |
| 30 | * return 1 if eeprom exist |
| 31 | */ |
| 32 | int atl1c_check_eeprom_exist(struct atl1c_hw *hw) |
| 33 | { |
| 34 | u32 data; |
| 35 | |
| 36 | AT_READ_REG(hw, REG_TWSI_DEBUG, &data); |
| 37 | if (data & TWSI_DEBUG_DEV_EXIST) |
| 38 | return 1; |
| 39 | |
Jie Yang | 8f574b3 | 2010-06-01 00:28:12 -0700 | [diff] [blame] | 40 | AT_READ_REG(hw, REG_MASTER_CTRL, &data); |
| 41 | if (data & MASTER_CTRL_OTP_SEL) |
| 42 | return 1; |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 43 | return 0; |
| 44 | } |
| 45 | |
Huang, Xiong | 229e6b6 | 2012-04-30 15:38:53 +0000 | [diff] [blame] | 46 | void atl1c_hw_set_mac_addr(struct atl1c_hw *hw, u8 *mac_addr) |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 47 | { |
| 48 | u32 value; |
| 49 | /* |
| 50 | * 00-0B-6A-F6-00-DC |
| 51 | * 0: 6AF600DC 1: 000B |
| 52 | * low dword |
| 53 | */ |
Huang, Xiong | 229e6b6 | 2012-04-30 15:38:53 +0000 | [diff] [blame] | 54 | value = mac_addr[2] << 24 | |
| 55 | mac_addr[3] << 16 | |
| 56 | mac_addr[4] << 8 | |
| 57 | mac_addr[5]; |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 58 | AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 0, value); |
| 59 | /* hight dword */ |
Huang, Xiong | 229e6b6 | 2012-04-30 15:38:53 +0000 | [diff] [blame] | 60 | value = mac_addr[0] << 8 | |
| 61 | mac_addr[1]; |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 62 | AT_WRITE_REG_ARRAY(hw, REG_MAC_STA_ADDR, 1, value); |
| 63 | } |
| 64 | |
Huang, Xiong | 229e6b6 | 2012-04-30 15:38:53 +0000 | [diff] [blame] | 65 | /* read mac address from hardware register */ |
| 66 | static bool atl1c_read_current_addr(struct atl1c_hw *hw, u8 *eth_addr) |
| 67 | { |
| 68 | u32 addr[2]; |
| 69 | |
| 70 | AT_READ_REG(hw, REG_MAC_STA_ADDR, &addr[0]); |
| 71 | AT_READ_REG(hw, REG_MAC_STA_ADDR + 4, &addr[1]); |
| 72 | |
| 73 | *(u32 *) ð_addr[2] = htonl(addr[0]); |
| 74 | *(u16 *) ð_addr[0] = htons((u16)addr[1]); |
| 75 | |
| 76 | return is_valid_ether_addr(eth_addr); |
| 77 | } |
| 78 | |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 79 | /* |
| 80 | * atl1c_get_permanent_address |
| 81 | * return 0 if get valid mac address, |
| 82 | */ |
| 83 | static int atl1c_get_permanent_address(struct atl1c_hw *hw) |
| 84 | { |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 85 | u32 i; |
| 86 | u32 otp_ctrl_data; |
| 87 | u32 twsi_ctrl_data; |
Luis R. Rodriguez | 496c185 | 2010-02-16 15:16:45 -0800 | [diff] [blame] | 88 | u16 phy_data; |
| 89 | bool raise_vol = false; |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 90 | |
Huang, Xiong | 229e6b6 | 2012-04-30 15:38:53 +0000 | [diff] [blame] | 91 | /* MAC-address from BIOS is the 1st priority */ |
| 92 | if (atl1c_read_current_addr(hw, hw->perm_mac_addr)) |
| 93 | return 0; |
| 94 | |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 95 | /* init */ |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 96 | AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data); |
| 97 | if (atl1c_check_eeprom_exist(hw)) { |
Ben Hutchings | 33ac0b8 | 2010-11-21 10:06:48 -0800 | [diff] [blame] | 98 | if (hw->nic_type == athr_l1c || hw->nic_type == athr_l2c) { |
Luis R. Rodriguez | 496c185 | 2010-02-16 15:16:45 -0800 | [diff] [blame] | 99 | /* Enable OTP CLK */ |
| 100 | if (!(otp_ctrl_data & OTP_CTRL_CLK_EN)) { |
| 101 | otp_ctrl_data |= OTP_CTRL_CLK_EN; |
| 102 | AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data); |
| 103 | AT_WRITE_FLUSH(hw); |
| 104 | msleep(1); |
| 105 | } |
| 106 | } |
Huang, Xiong | 229e6b6 | 2012-04-30 15:38:53 +0000 | [diff] [blame] | 107 | /* raise voltage temporally for l2cb */ |
| 108 | if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2) { |
| 109 | atl1c_read_phy_dbg(hw, MIIDBG_ANACTRL, &phy_data); |
| 110 | phy_data &= ~ANACTRL_HB_EN; |
| 111 | atl1c_write_phy_dbg(hw, MIIDBG_ANACTRL, phy_data); |
| 112 | atl1c_read_phy_dbg(hw, MIIDBG_VOLT_CTRL, &phy_data); |
| 113 | phy_data |= VOLT_CTRL_SWLOWEST; |
| 114 | atl1c_write_phy_dbg(hw, MIIDBG_VOLT_CTRL, phy_data); |
Luis R. Rodriguez | 496c185 | 2010-02-16 15:16:45 -0800 | [diff] [blame] | 115 | udelay(20); |
| 116 | raise_vol = true; |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 117 | } |
| 118 | |
| 119 | AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data); |
| 120 | twsi_ctrl_data |= TWSI_CTRL_SW_LDSTART; |
| 121 | AT_WRITE_REG(hw, REG_TWSI_CTRL, twsi_ctrl_data); |
| 122 | for (i = 0; i < AT_TWSI_EEPROM_TIMEOUT; i++) { |
| 123 | msleep(10); |
| 124 | AT_READ_REG(hw, REG_TWSI_CTRL, &twsi_ctrl_data); |
| 125 | if ((twsi_ctrl_data & TWSI_CTRL_SW_LDSTART) == 0) |
| 126 | break; |
| 127 | } |
| 128 | if (i >= AT_TWSI_EEPROM_TIMEOUT) |
| 129 | return -1; |
| 130 | } |
| 131 | /* Disable OTP_CLK */ |
Luis R. Rodriguez | 496c185 | 2010-02-16 15:16:45 -0800 | [diff] [blame] | 132 | if ((hw->nic_type == athr_l1c || hw->nic_type == athr_l2c)) { |
Jie Yang | 8f574b3 | 2010-06-01 00:28:12 -0700 | [diff] [blame] | 133 | otp_ctrl_data &= ~OTP_CTRL_CLK_EN; |
| 134 | AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data); |
| 135 | msleep(1); |
Luis R. Rodriguez | 496c185 | 2010-02-16 15:16:45 -0800 | [diff] [blame] | 136 | } |
| 137 | if (raise_vol) { |
Huang, Xiong | 229e6b6 | 2012-04-30 15:38:53 +0000 | [diff] [blame] | 138 | atl1c_read_phy_dbg(hw, MIIDBG_ANACTRL, &phy_data); |
| 139 | phy_data |= ANACTRL_HB_EN; |
| 140 | atl1c_write_phy_dbg(hw, MIIDBG_ANACTRL, phy_data); |
| 141 | atl1c_read_phy_dbg(hw, MIIDBG_VOLT_CTRL, &phy_data); |
| 142 | phy_data &= ~VOLT_CTRL_SWLOWEST; |
| 143 | atl1c_write_phy_dbg(hw, MIIDBG_VOLT_CTRL, phy_data); |
| 144 | udelay(20); |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 145 | } |
| 146 | |
Huang, Xiong | 229e6b6 | 2012-04-30 15:38:53 +0000 | [diff] [blame] | 147 | if (atl1c_read_current_addr(hw, hw->perm_mac_addr)) |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 148 | return 0; |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 149 | |
| 150 | return -1; |
| 151 | } |
| 152 | |
| 153 | bool atl1c_read_eeprom(struct atl1c_hw *hw, u32 offset, u32 *p_value) |
| 154 | { |
| 155 | int i; |
| 156 | int ret = false; |
| 157 | u32 otp_ctrl_data; |
| 158 | u32 control; |
| 159 | u32 data; |
| 160 | |
| 161 | if (offset & 3) |
| 162 | return ret; /* address do not align */ |
| 163 | |
| 164 | AT_READ_REG(hw, REG_OTP_CTRL, &otp_ctrl_data); |
| 165 | if (!(otp_ctrl_data & OTP_CTRL_CLK_EN)) |
| 166 | AT_WRITE_REG(hw, REG_OTP_CTRL, |
| 167 | (otp_ctrl_data | OTP_CTRL_CLK_EN)); |
| 168 | |
| 169 | AT_WRITE_REG(hw, REG_EEPROM_DATA_LO, 0); |
| 170 | control = (offset & EEPROM_CTRL_ADDR_MASK) << EEPROM_CTRL_ADDR_SHIFT; |
| 171 | AT_WRITE_REG(hw, REG_EEPROM_CTRL, control); |
| 172 | |
| 173 | for (i = 0; i < 10; i++) { |
| 174 | udelay(100); |
| 175 | AT_READ_REG(hw, REG_EEPROM_CTRL, &control); |
| 176 | if (control & EEPROM_CTRL_RW) |
| 177 | break; |
| 178 | } |
| 179 | if (control & EEPROM_CTRL_RW) { |
| 180 | AT_READ_REG(hw, REG_EEPROM_CTRL, &data); |
| 181 | AT_READ_REG(hw, REG_EEPROM_DATA_LO, p_value); |
| 182 | data = data & 0xFFFF; |
| 183 | *p_value = swab32((data << 16) | (*p_value >> 16)); |
| 184 | ret = true; |
| 185 | } |
| 186 | if (!(otp_ctrl_data & OTP_CTRL_CLK_EN)) |
| 187 | AT_WRITE_REG(hw, REG_OTP_CTRL, otp_ctrl_data); |
| 188 | |
| 189 | return ret; |
| 190 | } |
| 191 | /* |
| 192 | * Reads the adapter's MAC address from the EEPROM |
| 193 | * |
| 194 | * hw - Struct containing variables accessed by shared code |
| 195 | */ |
| 196 | int atl1c_read_mac_addr(struct atl1c_hw *hw) |
| 197 | { |
| 198 | int err = 0; |
| 199 | |
| 200 | err = atl1c_get_permanent_address(hw); |
| 201 | if (err) |
| 202 | random_ether_addr(hw->perm_mac_addr); |
| 203 | |
| 204 | memcpy(hw->mac_addr, hw->perm_mac_addr, sizeof(hw->perm_mac_addr)); |
Danny Kukawka | 6a214fd | 2012-02-17 05:43:30 +0000 | [diff] [blame] | 205 | return err; |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 206 | } |
| 207 | |
| 208 | /* |
| 209 | * atl1c_hash_mc_addr |
| 210 | * purpose |
| 211 | * set hash value for a multicast address |
| 212 | * hash calcu processing : |
| 213 | * 1. calcu 32bit CRC for multicast address |
| 214 | * 2. reverse crc with MSB to LSB |
| 215 | */ |
| 216 | u32 atl1c_hash_mc_addr(struct atl1c_hw *hw, u8 *mc_addr) |
| 217 | { |
| 218 | u32 crc32; |
| 219 | u32 value = 0; |
| 220 | int i; |
| 221 | |
| 222 | crc32 = ether_crc_le(6, mc_addr); |
| 223 | for (i = 0; i < 32; i++) |
| 224 | value |= (((crc32 >> i) & 1) << (31 - i)); |
| 225 | |
| 226 | return value; |
| 227 | } |
| 228 | |
| 229 | /* |
| 230 | * Sets the bit in the multicast table corresponding to the hash value. |
| 231 | * hw - Struct containing variables accessed by shared code |
| 232 | * hash_value - Multicast address hash value |
| 233 | */ |
| 234 | void atl1c_hash_set(struct atl1c_hw *hw, u32 hash_value) |
| 235 | { |
| 236 | u32 hash_bit, hash_reg; |
| 237 | u32 mta; |
| 238 | |
| 239 | /* |
| 240 | * The HASH Table is a register array of 2 32-bit registers. |
| 241 | * It is treated like an array of 64 bits. We want to set |
| 242 | * bit BitArray[hash_value]. So we figure out what register |
| 243 | * the bit is in, read it, OR in the new bit, then write |
| 244 | * back the new value. The register is determined by the |
| 245 | * upper bit of the hash value and the bit within that |
| 246 | * register are determined by the lower 5 bits of the value. |
| 247 | */ |
| 248 | hash_reg = (hash_value >> 31) & 0x1; |
| 249 | hash_bit = (hash_value >> 26) & 0x1F; |
| 250 | |
| 251 | mta = AT_READ_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg); |
| 252 | |
| 253 | mta |= (1 << hash_bit); |
| 254 | |
| 255 | AT_WRITE_REG_ARRAY(hw, REG_RX_HASH_TABLE, hash_reg, mta); |
| 256 | } |
| 257 | |
| 258 | /* |
Huang, Xiong | 929a5e9 | 2012-04-25 20:27:10 +0000 | [diff] [blame] | 259 | * wait mdio module be idle |
| 260 | * return true: idle |
| 261 | * false: still busy |
| 262 | */ |
| 263 | bool atl1c_wait_mdio_idle(struct atl1c_hw *hw) |
| 264 | { |
| 265 | u32 val; |
| 266 | int i; |
| 267 | |
| 268 | for (i = 0; i < MDIO_MAX_AC_TO; i++) { |
| 269 | AT_READ_REG(hw, REG_MDIO_CTRL, &val); |
| 270 | if (!(val & (MDIO_CTRL_BUSY | MDIO_CTRL_START))) |
| 271 | break; |
| 272 | udelay(10); |
| 273 | } |
| 274 | |
| 275 | return i != MDIO_MAX_AC_TO; |
| 276 | } |
| 277 | |
| 278 | void atl1c_stop_phy_polling(struct atl1c_hw *hw) |
| 279 | { |
| 280 | if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION)) |
| 281 | return; |
| 282 | |
| 283 | AT_WRITE_REG(hw, REG_MDIO_CTRL, 0); |
| 284 | atl1c_wait_mdio_idle(hw); |
| 285 | } |
| 286 | |
| 287 | void atl1c_start_phy_polling(struct atl1c_hw *hw, u16 clk_sel) |
| 288 | { |
| 289 | u32 val; |
| 290 | |
| 291 | if (!(hw->ctrl_flags & ATL1C_FPGA_VERSION)) |
| 292 | return; |
| 293 | |
| 294 | val = MDIO_CTRL_SPRES_PRMBL | |
| 295 | FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | |
| 296 | FIELDX(MDIO_CTRL_REG, 1) | |
| 297 | MDIO_CTRL_START | |
| 298 | MDIO_CTRL_OP_READ; |
| 299 | AT_WRITE_REG(hw, REG_MDIO_CTRL, val); |
| 300 | atl1c_wait_mdio_idle(hw); |
| 301 | val |= MDIO_CTRL_AP_EN; |
| 302 | val &= ~MDIO_CTRL_START; |
| 303 | AT_WRITE_REG(hw, REG_MDIO_CTRL, val); |
| 304 | udelay(30); |
| 305 | } |
| 306 | |
| 307 | |
| 308 | /* |
| 309 | * atl1c_read_phy_core |
| 310 | * core funtion to read register in PHY via MDIO control regsiter. |
| 311 | * ext: extension register (see IEEE 802.3) |
| 312 | * dev: device address (see IEEE 802.3 DEVAD, PRTAD is fixed to 0) |
| 313 | * reg: reg to read |
| 314 | */ |
| 315 | int atl1c_read_phy_core(struct atl1c_hw *hw, bool ext, u8 dev, |
| 316 | u16 reg, u16 *phy_data) |
| 317 | { |
| 318 | u32 val; |
| 319 | u16 clk_sel = MDIO_CTRL_CLK_25_4; |
| 320 | |
| 321 | atl1c_stop_phy_polling(hw); |
| 322 | |
| 323 | *phy_data = 0; |
| 324 | |
| 325 | /* only l2c_b2 & l1d_2 could use slow clock */ |
| 326 | if ((hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) && |
| 327 | hw->hibernate) |
| 328 | clk_sel = MDIO_CTRL_CLK_25_128; |
| 329 | if (ext) { |
| 330 | val = FIELDX(MDIO_EXTN_DEVAD, dev) | FIELDX(MDIO_EXTN_REG, reg); |
| 331 | AT_WRITE_REG(hw, REG_MDIO_EXTN, val); |
| 332 | val = MDIO_CTRL_SPRES_PRMBL | |
| 333 | FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | |
| 334 | MDIO_CTRL_START | |
| 335 | MDIO_CTRL_MODE_EXT | |
| 336 | MDIO_CTRL_OP_READ; |
| 337 | } else { |
| 338 | val = MDIO_CTRL_SPRES_PRMBL | |
| 339 | FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | |
| 340 | FIELDX(MDIO_CTRL_REG, reg) | |
| 341 | MDIO_CTRL_START | |
| 342 | MDIO_CTRL_OP_READ; |
| 343 | } |
| 344 | AT_WRITE_REG(hw, REG_MDIO_CTRL, val); |
| 345 | |
| 346 | if (!atl1c_wait_mdio_idle(hw)) |
| 347 | return -1; |
| 348 | |
| 349 | AT_READ_REG(hw, REG_MDIO_CTRL, &val); |
| 350 | *phy_data = (u16)FIELD_GETX(val, MDIO_CTRL_DATA); |
| 351 | |
| 352 | atl1c_start_phy_polling(hw, clk_sel); |
| 353 | |
| 354 | return 0; |
| 355 | } |
| 356 | |
| 357 | /* |
| 358 | * atl1c_write_phy_core |
| 359 | * core funtion to write to register in PHY via MDIO control regsiter. |
| 360 | * ext: extension register (see IEEE 802.3) |
| 361 | * dev: device address (see IEEE 802.3 DEVAD, PRTAD is fixed to 0) |
| 362 | * reg: reg to write |
| 363 | */ |
| 364 | int atl1c_write_phy_core(struct atl1c_hw *hw, bool ext, u8 dev, |
| 365 | u16 reg, u16 phy_data) |
| 366 | { |
| 367 | u32 val; |
| 368 | u16 clk_sel = MDIO_CTRL_CLK_25_4; |
| 369 | |
| 370 | atl1c_stop_phy_polling(hw); |
| 371 | |
| 372 | |
| 373 | /* only l2c_b2 & l1d_2 could use slow clock */ |
| 374 | if ((hw->nic_type == athr_l2c_b2 || hw->nic_type == athr_l1d_2) && |
| 375 | hw->hibernate) |
| 376 | clk_sel = MDIO_CTRL_CLK_25_128; |
| 377 | |
| 378 | if (ext) { |
| 379 | val = FIELDX(MDIO_EXTN_DEVAD, dev) | FIELDX(MDIO_EXTN_REG, reg); |
| 380 | AT_WRITE_REG(hw, REG_MDIO_EXTN, val); |
| 381 | val = MDIO_CTRL_SPRES_PRMBL | |
| 382 | FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | |
| 383 | FIELDX(MDIO_CTRL_DATA, phy_data) | |
| 384 | MDIO_CTRL_START | |
| 385 | MDIO_CTRL_MODE_EXT; |
| 386 | } else { |
| 387 | val = MDIO_CTRL_SPRES_PRMBL | |
| 388 | FIELDX(MDIO_CTRL_CLK_SEL, clk_sel) | |
| 389 | FIELDX(MDIO_CTRL_DATA, phy_data) | |
| 390 | FIELDX(MDIO_CTRL_REG, reg) | |
| 391 | MDIO_CTRL_START; |
| 392 | } |
| 393 | AT_WRITE_REG(hw, REG_MDIO_CTRL, val); |
| 394 | |
| 395 | if (!atl1c_wait_mdio_idle(hw)) |
| 396 | return -1; |
| 397 | |
| 398 | atl1c_start_phy_polling(hw, clk_sel); |
| 399 | |
| 400 | return 0; |
| 401 | } |
| 402 | |
| 403 | /* |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 404 | * Reads the value from a PHY register |
| 405 | * hw - Struct containing variables accessed by shared code |
| 406 | * reg_addr - address of the PHY register to read |
| 407 | */ |
| 408 | int atl1c_read_phy_reg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data) |
| 409 | { |
Huang, Xiong | 929a5e9 | 2012-04-25 20:27:10 +0000 | [diff] [blame] | 410 | return atl1c_read_phy_core(hw, false, 0, reg_addr, phy_data); |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 411 | } |
| 412 | |
| 413 | /* |
| 414 | * Writes a value to a PHY register |
| 415 | * hw - Struct containing variables accessed by shared code |
| 416 | * reg_addr - address of the PHY register to write |
| 417 | * data - data to write to the PHY |
| 418 | */ |
| 419 | int atl1c_write_phy_reg(struct atl1c_hw *hw, u32 reg_addr, u16 phy_data) |
| 420 | { |
Huang, Xiong | 929a5e9 | 2012-04-25 20:27:10 +0000 | [diff] [blame] | 421 | return atl1c_write_phy_core(hw, false, 0, reg_addr, phy_data); |
| 422 | } |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 423 | |
Huang, Xiong | 929a5e9 | 2012-04-25 20:27:10 +0000 | [diff] [blame] | 424 | /* read from PHY extension register */ |
| 425 | int atl1c_read_phy_ext(struct atl1c_hw *hw, u8 dev_addr, |
| 426 | u16 reg_addr, u16 *phy_data) |
| 427 | { |
| 428 | return atl1c_read_phy_core(hw, true, dev_addr, reg_addr, phy_data); |
| 429 | } |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 430 | |
Huang, Xiong | 929a5e9 | 2012-04-25 20:27:10 +0000 | [diff] [blame] | 431 | /* write to PHY extension register */ |
| 432 | int atl1c_write_phy_ext(struct atl1c_hw *hw, u8 dev_addr, |
| 433 | u16 reg_addr, u16 phy_data) |
| 434 | { |
| 435 | return atl1c_write_phy_core(hw, true, dev_addr, reg_addr, phy_data); |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 436 | } |
| 437 | |
Huang, Xiong | ce5b972 | 2012-04-25 20:27:14 +0000 | [diff] [blame] | 438 | int atl1c_read_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 *phy_data) |
| 439 | { |
| 440 | int err; |
| 441 | |
| 442 | err = atl1c_write_phy_reg(hw, MII_DBG_ADDR, reg_addr); |
| 443 | if (unlikely(err)) |
| 444 | return err; |
| 445 | else |
| 446 | err = atl1c_read_phy_reg(hw, MII_DBG_DATA, phy_data); |
| 447 | |
| 448 | return err; |
| 449 | } |
| 450 | |
| 451 | int atl1c_write_phy_dbg(struct atl1c_hw *hw, u16 reg_addr, u16 phy_data) |
| 452 | { |
| 453 | int err; |
| 454 | |
| 455 | err = atl1c_write_phy_reg(hw, MII_DBG_ADDR, reg_addr); |
| 456 | if (unlikely(err)) |
| 457 | return err; |
| 458 | else |
| 459 | err = atl1c_write_phy_reg(hw, MII_DBG_DATA, phy_data); |
| 460 | |
| 461 | return err; |
| 462 | } |
| 463 | |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 464 | /* |
| 465 | * Configures PHY autoneg and flow control advertisement settings |
| 466 | * |
| 467 | * hw - Struct containing variables accessed by shared code |
| 468 | */ |
| 469 | static int atl1c_phy_setup_adv(struct atl1c_hw *hw) |
| 470 | { |
françois romieu | 34aac66 | 2011-01-20 04:59:06 +0000 | [diff] [blame] | 471 | u16 mii_adv_data = ADVERTISE_DEFAULT_CAP & ~ADVERTISE_ALL; |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 472 | u16 mii_giga_ctrl_data = GIGA_CR_1000T_DEFAULT_CAP & |
| 473 | ~GIGA_CR_1000T_SPEED_MASK; |
| 474 | |
| 475 | if (hw->autoneg_advertised & ADVERTISED_10baseT_Half) |
| 476 | mii_adv_data |= ADVERTISE_10HALF; |
| 477 | if (hw->autoneg_advertised & ADVERTISED_10baseT_Full) |
| 478 | mii_adv_data |= ADVERTISE_10FULL; |
| 479 | if (hw->autoneg_advertised & ADVERTISED_100baseT_Half) |
| 480 | mii_adv_data |= ADVERTISE_100HALF; |
| 481 | if (hw->autoneg_advertised & ADVERTISED_100baseT_Full) |
| 482 | mii_adv_data |= ADVERTISE_100FULL; |
| 483 | |
| 484 | if (hw->autoneg_advertised & ADVERTISED_Autoneg) |
| 485 | mii_adv_data |= ADVERTISE_10HALF | ADVERTISE_10FULL | |
| 486 | ADVERTISE_100HALF | ADVERTISE_100FULL; |
| 487 | |
Luis R. Rodriguez | 496c185 | 2010-02-16 15:16:45 -0800 | [diff] [blame] | 488 | if (hw->link_cap_flags & ATL1C_LINK_CAP_1000M) { |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 489 | if (hw->autoneg_advertised & ADVERTISED_1000baseT_Half) |
| 490 | mii_giga_ctrl_data |= ADVERTISE_1000HALF; |
| 491 | if (hw->autoneg_advertised & ADVERTISED_1000baseT_Full) |
| 492 | mii_giga_ctrl_data |= ADVERTISE_1000FULL; |
| 493 | if (hw->autoneg_advertised & ADVERTISED_Autoneg) |
| 494 | mii_giga_ctrl_data |= ADVERTISE_1000HALF | |
| 495 | ADVERTISE_1000FULL; |
| 496 | } |
| 497 | |
| 498 | if (atl1c_write_phy_reg(hw, MII_ADVERTISE, mii_adv_data) != 0 || |
françois romieu | 34aac66 | 2011-01-20 04:59:06 +0000 | [diff] [blame] | 499 | atl1c_write_phy_reg(hw, MII_CTRL1000, mii_giga_ctrl_data) != 0) |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 500 | return -1; |
| 501 | return 0; |
| 502 | } |
| 503 | |
| 504 | void atl1c_phy_disable(struct atl1c_hw *hw) |
| 505 | { |
Huang, Xiong | 319d013 | 2012-04-25 20:40:59 +0000 | [diff] [blame] | 506 | atl1c_power_saving(hw, 0); |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 507 | } |
| 508 | |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 509 | |
| 510 | int atl1c_phy_reset(struct atl1c_hw *hw) |
| 511 | { |
| 512 | struct atl1c_adapter *adapter = hw->adapter; |
| 513 | struct pci_dev *pdev = adapter->pdev; |
Luis R. Rodriguez | 496c185 | 2010-02-16 15:16:45 -0800 | [diff] [blame] | 514 | u16 phy_data; |
Huang, Xiong | ce5b972 | 2012-04-25 20:27:14 +0000 | [diff] [blame] | 515 | u32 phy_ctrl_data, lpi_ctrl; |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 516 | int err; |
| 517 | |
Huang, Xiong | ce5b972 | 2012-04-25 20:27:14 +0000 | [diff] [blame] | 518 | /* reset PHY core */ |
| 519 | AT_READ_REG(hw, REG_GPHY_CTRL, &phy_ctrl_data); |
| 520 | phy_ctrl_data &= ~(GPHY_CTRL_EXT_RESET | GPHY_CTRL_PHY_IDDQ | |
| 521 | GPHY_CTRL_GATE_25M_EN | GPHY_CTRL_PWDOWN_HW | GPHY_CTRL_CLS); |
| 522 | phy_ctrl_data |= GPHY_CTRL_SEL_ANA_RST; |
| 523 | if (!(hw->ctrl_flags & ATL1C_HIB_DISABLE)) |
| 524 | phy_ctrl_data |= (GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE); |
| 525 | else |
| 526 | phy_ctrl_data &= ~(GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE); |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 527 | AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data); |
| 528 | AT_WRITE_FLUSH(hw); |
Huang, Xiong | ce5b972 | 2012-04-25 20:27:14 +0000 | [diff] [blame] | 529 | udelay(10); |
| 530 | AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl_data | GPHY_CTRL_EXT_RESET); |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 531 | AT_WRITE_FLUSH(hw); |
Huang, Xiong | ce5b972 | 2012-04-25 20:27:14 +0000 | [diff] [blame] | 532 | udelay(10 * GPHY_CTRL_EXT_RST_TO); /* delay 800us */ |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 533 | |
Huang, Xiong | ce5b972 | 2012-04-25 20:27:14 +0000 | [diff] [blame] | 534 | /* switch clock */ |
Luis R. Rodriguez | 496c185 | 2010-02-16 15:16:45 -0800 | [diff] [blame] | 535 | if (hw->nic_type == athr_l2c_b) { |
Huang, Xiong | ce5b972 | 2012-04-25 20:27:14 +0000 | [diff] [blame] | 536 | atl1c_read_phy_dbg(hw, MIIDBG_CFGLPSPD, &phy_data); |
| 537 | atl1c_write_phy_dbg(hw, MIIDBG_CFGLPSPD, |
| 538 | phy_data & ~CFGLPSPD_RSTCNT_CLK125SW); |
Luis R. Rodriguez | 496c185 | 2010-02-16 15:16:45 -0800 | [diff] [blame] | 539 | } |
| 540 | |
Huang, Xiong | ce5b972 | 2012-04-25 20:27:14 +0000 | [diff] [blame] | 541 | /* tx-half amplitude issue fix */ |
| 542 | if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2) { |
| 543 | atl1c_read_phy_dbg(hw, MIIDBG_CABLE1TH_DET, &phy_data); |
| 544 | phy_data |= CABLE1TH_DET_EN; |
| 545 | atl1c_write_phy_dbg(hw, MIIDBG_CABLE1TH_DET, phy_data); |
Luis R. Rodriguez | 496c185 | 2010-02-16 15:16:45 -0800 | [diff] [blame] | 546 | } |
Huang, Xiong | ce5b972 | 2012-04-25 20:27:14 +0000 | [diff] [blame] | 547 | |
| 548 | /* clear bit3 of dbgport 3B to lower voltage */ |
| 549 | if (!(hw->ctrl_flags & ATL1C_HIB_DISABLE)) { |
| 550 | if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2) { |
| 551 | atl1c_read_phy_dbg(hw, MIIDBG_VOLT_CTRL, &phy_data); |
| 552 | phy_data &= ~VOLT_CTRL_SWLOWEST; |
| 553 | atl1c_write_phy_dbg(hw, MIIDBG_VOLT_CTRL, phy_data); |
| 554 | } |
| 555 | /* power saving config */ |
| 556 | phy_data = |
| 557 | hw->nic_type == athr_l1d || hw->nic_type == athr_l1d_2 ? |
| 558 | L1D_LEGCYPS_DEF : L1C_LEGCYPS_DEF; |
| 559 | atl1c_write_phy_dbg(hw, MIIDBG_LEGCYPS, phy_data); |
| 560 | /* hib */ |
| 561 | atl1c_write_phy_dbg(hw, MIIDBG_SYSMODCTRL, |
| 562 | SYSMODCTRL_IECHOADJ_DEF); |
| 563 | } else { |
| 564 | /* disable pws */ |
| 565 | atl1c_read_phy_dbg(hw, MIIDBG_LEGCYPS, &phy_data); |
| 566 | atl1c_write_phy_dbg(hw, MIIDBG_LEGCYPS, |
| 567 | phy_data & ~LEGCYPS_EN); |
| 568 | /* disable hibernate */ |
| 569 | atl1c_read_phy_dbg(hw, MIIDBG_HIBNEG, &phy_data); |
| 570 | atl1c_write_phy_dbg(hw, MIIDBG_HIBNEG, |
| 571 | phy_data & HIBNEG_PSHIB_EN); |
Jie Yang | 8f574b3 | 2010-06-01 00:28:12 -0700 | [diff] [blame] | 572 | } |
Huang, Xiong | ce5b972 | 2012-04-25 20:27:14 +0000 | [diff] [blame] | 573 | /* disable AZ(EEE) by default */ |
| 574 | if (hw->nic_type == athr_l1d || hw->nic_type == athr_l1d_2 || |
| 575 | hw->nic_type == athr_l2c_b2) { |
| 576 | AT_READ_REG(hw, REG_LPI_CTRL, &lpi_ctrl); |
| 577 | AT_WRITE_REG(hw, REG_LPI_CTRL, lpi_ctrl & ~LPI_CTRL_EN); |
| 578 | atl1c_write_phy_ext(hw, MIIEXT_ANEG, MIIEXT_LOCAL_EEEADV, 0); |
| 579 | atl1c_write_phy_ext(hw, MIIEXT_PCS, MIIEXT_CLDCTRL3, |
| 580 | L2CB_CLDCTRL3); |
Jie Yang | 8f574b3 | 2010-06-01 00:28:12 -0700 | [diff] [blame] | 581 | } |
Huang, Xiong | ce5b972 | 2012-04-25 20:27:14 +0000 | [diff] [blame] | 582 | |
| 583 | /* other debug port to set */ |
| 584 | atl1c_write_phy_dbg(hw, MIIDBG_ANACTRL, ANACTRL_DEF); |
| 585 | atl1c_write_phy_dbg(hw, MIIDBG_SRDSYSMOD, SRDSYSMOD_DEF); |
| 586 | atl1c_write_phy_dbg(hw, MIIDBG_TST10BTCFG, TST10BTCFG_DEF); |
| 587 | /* UNH-IOL test issue, set bit7 */ |
| 588 | atl1c_write_phy_dbg(hw, MIIDBG_TST100BTCFG, |
| 589 | TST100BTCFG_DEF | TST100BTCFG_LITCH_EN); |
| 590 | |
| 591 | /* set phy interrupt mask */ |
| 592 | phy_data = IER_LINK_UP | IER_LINK_DOWN; |
| 593 | err = atl1c_write_phy_reg(hw, MII_IER, phy_data); |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 594 | if (err) { |
| 595 | if (netif_msg_hw(adapter)) |
| 596 | dev_err(&pdev->dev, |
| 597 | "Error enable PHY linkChange Interrupt\n"); |
| 598 | return err; |
| 599 | } |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 600 | return 0; |
| 601 | } |
| 602 | |
| 603 | int atl1c_phy_init(struct atl1c_hw *hw) |
| 604 | { |
Joe Perches | 6469933 | 2012-06-04 12:44:16 +0000 | [diff] [blame] | 605 | struct atl1c_adapter *adapter = hw->adapter; |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 606 | struct pci_dev *pdev = adapter->pdev; |
| 607 | int ret_val; |
| 608 | u16 mii_bmcr_data = BMCR_RESET; |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 609 | |
Jie Yang | 8f574b3 | 2010-06-01 00:28:12 -0700 | [diff] [blame] | 610 | if ((atl1c_read_phy_reg(hw, MII_PHYSID1, &hw->phy_id1) != 0) || |
| 611 | (atl1c_read_phy_reg(hw, MII_PHYSID2, &hw->phy_id2) != 0)) { |
| 612 | dev_err(&pdev->dev, "Error get phy ID\n"); |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 613 | return -1; |
| 614 | } |
| 615 | switch (hw->media_type) { |
| 616 | case MEDIA_TYPE_AUTO_SENSOR: |
| 617 | ret_val = atl1c_phy_setup_adv(hw); |
| 618 | if (ret_val) { |
| 619 | if (netif_msg_link(adapter)) |
| 620 | dev_err(&pdev->dev, |
| 621 | "Error Setting up Auto-Negotiation\n"); |
| 622 | return ret_val; |
| 623 | } |
françois romieu | 34aac66 | 2011-01-20 04:59:06 +0000 | [diff] [blame] | 624 | mii_bmcr_data |= BMCR_ANENABLE | BMCR_ANRESTART; |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 625 | break; |
| 626 | case MEDIA_TYPE_100M_FULL: |
françois romieu | 34aac66 | 2011-01-20 04:59:06 +0000 | [diff] [blame] | 627 | mii_bmcr_data |= BMCR_SPEED100 | BMCR_FULLDPLX; |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 628 | break; |
| 629 | case MEDIA_TYPE_100M_HALF: |
françois romieu | 34aac66 | 2011-01-20 04:59:06 +0000 | [diff] [blame] | 630 | mii_bmcr_data |= BMCR_SPEED100; |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 631 | break; |
| 632 | case MEDIA_TYPE_10M_FULL: |
françois romieu | 34aac66 | 2011-01-20 04:59:06 +0000 | [diff] [blame] | 633 | mii_bmcr_data |= BMCR_FULLDPLX; |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 634 | break; |
| 635 | case MEDIA_TYPE_10M_HALF: |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 636 | break; |
| 637 | default: |
| 638 | if (netif_msg_link(adapter)) |
| 639 | dev_err(&pdev->dev, "Wrong Media type %d\n", |
| 640 | hw->media_type); |
| 641 | return -1; |
| 642 | break; |
| 643 | } |
| 644 | |
| 645 | ret_val = atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data); |
| 646 | if (ret_val) |
| 647 | return ret_val; |
| 648 | hw->phy_configured = true; |
| 649 | |
| 650 | return 0; |
| 651 | } |
| 652 | |
| 653 | /* |
| 654 | * Detects the current speed and duplex settings of the hardware. |
| 655 | * |
| 656 | * hw - Struct containing variables accessed by shared code |
| 657 | * speed - Speed of the connection |
| 658 | * duplex - Duplex setting of the connection |
| 659 | */ |
| 660 | int atl1c_get_speed_and_duplex(struct atl1c_hw *hw, u16 *speed, u16 *duplex) |
| 661 | { |
| 662 | int err; |
| 663 | u16 phy_data; |
| 664 | |
| 665 | /* Read PHY Specific Status Register (17) */ |
| 666 | err = atl1c_read_phy_reg(hw, MII_GIGA_PSSR, &phy_data); |
| 667 | if (err) |
| 668 | return err; |
| 669 | |
| 670 | if (!(phy_data & GIGA_PSSR_SPD_DPLX_RESOLVED)) |
| 671 | return -1; |
| 672 | |
| 673 | switch (phy_data & GIGA_PSSR_SPEED) { |
| 674 | case GIGA_PSSR_1000MBS: |
| 675 | *speed = SPEED_1000; |
| 676 | break; |
| 677 | case GIGA_PSSR_100MBS: |
| 678 | *speed = SPEED_100; |
| 679 | break; |
| 680 | case GIGA_PSSR_10MBS: |
| 681 | *speed = SPEED_10; |
| 682 | break; |
| 683 | default: |
| 684 | return -1; |
| 685 | break; |
| 686 | } |
| 687 | |
| 688 | if (phy_data & GIGA_PSSR_DPLX) |
| 689 | *duplex = FULL_DUPLEX; |
| 690 | else |
| 691 | *duplex = HALF_DUPLEX; |
| 692 | |
| 693 | return 0; |
| 694 | } |
| 695 | |
Huang, Xiong | 319d013 | 2012-04-25 20:40:59 +0000 | [diff] [blame] | 696 | /* select one link mode to get lower power consumption */ |
| 697 | int atl1c_phy_to_ps_link(struct atl1c_hw *hw) |
Jie Yang | 8f574b3 | 2010-06-01 00:28:12 -0700 | [diff] [blame] | 698 | { |
Joe Perches | 6469933 | 2012-06-04 12:44:16 +0000 | [diff] [blame] | 699 | struct atl1c_adapter *adapter = hw->adapter; |
Jie Yang | 8f574b3 | 2010-06-01 00:28:12 -0700 | [diff] [blame] | 700 | struct pci_dev *pdev = adapter->pdev; |
| 701 | int ret = 0; |
| 702 | u16 autoneg_advertised = ADVERTISED_10baseT_Half; |
| 703 | u16 save_autoneg_advertised; |
| 704 | u16 phy_data; |
| 705 | u16 mii_lpa_data; |
| 706 | u16 speed = SPEED_0; |
| 707 | u16 duplex = FULL_DUPLEX; |
| 708 | int i; |
| 709 | |
| 710 | atl1c_read_phy_reg(hw, MII_BMSR, &phy_data); |
| 711 | atl1c_read_phy_reg(hw, MII_BMSR, &phy_data); |
| 712 | if (phy_data & BMSR_LSTATUS) { |
| 713 | atl1c_read_phy_reg(hw, MII_LPA, &mii_lpa_data); |
| 714 | if (mii_lpa_data & LPA_10FULL) |
| 715 | autoneg_advertised = ADVERTISED_10baseT_Full; |
| 716 | else if (mii_lpa_data & LPA_10HALF) |
| 717 | autoneg_advertised = ADVERTISED_10baseT_Half; |
| 718 | else if (mii_lpa_data & LPA_100HALF) |
| 719 | autoneg_advertised = ADVERTISED_100baseT_Half; |
| 720 | else if (mii_lpa_data & LPA_100FULL) |
| 721 | autoneg_advertised = ADVERTISED_100baseT_Full; |
| 722 | |
| 723 | save_autoneg_advertised = hw->autoneg_advertised; |
| 724 | hw->phy_configured = false; |
| 725 | hw->autoneg_advertised = autoneg_advertised; |
| 726 | if (atl1c_restart_autoneg(hw) != 0) { |
| 727 | dev_dbg(&pdev->dev, "phy autoneg failed\n"); |
| 728 | ret = -1; |
| 729 | } |
| 730 | hw->autoneg_advertised = save_autoneg_advertised; |
| 731 | |
| 732 | if (mii_lpa_data) { |
| 733 | for (i = 0; i < AT_SUSPEND_LINK_TIMEOUT; i++) { |
| 734 | mdelay(100); |
| 735 | atl1c_read_phy_reg(hw, MII_BMSR, &phy_data); |
| 736 | atl1c_read_phy_reg(hw, MII_BMSR, &phy_data); |
| 737 | if (phy_data & BMSR_LSTATUS) { |
| 738 | if (atl1c_get_speed_and_duplex(hw, &speed, |
| 739 | &duplex) != 0) |
| 740 | dev_dbg(&pdev->dev, |
| 741 | "get speed and duplex failed\n"); |
| 742 | break; |
| 743 | } |
| 744 | } |
| 745 | } |
| 746 | } else { |
| 747 | speed = SPEED_10; |
| 748 | duplex = HALF_DUPLEX; |
| 749 | } |
| 750 | adapter->link_speed = speed; |
| 751 | adapter->link_duplex = duplex; |
| 752 | |
| 753 | return ret; |
| 754 | } |
| 755 | |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 756 | int atl1c_restart_autoneg(struct atl1c_hw *hw) |
| 757 | { |
| 758 | int err = 0; |
| 759 | u16 mii_bmcr_data = BMCR_RESET; |
| 760 | |
| 761 | err = atl1c_phy_setup_adv(hw); |
| 762 | if (err) |
| 763 | return err; |
françois romieu | 34aac66 | 2011-01-20 04:59:06 +0000 | [diff] [blame] | 764 | mii_bmcr_data |= BMCR_ANENABLE | BMCR_ANRESTART; |
Jie Yang | 43250dd | 2009-02-18 17:24:15 -0800 | [diff] [blame] | 765 | |
| 766 | return atl1c_write_phy_reg(hw, MII_BMCR, mii_bmcr_data); |
| 767 | } |
Huang, Xiong | 319d013 | 2012-04-25 20:40:59 +0000 | [diff] [blame] | 768 | |
| 769 | int atl1c_power_saving(struct atl1c_hw *hw, u32 wufc) |
| 770 | { |
Joe Perches | 6469933 | 2012-06-04 12:44:16 +0000 | [diff] [blame] | 771 | struct atl1c_adapter *adapter = hw->adapter; |
Huang, Xiong | 319d013 | 2012-04-25 20:40:59 +0000 | [diff] [blame] | 772 | struct pci_dev *pdev = adapter->pdev; |
| 773 | u32 master_ctrl, mac_ctrl, phy_ctrl; |
| 774 | u32 wol_ctrl, speed; |
| 775 | u16 phy_data; |
| 776 | |
| 777 | wol_ctrl = 0; |
| 778 | speed = adapter->link_speed == SPEED_1000 ? |
| 779 | MAC_CTRL_SPEED_1000 : MAC_CTRL_SPEED_10_100; |
| 780 | |
| 781 | AT_READ_REG(hw, REG_MASTER_CTRL, &master_ctrl); |
| 782 | AT_READ_REG(hw, REG_MAC_CTRL, &mac_ctrl); |
| 783 | AT_READ_REG(hw, REG_GPHY_CTRL, &phy_ctrl); |
| 784 | |
| 785 | master_ctrl &= ~MASTER_CTRL_CLK_SEL_DIS; |
| 786 | mac_ctrl = FIELD_SETX(mac_ctrl, MAC_CTRL_SPEED, speed); |
| 787 | mac_ctrl &= ~(MAC_CTRL_DUPLX | MAC_CTRL_RX_EN | MAC_CTRL_TX_EN); |
| 788 | if (adapter->link_duplex == FULL_DUPLEX) |
| 789 | mac_ctrl |= MAC_CTRL_DUPLX; |
| 790 | phy_ctrl &= ~(GPHY_CTRL_EXT_RESET | GPHY_CTRL_CLS); |
| 791 | phy_ctrl |= GPHY_CTRL_SEL_ANA_RST | GPHY_CTRL_HIB_PULSE | |
| 792 | GPHY_CTRL_HIB_EN; |
| 793 | if (!wufc) { /* without WoL */ |
| 794 | master_ctrl |= MASTER_CTRL_CLK_SEL_DIS; |
| 795 | phy_ctrl |= GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PWDOWN_HW; |
| 796 | AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl); |
| 797 | AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl); |
| 798 | AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl); |
| 799 | AT_WRITE_REG(hw, REG_WOL_CTRL, 0); |
| 800 | hw->phy_configured = false; /* re-init PHY when resume */ |
| 801 | return 0; |
| 802 | } |
| 803 | phy_ctrl |= GPHY_CTRL_EXT_RESET; |
| 804 | if (wufc & AT_WUFC_MAG) { |
| 805 | mac_ctrl |= MAC_CTRL_RX_EN | MAC_CTRL_BC_EN; |
| 806 | wol_ctrl |= WOL_MAGIC_EN | WOL_MAGIC_PME_EN; |
| 807 | if (hw->nic_type == athr_l2c_b && hw->revision_id == L2CB_V11) |
| 808 | wol_ctrl |= WOL_PATTERN_EN | WOL_PATTERN_PME_EN; |
| 809 | } |
| 810 | if (wufc & AT_WUFC_LNKC) { |
| 811 | wol_ctrl |= WOL_LINK_CHG_EN | WOL_LINK_CHG_PME_EN; |
| 812 | if (atl1c_write_phy_reg(hw, MII_IER, IER_LINK_UP) != 0) { |
| 813 | dev_dbg(&pdev->dev, "%s: write phy MII_IER faild.\n", |
| 814 | atl1c_driver_name); |
| 815 | } |
| 816 | } |
| 817 | /* clear PHY interrupt */ |
| 818 | atl1c_read_phy_reg(hw, MII_ISR, &phy_data); |
| 819 | |
| 820 | dev_dbg(&pdev->dev, "%s: suspend MAC=%x,MASTER=%x,PHY=0x%x,WOL=%x\n", |
| 821 | atl1c_driver_name, mac_ctrl, master_ctrl, phy_ctrl, wol_ctrl); |
| 822 | AT_WRITE_REG(hw, REG_MASTER_CTRL, master_ctrl); |
| 823 | AT_WRITE_REG(hw, REG_MAC_CTRL, mac_ctrl); |
| 824 | AT_WRITE_REG(hw, REG_GPHY_CTRL, phy_ctrl); |
| 825 | AT_WRITE_REG(hw, REG_WOL_CTRL, wol_ctrl); |
| 826 | |
| 827 | return 0; |
| 828 | } |
Huang, Xiong | 903d7ce | 2012-04-30 15:38:50 +0000 | [diff] [blame] | 829 | |
| 830 | |
| 831 | /* configure phy after Link change Event */ |
| 832 | void atl1c_post_phy_linkchg(struct atl1c_hw *hw, u16 link_speed) |
| 833 | { |
| 834 | u16 phy_val; |
| 835 | bool adj_thresh = false; |
| 836 | |
| 837 | if (hw->nic_type == athr_l2c_b || hw->nic_type == athr_l2c_b2 || |
| 838 | hw->nic_type == athr_l1d || hw->nic_type == athr_l1d_2) |
| 839 | adj_thresh = true; |
| 840 | |
| 841 | if (link_speed != SPEED_0) { /* link up */ |
| 842 | /* az with brcm, half-amp */ |
| 843 | if (hw->nic_type == athr_l1d_2) { |
| 844 | atl1c_read_phy_ext(hw, MIIEXT_PCS, MIIEXT_CLDCTRL6, |
| 845 | &phy_val); |
| 846 | phy_val = FIELD_GETX(phy_val, CLDCTRL6_CAB_LEN); |
| 847 | phy_val = phy_val > CLDCTRL6_CAB_LEN_SHORT ? |
| 848 | AZ_ANADECT_LONG : AZ_ANADECT_DEF; |
| 849 | atl1c_write_phy_dbg(hw, MIIDBG_AZ_ANADECT, phy_val); |
| 850 | } |
| 851 | /* threshold adjust */ |
| 852 | if (adj_thresh && link_speed == SPEED_100 && hw->msi_lnkpatch) { |
| 853 | atl1c_write_phy_dbg(hw, MIIDBG_MSE16DB, L1D_MSE16DB_UP); |
| 854 | atl1c_write_phy_dbg(hw, MIIDBG_SYSMODCTRL, |
| 855 | L1D_SYSMODCTRL_IECHOADJ_DEF); |
| 856 | } |
| 857 | } else { /* link down */ |
| 858 | if (adj_thresh && hw->msi_lnkpatch) { |
| 859 | atl1c_write_phy_dbg(hw, MIIDBG_SYSMODCTRL, |
| 860 | SYSMODCTRL_IECHOADJ_DEF); |
| 861 | atl1c_write_phy_dbg(hw, MIIDBG_MSE16DB, |
| 862 | L1D_MSE16DB_DOWN); |
| 863 | } |
| 864 | } |
| 865 | } |