Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 1 | /******************************************************************************* |
| 2 | |
| 3 | Intel 10 Gigabit PCI Express Linux driver |
Don Skidmore | 9497182 | 2012-01-06 03:24:16 +0000 | [diff] [blame] | 4 | Copyright(c) 1999 - 2012 Intel Corporation. |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 5 | |
| 6 | This program is free software; you can redistribute it and/or modify it |
| 7 | under the terms and conditions of the GNU General Public License, |
| 8 | version 2, as published by the Free Software Foundation. |
| 9 | |
| 10 | This program is distributed in the hope it will be useful, but WITHOUT |
| 11 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 12 | FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 13 | more details. |
| 14 | |
| 15 | You should have received a copy of the GNU General Public License along with |
| 16 | this program; if not, write to the Free Software Foundation, Inc., |
| 17 | 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. |
| 18 | |
| 19 | The full GNU General Public License is included in this distribution in |
| 20 | the file called "COPYING". |
| 21 | |
| 22 | Contact Information: |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 23 | e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> |
| 24 | Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 |
| 25 | |
| 26 | *******************************************************************************/ |
| 27 | |
| 28 | #include <linux/pci.h> |
| 29 | #include <linux/delay.h> |
| 30 | #include <linux/sched.h> |
| 31 | |
| 32 | #include "ixgbe_common.h" |
| 33 | #include "ixgbe_phy.h" |
| 34 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 35 | static void ixgbe_i2c_start(struct ixgbe_hw *hw); |
| 36 | static void ixgbe_i2c_stop(struct ixgbe_hw *hw); |
| 37 | static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); |
| 38 | static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); |
| 39 | static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); |
| 40 | static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); |
| 41 | static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); |
Emil Tantilov | e1befd7 | 2011-08-27 07:18:47 +0000 | [diff] [blame] | 42 | static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 43 | static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); |
| 44 | static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); |
| 45 | static bool ixgbe_get_i2c_data(u32 *i2cctl); |
| 46 | static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 47 | static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id); |
| 48 | static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 49 | |
| 50 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 51 | * ixgbe_identify_phy_generic - Get physical layer module |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 52 | * @hw: pointer to hardware structure |
| 53 | * |
| 54 | * Determines the physical layer module found on the current adapter. |
| 55 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 56 | s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 57 | { |
| 58 | s32 status = IXGBE_ERR_PHY_ADDR_INVALID; |
| 59 | u32 phy_addr; |
Emil Tantilov | 037c6d0 | 2011-02-25 07:49:39 +0000 | [diff] [blame] | 60 | u16 ext_ability = 0; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 61 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 62 | if (hw->phy.type == ixgbe_phy_unknown) { |
| 63 | for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { |
Don Skidmore | 63d6e1d | 2009-07-02 12:50:12 +0000 | [diff] [blame] | 64 | hw->phy.mdio.prtad = phy_addr; |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 65 | if (mdio45_probe(&hw->phy.mdio, phy_addr) == 0) { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 66 | ixgbe_get_phy_id(hw); |
| 67 | hw->phy.type = |
| 68 | ixgbe_get_phy_type_from_id(hw->phy.id); |
Emil Tantilov | 037c6d0 | 2011-02-25 07:49:39 +0000 | [diff] [blame] | 69 | |
| 70 | if (hw->phy.type == ixgbe_phy_unknown) { |
| 71 | hw->phy.ops.read_reg(hw, |
| 72 | MDIO_PMA_EXTABLE, |
| 73 | MDIO_MMD_PMAPMD, |
| 74 | &ext_ability); |
| 75 | if (ext_ability & |
| 76 | (MDIO_PMA_EXTABLE_10GBT | |
| 77 | MDIO_PMA_EXTABLE_1000BT)) |
| 78 | hw->phy.type = |
| 79 | ixgbe_phy_cu_unknown; |
| 80 | else |
| 81 | hw->phy.type = |
| 82 | ixgbe_phy_generic; |
| 83 | } |
| 84 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 85 | status = 0; |
| 86 | break; |
| 87 | } |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 88 | } |
Don Skidmore | 63d6e1d | 2009-07-02 12:50:12 +0000 | [diff] [blame] | 89 | /* clear value if nothing found */ |
Emil Tantilov | 037c6d0 | 2011-02-25 07:49:39 +0000 | [diff] [blame] | 90 | if (status != 0) |
| 91 | hw->phy.mdio.prtad = 0; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 92 | } else { |
| 93 | status = 0; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 94 | } |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 95 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 96 | return status; |
| 97 | } |
| 98 | |
| 99 | /** |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 100 | * ixgbe_get_phy_id - Get the phy type |
| 101 | * @hw: pointer to hardware structure |
| 102 | * |
| 103 | **/ |
| 104 | static s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) |
| 105 | { |
| 106 | u32 status; |
| 107 | u16 phy_id_high = 0; |
| 108 | u16 phy_id_low = 0; |
| 109 | |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 110 | status = hw->phy.ops.read_reg(hw, MDIO_DEVID1, MDIO_MMD_PMAPMD, |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 111 | &phy_id_high); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 112 | |
| 113 | if (status == 0) { |
| 114 | hw->phy.id = (u32)(phy_id_high << 16); |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 115 | status = hw->phy.ops.read_reg(hw, MDIO_DEVID2, MDIO_MMD_PMAPMD, |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 116 | &phy_id_low); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 117 | hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); |
| 118 | hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); |
| 119 | } |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 120 | return status; |
| 121 | } |
| 122 | |
| 123 | /** |
| 124 | * ixgbe_get_phy_type_from_id - Get the phy type |
| 125 | * @hw: pointer to hardware structure |
| 126 | * |
| 127 | **/ |
| 128 | static enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) |
| 129 | { |
| 130 | enum ixgbe_phy_type phy_type; |
| 131 | |
| 132 | switch (phy_id) { |
Jesse Brandeburg | 0befdb3 | 2008-10-31 00:46:40 -0700 | [diff] [blame] | 133 | case TN1010_PHY_ID: |
| 134 | phy_type = ixgbe_phy_tn; |
| 135 | break; |
Don Skidmore | 2b26490 | 2010-12-09 06:55:14 +0000 | [diff] [blame] | 136 | case X540_PHY_ID: |
Don Skidmore | fe15e8e | 2010-11-16 19:27:16 -0800 | [diff] [blame] | 137 | phy_type = ixgbe_phy_aq; |
| 138 | break; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 139 | case QT2022_PHY_ID: |
| 140 | phy_type = ixgbe_phy_qt; |
| 141 | break; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 142 | case ATH_PHY_ID: |
| 143 | phy_type = ixgbe_phy_nl; |
| 144 | break; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 145 | default: |
| 146 | phy_type = ixgbe_phy_unknown; |
| 147 | break; |
| 148 | } |
| 149 | |
| 150 | return phy_type; |
| 151 | } |
| 152 | |
| 153 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 154 | * ixgbe_reset_phy_generic - Performs a PHY reset |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 155 | * @hw: pointer to hardware structure |
| 156 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 157 | s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 158 | { |
Emil Tantilov | 1783575 | 2011-02-16 01:38:13 +0000 | [diff] [blame] | 159 | u32 i; |
| 160 | u16 ctrl = 0; |
| 161 | s32 status = 0; |
| 162 | |
| 163 | if (hw->phy.type == ixgbe_phy_unknown) |
| 164 | status = ixgbe_identify_phy_generic(hw); |
| 165 | |
| 166 | if (status != 0 || hw->phy.type == ixgbe_phy_none) |
| 167 | goto out; |
| 168 | |
Mallikarjuna R Chilakala | 119fc60 | 2010-05-20 23:07:06 -0700 | [diff] [blame] | 169 | /* Don't reset PHY if it's shut down due to overtemp. */ |
| 170 | if (!hw->phy.reset_if_overtemp && |
| 171 | (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) |
Emil Tantilov | 1783575 | 2011-02-16 01:38:13 +0000 | [diff] [blame] | 172 | goto out; |
Mallikarjuna R Chilakala | 119fc60 | 2010-05-20 23:07:06 -0700 | [diff] [blame] | 173 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 174 | /* |
| 175 | * Perform soft PHY reset to the PHY_XS. |
| 176 | * This will cause a soft reset to the PHY |
| 177 | */ |
Emil Tantilov | 1783575 | 2011-02-16 01:38:13 +0000 | [diff] [blame] | 178 | hw->phy.ops.write_reg(hw, MDIO_CTRL1, |
| 179 | MDIO_MMD_PHYXS, |
| 180 | MDIO_CTRL1_RESET); |
| 181 | |
| 182 | /* |
| 183 | * Poll for reset bit to self-clear indicating reset is complete. |
| 184 | * Some PHYs could take up to 3 seconds to complete and need about |
| 185 | * 1.7 usec delay after the reset is complete. |
| 186 | */ |
| 187 | for (i = 0; i < 30; i++) { |
| 188 | msleep(100); |
| 189 | hw->phy.ops.read_reg(hw, MDIO_CTRL1, |
| 190 | MDIO_MMD_PHYXS, &ctrl); |
| 191 | if (!(ctrl & MDIO_CTRL1_RESET)) { |
| 192 | udelay(2); |
| 193 | break; |
| 194 | } |
| 195 | } |
| 196 | |
| 197 | if (ctrl & MDIO_CTRL1_RESET) { |
| 198 | status = IXGBE_ERR_RESET_FAILED; |
| 199 | hw_dbg(hw, "PHY reset polling failed to complete.\n"); |
| 200 | } |
| 201 | |
| 202 | out: |
| 203 | return status; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 204 | } |
| 205 | |
| 206 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 207 | * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 208 | * @hw: pointer to hardware structure |
| 209 | * @reg_addr: 32 bit address of PHY register to read |
| 210 | * @phy_data: Pointer to read data from PHY register |
| 211 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 212 | s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, |
| 213 | u32 device_type, u16 *phy_data) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 214 | { |
| 215 | u32 command; |
| 216 | u32 i; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 217 | u32 data; |
| 218 | s32 status = 0; |
| 219 | u16 gssr; |
| 220 | |
| 221 | if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) |
| 222 | gssr = IXGBE_GSSR_PHY1_SM; |
| 223 | else |
| 224 | gssr = IXGBE_GSSR_PHY0_SM; |
| 225 | |
Don Skidmore | 5e65510 | 2011-02-25 01:58:04 +0000 | [diff] [blame] | 226 | if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 227 | status = IXGBE_ERR_SWFW_SYNC; |
| 228 | |
| 229 | if (status == 0) { |
| 230 | /* Setup and write the address cycle command */ |
| 231 | command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 232 | (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 233 | (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 234 | (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 235 | |
| 236 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); |
| 237 | |
| 238 | /* |
| 239 | * Check every 10 usec to see if the address cycle completed. |
| 240 | * The MDI Command bit will clear when the operation is |
| 241 | * complete |
| 242 | */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 243 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 244 | udelay(10); |
| 245 | |
| 246 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); |
| 247 | |
| 248 | if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) |
| 249 | break; |
| 250 | } |
| 251 | |
| 252 | if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { |
| 253 | hw_dbg(hw, "PHY address command did not complete.\n"); |
| 254 | status = IXGBE_ERR_PHY; |
| 255 | } |
| 256 | |
| 257 | if (status == 0) { |
| 258 | /* |
| 259 | * Address cycle complete, setup and write the read |
| 260 | * command |
| 261 | */ |
| 262 | command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 263 | (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 264 | (hw->phy.mdio.prtad << |
| 265 | IXGBE_MSCA_PHY_ADDR_SHIFT) | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 266 | (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 267 | |
| 268 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); |
| 269 | |
| 270 | /* |
| 271 | * Check every 10 usec to see if the address cycle |
| 272 | * completed. The MDI Command bit will clear when the |
| 273 | * operation is complete |
| 274 | */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 275 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 276 | udelay(10); |
| 277 | |
| 278 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); |
| 279 | |
| 280 | if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) |
| 281 | break; |
| 282 | } |
| 283 | |
| 284 | if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 285 | hw_dbg(hw, "PHY read command didn't complete\n"); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 286 | status = IXGBE_ERR_PHY; |
| 287 | } else { |
| 288 | /* |
| 289 | * Read operation is complete. Get the data |
| 290 | * from MSRWD |
| 291 | */ |
| 292 | data = IXGBE_READ_REG(hw, IXGBE_MSRWD); |
| 293 | data >>= IXGBE_MSRWD_READ_DATA_SHIFT; |
| 294 | *phy_data = (u16)(data); |
| 295 | } |
| 296 | } |
| 297 | |
Don Skidmore | 5e65510 | 2011-02-25 01:58:04 +0000 | [diff] [blame] | 298 | hw->mac.ops.release_swfw_sync(hw, gssr); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 299 | } |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 300 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 301 | return status; |
| 302 | } |
| 303 | |
| 304 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 305 | * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 306 | * @hw: pointer to hardware structure |
| 307 | * @reg_addr: 32 bit PHY register to write |
| 308 | * @device_type: 5 bit device type |
| 309 | * @phy_data: Data to write to the PHY register |
| 310 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 311 | s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, |
| 312 | u32 device_type, u16 phy_data) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 313 | { |
| 314 | u32 command; |
| 315 | u32 i; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 316 | s32 status = 0; |
| 317 | u16 gssr; |
| 318 | |
| 319 | if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) |
| 320 | gssr = IXGBE_GSSR_PHY1_SM; |
| 321 | else |
| 322 | gssr = IXGBE_GSSR_PHY0_SM; |
| 323 | |
Don Skidmore | 5e65510 | 2011-02-25 01:58:04 +0000 | [diff] [blame] | 324 | if (hw->mac.ops.acquire_swfw_sync(hw, gssr) != 0) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 325 | status = IXGBE_ERR_SWFW_SYNC; |
| 326 | |
| 327 | if (status == 0) { |
| 328 | /* Put the data in the MDI single read and write data register*/ |
| 329 | IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); |
| 330 | |
| 331 | /* Setup and write the address cycle command */ |
| 332 | command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 333 | (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 334 | (hw->phy.mdio.prtad << IXGBE_MSCA_PHY_ADDR_SHIFT) | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 335 | (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 336 | |
| 337 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); |
| 338 | |
| 339 | /* |
| 340 | * Check every 10 usec to see if the address cycle completed. |
| 341 | * The MDI Command bit will clear when the operation is |
| 342 | * complete |
| 343 | */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 344 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 345 | udelay(10); |
| 346 | |
| 347 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); |
| 348 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 349 | if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 350 | break; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 351 | } |
| 352 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 353 | if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { |
| 354 | hw_dbg(hw, "PHY address cmd didn't complete\n"); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 355 | status = IXGBE_ERR_PHY; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 356 | } |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 357 | |
| 358 | if (status == 0) { |
| 359 | /* |
| 360 | * Address cycle complete, setup and write the write |
| 361 | * command |
| 362 | */ |
| 363 | command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 364 | (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 365 | (hw->phy.mdio.prtad << |
| 366 | IXGBE_MSCA_PHY_ADDR_SHIFT) | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 367 | (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 368 | |
| 369 | IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); |
| 370 | |
| 371 | /* |
| 372 | * Check every 10 usec to see if the address cycle |
| 373 | * completed. The MDI Command bit will clear when the |
| 374 | * operation is complete |
| 375 | */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 376 | for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 377 | udelay(10); |
| 378 | |
| 379 | command = IXGBE_READ_REG(hw, IXGBE_MSCA); |
| 380 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 381 | if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 382 | break; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 383 | } |
| 384 | |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 385 | if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { |
| 386 | hw_dbg(hw, "PHY address cmd didn't complete\n"); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 387 | status = IXGBE_ERR_PHY; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 388 | } |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 389 | } |
| 390 | |
Don Skidmore | 5e65510 | 2011-02-25 01:58:04 +0000 | [diff] [blame] | 391 | hw->mac.ops.release_swfw_sync(hw, gssr); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 392 | } |
| 393 | |
| 394 | return status; |
| 395 | } |
| 396 | |
| 397 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 398 | * ixgbe_setup_phy_link_generic - Set and restart autoneg |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 399 | * @hw: pointer to hardware structure |
| 400 | * |
| 401 | * Restart autonegotiation and PHY and waits for completion. |
| 402 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 403 | s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 404 | { |
Emil Tantilov | 9dda173 | 2011-03-05 01:28:07 +0000 | [diff] [blame] | 405 | s32 status = 0; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 406 | u32 time_out; |
| 407 | u32 max_time_out = 10; |
Emil Tantilov | 9dda173 | 2011-03-05 01:28:07 +0000 | [diff] [blame] | 408 | u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; |
| 409 | bool autoneg = false; |
| 410 | ixgbe_link_speed speed; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 411 | |
Emil Tantilov | 9dda173 | 2011-03-05 01:28:07 +0000 | [diff] [blame] | 412 | ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 413 | |
Emil Tantilov | 9dda173 | 2011-03-05 01:28:07 +0000 | [diff] [blame] | 414 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) { |
| 415 | /* Set or unset auto-negotiation 10G advertisement */ |
| 416 | hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, |
| 417 | MDIO_MMD_AN, |
| 418 | &autoneg_reg); |
| 419 | |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 420 | autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; |
Emil Tantilov | 9dda173 | 2011-03-05 01:28:07 +0000 | [diff] [blame] | 421 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) |
| 422 | autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 423 | |
Emil Tantilov | 9dda173 | 2011-03-05 01:28:07 +0000 | [diff] [blame] | 424 | hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, |
| 425 | MDIO_MMD_AN, |
| 426 | autoneg_reg); |
| 427 | } |
| 428 | |
| 429 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) { |
| 430 | /* Set or unset auto-negotiation 1G advertisement */ |
| 431 | hw->phy.ops.read_reg(hw, |
| 432 | IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, |
| 433 | MDIO_MMD_AN, |
| 434 | &autoneg_reg); |
| 435 | |
| 436 | autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; |
| 437 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) |
| 438 | autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; |
| 439 | |
| 440 | hw->phy.ops.write_reg(hw, |
| 441 | IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, |
| 442 | MDIO_MMD_AN, |
| 443 | autoneg_reg); |
| 444 | } |
| 445 | |
| 446 | if (speed & IXGBE_LINK_SPEED_100_FULL) { |
| 447 | /* Set or unset auto-negotiation 100M advertisement */ |
| 448 | hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, |
| 449 | MDIO_MMD_AN, |
| 450 | &autoneg_reg); |
| 451 | |
Emil Tantilov | a59e8a1 | 2011-03-31 09:36:12 +0000 | [diff] [blame] | 452 | autoneg_reg &= ~(ADVERTISE_100FULL | |
| 453 | ADVERTISE_100HALF); |
Emil Tantilov | 9dda173 | 2011-03-05 01:28:07 +0000 | [diff] [blame] | 454 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) |
| 455 | autoneg_reg |= ADVERTISE_100FULL; |
| 456 | |
| 457 | hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, |
| 458 | MDIO_MMD_AN, |
| 459 | autoneg_reg); |
| 460 | } |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 461 | |
| 462 | /* Restart PHY autonegotiation and wait for completion */ |
Emil Tantilov | 9dda173 | 2011-03-05 01:28:07 +0000 | [diff] [blame] | 463 | hw->phy.ops.read_reg(hw, MDIO_CTRL1, |
| 464 | MDIO_MMD_AN, &autoneg_reg); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 465 | |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 466 | autoneg_reg |= MDIO_AN_CTRL1_RESTART; |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 467 | |
Emil Tantilov | 9dda173 | 2011-03-05 01:28:07 +0000 | [diff] [blame] | 468 | hw->phy.ops.write_reg(hw, MDIO_CTRL1, |
| 469 | MDIO_MMD_AN, autoneg_reg); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 470 | |
| 471 | /* Wait for autonegotiation to finish */ |
| 472 | for (time_out = 0; time_out < max_time_out; time_out++) { |
| 473 | udelay(10); |
| 474 | /* Restart PHY autonegotiation and wait for completion */ |
Emil Tantilov | 9dda173 | 2011-03-05 01:28:07 +0000 | [diff] [blame] | 475 | status = hw->phy.ops.read_reg(hw, MDIO_STAT1, |
| 476 | MDIO_MMD_AN, |
| 477 | &autoneg_reg); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 478 | |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 479 | autoneg_reg &= MDIO_AN_STAT1_COMPLETE; |
| 480 | if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) { |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 481 | break; |
| 482 | } |
| 483 | } |
| 484 | |
Emil Tantilov | 9dda173 | 2011-03-05 01:28:07 +0000 | [diff] [blame] | 485 | if (time_out == max_time_out) { |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 486 | status = IXGBE_ERR_LINK_SETUP; |
Emil Tantilov | 9dda173 | 2011-03-05 01:28:07 +0000 | [diff] [blame] | 487 | hw_dbg(hw, "ixgbe_setup_phy_link_generic: time out"); |
| 488 | } |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 489 | |
| 490 | return status; |
| 491 | } |
| 492 | |
| 493 | /** |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 494 | * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 495 | * @hw: pointer to hardware structure |
| 496 | * @speed: new link speed |
| 497 | * @autoneg: true if autonegotiation enabled |
| 498 | **/ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 499 | s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, |
| 500 | ixgbe_link_speed speed, |
| 501 | bool autoneg, |
| 502 | bool autoneg_wait_to_complete) |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 503 | { |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 504 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 505 | /* |
| 506 | * Clear autoneg_advertised and set new values based on input link |
| 507 | * speed. |
| 508 | */ |
| 509 | hw->phy.autoneg_advertised = 0; |
| 510 | |
| 511 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) |
| 512 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 513 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 514 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) |
| 515 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; |
| 516 | |
Emil Tantilov | 9dda173 | 2011-03-05 01:28:07 +0000 | [diff] [blame] | 517 | if (speed & IXGBE_LINK_SPEED_100_FULL) |
| 518 | hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; |
| 519 | |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 520 | /* Setup link based on the new speed settings */ |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 521 | hw->phy.ops.setup_link(hw); |
Auke Kok | 9a799d7 | 2007-09-15 14:07:45 -0700 | [diff] [blame] | 522 | |
| 523 | return 0; |
| 524 | } |
Jesse Brandeburg | c44ade9 | 2008-09-11 19:59:59 -0700 | [diff] [blame] | 525 | |
Jesse Brandeburg | 0befdb3 | 2008-10-31 00:46:40 -0700 | [diff] [blame] | 526 | /** |
Don Skidmore | a391f1d | 2010-11-16 19:27:15 -0800 | [diff] [blame] | 527 | * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities |
| 528 | * @hw: pointer to hardware structure |
| 529 | * @speed: pointer to link speed |
| 530 | * @autoneg: boolean auto-negotiation value |
| 531 | * |
| 532 | * Determines the link capabilities by reading the AUTOC register. |
| 533 | */ |
| 534 | s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, |
Don Skidmore | fe15e8e | 2010-11-16 19:27:16 -0800 | [diff] [blame] | 535 | ixgbe_link_speed *speed, |
| 536 | bool *autoneg) |
Don Skidmore | a391f1d | 2010-11-16 19:27:15 -0800 | [diff] [blame] | 537 | { |
| 538 | s32 status = IXGBE_ERR_LINK_SETUP; |
| 539 | u16 speed_ability; |
| 540 | |
| 541 | *speed = 0; |
| 542 | *autoneg = true; |
| 543 | |
| 544 | status = hw->phy.ops.read_reg(hw, MDIO_SPEED, MDIO_MMD_PMAPMD, |
| 545 | &speed_ability); |
| 546 | |
| 547 | if (status == 0) { |
| 548 | if (speed_ability & MDIO_SPEED_10G) |
| 549 | *speed |= IXGBE_LINK_SPEED_10GB_FULL; |
| 550 | if (speed_ability & MDIO_PMA_SPEED_1000) |
| 551 | *speed |= IXGBE_LINK_SPEED_1GB_FULL; |
| 552 | if (speed_ability & MDIO_PMA_SPEED_100) |
| 553 | *speed |= IXGBE_LINK_SPEED_100_FULL; |
| 554 | } |
| 555 | |
| 556 | return status; |
| 557 | } |
| 558 | |
| 559 | /** |
Emil Tantilov | 9dda173 | 2011-03-05 01:28:07 +0000 | [diff] [blame] | 560 | * ixgbe_check_phy_link_tnx - Determine link and speed status |
| 561 | * @hw: pointer to hardware structure |
| 562 | * |
| 563 | * Reads the VS1 register to determine if link is up and the current speed for |
| 564 | * the PHY. |
| 565 | **/ |
| 566 | s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, |
| 567 | bool *link_up) |
| 568 | { |
| 569 | s32 status = 0; |
| 570 | u32 time_out; |
| 571 | u32 max_time_out = 10; |
| 572 | u16 phy_link = 0; |
| 573 | u16 phy_speed = 0; |
| 574 | u16 phy_data = 0; |
| 575 | |
| 576 | /* Initialize speed and link to default case */ |
| 577 | *link_up = false; |
| 578 | *speed = IXGBE_LINK_SPEED_10GB_FULL; |
| 579 | |
| 580 | /* |
| 581 | * Check current speed and link status of the PHY register. |
| 582 | * This is a vendor specific register and may have to |
| 583 | * be changed for other copper PHYs. |
| 584 | */ |
| 585 | for (time_out = 0; time_out < max_time_out; time_out++) { |
| 586 | udelay(10); |
| 587 | status = hw->phy.ops.read_reg(hw, |
| 588 | MDIO_STAT1, |
| 589 | MDIO_MMD_VEND1, |
| 590 | &phy_data); |
| 591 | phy_link = phy_data & |
| 592 | IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; |
| 593 | phy_speed = phy_data & |
| 594 | IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; |
| 595 | if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { |
| 596 | *link_up = true; |
| 597 | if (phy_speed == |
| 598 | IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) |
| 599 | *speed = IXGBE_LINK_SPEED_1GB_FULL; |
| 600 | break; |
| 601 | } |
| 602 | } |
| 603 | |
| 604 | return status; |
| 605 | } |
| 606 | |
| 607 | /** |
| 608 | * ixgbe_setup_phy_link_tnx - Set and restart autoneg |
| 609 | * @hw: pointer to hardware structure |
| 610 | * |
| 611 | * Restart autonegotiation and PHY and waits for completion. |
| 612 | **/ |
| 613 | s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) |
| 614 | { |
| 615 | s32 status = 0; |
| 616 | u32 time_out; |
| 617 | u32 max_time_out = 10; |
| 618 | u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; |
| 619 | bool autoneg = false; |
| 620 | ixgbe_link_speed speed; |
| 621 | |
| 622 | ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); |
| 623 | |
| 624 | if (speed & IXGBE_LINK_SPEED_10GB_FULL) { |
| 625 | /* Set or unset auto-negotiation 10G advertisement */ |
| 626 | hw->phy.ops.read_reg(hw, MDIO_AN_10GBT_CTRL, |
| 627 | MDIO_MMD_AN, |
| 628 | &autoneg_reg); |
| 629 | |
| 630 | autoneg_reg &= ~MDIO_AN_10GBT_CTRL_ADV10G; |
| 631 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) |
| 632 | autoneg_reg |= MDIO_AN_10GBT_CTRL_ADV10G; |
| 633 | |
| 634 | hw->phy.ops.write_reg(hw, MDIO_AN_10GBT_CTRL, |
| 635 | MDIO_MMD_AN, |
| 636 | autoneg_reg); |
| 637 | } |
| 638 | |
| 639 | if (speed & IXGBE_LINK_SPEED_1GB_FULL) { |
| 640 | /* Set or unset auto-negotiation 1G advertisement */ |
| 641 | hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, |
| 642 | MDIO_MMD_AN, |
| 643 | &autoneg_reg); |
| 644 | |
| 645 | autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; |
| 646 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) |
| 647 | autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; |
| 648 | |
| 649 | hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, |
| 650 | MDIO_MMD_AN, |
| 651 | autoneg_reg); |
| 652 | } |
| 653 | |
| 654 | if (speed & IXGBE_LINK_SPEED_100_FULL) { |
| 655 | /* Set or unset auto-negotiation 100M advertisement */ |
| 656 | hw->phy.ops.read_reg(hw, MDIO_AN_ADVERTISE, |
| 657 | MDIO_MMD_AN, |
| 658 | &autoneg_reg); |
| 659 | |
Emil Tantilov | 50c022e | 2011-03-31 09:36:12 +0000 | [diff] [blame] | 660 | autoneg_reg &= ~(ADVERTISE_100FULL | |
| 661 | ADVERTISE_100HALF); |
Emil Tantilov | 9dda173 | 2011-03-05 01:28:07 +0000 | [diff] [blame] | 662 | if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) |
| 663 | autoneg_reg |= ADVERTISE_100FULL; |
| 664 | |
| 665 | hw->phy.ops.write_reg(hw, MDIO_AN_ADVERTISE, |
| 666 | MDIO_MMD_AN, |
| 667 | autoneg_reg); |
| 668 | } |
| 669 | |
| 670 | /* Restart PHY autonegotiation and wait for completion */ |
| 671 | hw->phy.ops.read_reg(hw, MDIO_CTRL1, |
| 672 | MDIO_MMD_AN, &autoneg_reg); |
| 673 | |
| 674 | autoneg_reg |= MDIO_AN_CTRL1_RESTART; |
| 675 | |
| 676 | hw->phy.ops.write_reg(hw, MDIO_CTRL1, |
| 677 | MDIO_MMD_AN, autoneg_reg); |
| 678 | |
| 679 | /* Wait for autonegotiation to finish */ |
| 680 | for (time_out = 0; time_out < max_time_out; time_out++) { |
| 681 | udelay(10); |
| 682 | /* Restart PHY autonegotiation and wait for completion */ |
| 683 | status = hw->phy.ops.read_reg(hw, MDIO_STAT1, |
| 684 | MDIO_MMD_AN, |
| 685 | &autoneg_reg); |
| 686 | |
| 687 | autoneg_reg &= MDIO_AN_STAT1_COMPLETE; |
| 688 | if (autoneg_reg == MDIO_AN_STAT1_COMPLETE) |
| 689 | break; |
| 690 | } |
| 691 | |
| 692 | if (time_out == max_time_out) { |
| 693 | status = IXGBE_ERR_LINK_SETUP; |
| 694 | hw_dbg(hw, "ixgbe_setup_phy_link_tnx: time out"); |
| 695 | } |
| 696 | |
| 697 | return status; |
| 698 | } |
| 699 | |
| 700 | /** |
| 701 | * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version |
| 702 | * @hw: pointer to hardware structure |
| 703 | * @firmware_version: pointer to the PHY Firmware Version |
| 704 | **/ |
| 705 | s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, |
| 706 | u16 *firmware_version) |
| 707 | { |
| 708 | s32 status = 0; |
| 709 | |
| 710 | status = hw->phy.ops.read_reg(hw, TNX_FW_REV, |
| 711 | MDIO_MMD_VEND1, |
| 712 | firmware_version); |
| 713 | |
| 714 | return status; |
| 715 | } |
| 716 | |
| 717 | /** |
| 718 | * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version |
| 719 | * @hw: pointer to hardware structure |
| 720 | * @firmware_version: pointer to the PHY Firmware Version |
| 721 | **/ |
| 722 | s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, |
| 723 | u16 *firmware_version) |
| 724 | { |
| 725 | s32 status = 0; |
| 726 | |
| 727 | status = hw->phy.ops.read_reg(hw, AQ_FW_REV, |
| 728 | MDIO_MMD_VEND1, |
| 729 | firmware_version); |
| 730 | |
| 731 | return status; |
| 732 | } |
| 733 | |
| 734 | /** |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 735 | * ixgbe_reset_phy_nl - Performs a PHY reset |
| 736 | * @hw: pointer to hardware structure |
| 737 | **/ |
| 738 | s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) |
| 739 | { |
| 740 | u16 phy_offset, control, eword, edata, block_crc; |
| 741 | bool end_data = false; |
| 742 | u16 list_offset, data_offset; |
| 743 | u16 phy_data = 0; |
| 744 | s32 ret_val = 0; |
| 745 | u32 i; |
| 746 | |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 747 | hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, &phy_data); |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 748 | |
| 749 | /* reset the PHY and poll for completion */ |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 750 | hw->phy.ops.write_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, |
| 751 | (phy_data | MDIO_CTRL1_RESET)); |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 752 | |
| 753 | for (i = 0; i < 100; i++) { |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 754 | hw->phy.ops.read_reg(hw, MDIO_CTRL1, MDIO_MMD_PHYXS, |
| 755 | &phy_data); |
| 756 | if ((phy_data & MDIO_CTRL1_RESET) == 0) |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 757 | break; |
Don Skidmore | 032b432 | 2011-03-18 09:32:53 +0000 | [diff] [blame] | 758 | usleep_range(10000, 20000); |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 759 | } |
| 760 | |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 761 | if ((phy_data & MDIO_CTRL1_RESET) != 0) { |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 762 | hw_dbg(hw, "PHY reset did not complete.\n"); |
| 763 | ret_val = IXGBE_ERR_PHY; |
| 764 | goto out; |
| 765 | } |
| 766 | |
| 767 | /* Get init offsets */ |
| 768 | ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, |
| 769 | &data_offset); |
| 770 | if (ret_val != 0) |
| 771 | goto out; |
| 772 | |
| 773 | ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); |
| 774 | data_offset++; |
| 775 | while (!end_data) { |
| 776 | /* |
| 777 | * Read control word from PHY init contents offset |
| 778 | */ |
| 779 | ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); |
| 780 | control = (eword & IXGBE_CONTROL_MASK_NL) >> |
| 781 | IXGBE_CONTROL_SHIFT_NL; |
| 782 | edata = eword & IXGBE_DATA_MASK_NL; |
| 783 | switch (control) { |
| 784 | case IXGBE_DELAY_NL: |
| 785 | data_offset++; |
| 786 | hw_dbg(hw, "DELAY: %d MS\n", edata); |
Don Skidmore | 032b432 | 2011-03-18 09:32:53 +0000 | [diff] [blame] | 787 | usleep_range(edata * 1000, edata * 2000); |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 788 | break; |
| 789 | case IXGBE_DATA_NL: |
Frans Pop | d6dbee8 | 2010-03-24 07:57:35 +0000 | [diff] [blame] | 790 | hw_dbg(hw, "DATA:\n"); |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 791 | data_offset++; |
| 792 | hw->eeprom.ops.read(hw, data_offset++, |
| 793 | &phy_offset); |
| 794 | for (i = 0; i < edata; i++) { |
| 795 | hw->eeprom.ops.read(hw, data_offset, &eword); |
| 796 | hw->phy.ops.write_reg(hw, phy_offset, |
Ben Hutchings | 6b73e10 | 2009-04-29 08:08:58 +0000 | [diff] [blame] | 797 | MDIO_MMD_PMAPMD, eword); |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 798 | hw_dbg(hw, "Wrote %4.4x to %4.4x\n", eword, |
| 799 | phy_offset); |
| 800 | data_offset++; |
| 801 | phy_offset++; |
| 802 | } |
| 803 | break; |
| 804 | case IXGBE_CONTROL_NL: |
| 805 | data_offset++; |
Frans Pop | d6dbee8 | 2010-03-24 07:57:35 +0000 | [diff] [blame] | 806 | hw_dbg(hw, "CONTROL:\n"); |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 807 | if (edata == IXGBE_CONTROL_EOL_NL) { |
| 808 | hw_dbg(hw, "EOL\n"); |
| 809 | end_data = true; |
| 810 | } else if (edata == IXGBE_CONTROL_SOL_NL) { |
| 811 | hw_dbg(hw, "SOL\n"); |
| 812 | } else { |
| 813 | hw_dbg(hw, "Bad control value\n"); |
| 814 | ret_val = IXGBE_ERR_PHY; |
| 815 | goto out; |
| 816 | } |
| 817 | break; |
| 818 | default: |
| 819 | hw_dbg(hw, "Bad control type\n"); |
| 820 | ret_val = IXGBE_ERR_PHY; |
| 821 | goto out; |
| 822 | } |
| 823 | } |
| 824 | |
| 825 | out: |
| 826 | return ret_val; |
| 827 | } |
| 828 | |
| 829 | /** |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 830 | * ixgbe_identify_sfp_module_generic - Identifies SFP modules |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 831 | * @hw: pointer to hardware structure |
| 832 | * |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 833 | * Searches for and identifies the SFP module and assigns appropriate PHY type. |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 834 | **/ |
| 835 | s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) |
| 836 | { |
Peter P Waskiewicz Jr | 8ef78ad | 2012-02-01 09:19:21 +0000 | [diff] [blame] | 837 | struct ixgbe_adapter *adapter = hw->back; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 838 | s32 status = IXGBE_ERR_PHY_ADDR_INVALID; |
| 839 | u32 vendor_oui = 0; |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 840 | enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 841 | u8 identifier = 0; |
| 842 | u8 comp_codes_1g = 0; |
| 843 | u8 comp_codes_10g = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 844 | u8 oui_bytes[3] = {0, 0, 0}; |
Peter P Waskiewicz Jr | 537d58a | 2009-05-19 09:18:51 +0000 | [diff] [blame] | 845 | u8 cable_tech = 0; |
Don Skidmore | ea0a04d | 2010-05-18 16:00:13 +0000 | [diff] [blame] | 846 | u8 cable_spec = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 847 | u16 enforce_sfp = 0; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 848 | |
Don Skidmore | 8ca783a | 2009-05-26 20:40:47 -0700 | [diff] [blame] | 849 | if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { |
| 850 | hw->phy.sfp_type = ixgbe_sfp_type_not_present; |
| 851 | status = IXGBE_ERR_SFP_NOT_PRESENT; |
| 852 | goto out; |
| 853 | } |
| 854 | |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 855 | status = hw->phy.ops.read_i2c_eeprom(hw, |
| 856 | IXGBE_SFF_IDENTIFIER, |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 857 | &identifier); |
| 858 | |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 859 | if (status == IXGBE_ERR_SWFW_SYNC || |
| 860 | status == IXGBE_ERR_I2C || |
| 861 | status == IXGBE_ERR_SFP_NOT_PRESENT) |
| 862 | goto err_read_i2c_eeprom; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 863 | |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 864 | /* LAN ID is needed for sfp_type determination */ |
| 865 | hw->mac.ops.set_lan_id(hw); |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 866 | |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 867 | if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { |
| 868 | hw->phy.type = ixgbe_phy_sfp_unsupported; |
| 869 | status = IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 870 | } else { |
| 871 | status = hw->phy.ops.read_i2c_eeprom(hw, |
| 872 | IXGBE_SFF_1GBE_COMP_CODES, |
| 873 | &comp_codes_1g); |
| 874 | |
| 875 | if (status == IXGBE_ERR_SWFW_SYNC || |
| 876 | status == IXGBE_ERR_I2C || |
| 877 | status == IXGBE_ERR_SFP_NOT_PRESENT) |
| 878 | goto err_read_i2c_eeprom; |
| 879 | |
| 880 | status = hw->phy.ops.read_i2c_eeprom(hw, |
| 881 | IXGBE_SFF_10GBE_COMP_CODES, |
| 882 | &comp_codes_10g); |
| 883 | |
| 884 | if (status == IXGBE_ERR_SWFW_SYNC || |
| 885 | status == IXGBE_ERR_I2C || |
| 886 | status == IXGBE_ERR_SFP_NOT_PRESENT) |
| 887 | goto err_read_i2c_eeprom; |
| 888 | status = hw->phy.ops.read_i2c_eeprom(hw, |
| 889 | IXGBE_SFF_CABLE_TECHNOLOGY, |
| 890 | &cable_tech); |
| 891 | |
| 892 | if (status == IXGBE_ERR_SWFW_SYNC || |
| 893 | status == IXGBE_ERR_I2C || |
| 894 | status == IXGBE_ERR_SFP_NOT_PRESENT) |
| 895 | goto err_read_i2c_eeprom; |
| 896 | |
| 897 | /* ID Module |
| 898 | * ========= |
| 899 | * 0 SFP_DA_CU |
| 900 | * 1 SFP_SR |
| 901 | * 2 SFP_LR |
| 902 | * 3 SFP_DA_CORE0 - 82599-specific |
| 903 | * 4 SFP_DA_CORE1 - 82599-specific |
| 904 | * 5 SFP_SR/LR_CORE0 - 82599-specific |
| 905 | * 6 SFP_SR/LR_CORE1 - 82599-specific |
| 906 | * 7 SFP_act_lmt_DA_CORE0 - 82599-specific |
| 907 | * 8 SFP_act_lmt_DA_CORE1 - 82599-specific |
| 908 | * 9 SFP_1g_cu_CORE0 - 82599-specific |
| 909 | * 10 SFP_1g_cu_CORE1 - 82599-specific |
Jacob Keller | a49fda3 | 2012-06-08 06:59:09 +0000 | [diff] [blame] | 910 | * 11 SFP_1g_sx_CORE0 - 82599-specific |
| 911 | * 12 SFP_1g_sx_CORE1 - 82599-specific |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 912 | */ |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 913 | if (hw->mac.type == ixgbe_mac_82598EB) { |
Peter P Waskiewicz Jr | 537d58a | 2009-05-19 09:18:51 +0000 | [diff] [blame] | 914 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 915 | hw->phy.sfp_type = ixgbe_sfp_type_da_cu; |
| 916 | else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) |
| 917 | hw->phy.sfp_type = ixgbe_sfp_type_sr; |
| 918 | else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) |
| 919 | hw->phy.sfp_type = ixgbe_sfp_type_lr; |
| 920 | else |
| 921 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
| 922 | } else if (hw->mac.type == ixgbe_mac_82599EB) { |
Don Skidmore | ea0a04d | 2010-05-18 16:00:13 +0000 | [diff] [blame] | 923 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 924 | if (hw->bus.lan_id == 0) |
| 925 | hw->phy.sfp_type = |
| 926 | ixgbe_sfp_type_da_cu_core0; |
| 927 | else |
| 928 | hw->phy.sfp_type = |
| 929 | ixgbe_sfp_type_da_cu_core1; |
Don Skidmore | ea0a04d | 2010-05-18 16:00:13 +0000 | [diff] [blame] | 930 | } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { |
| 931 | hw->phy.ops.read_i2c_eeprom( |
| 932 | hw, IXGBE_SFF_CABLE_SPEC_COMP, |
| 933 | &cable_spec); |
| 934 | if (cable_spec & |
| 935 | IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { |
| 936 | if (hw->bus.lan_id == 0) |
| 937 | hw->phy.sfp_type = |
| 938 | ixgbe_sfp_type_da_act_lmt_core0; |
| 939 | else |
| 940 | hw->phy.sfp_type = |
| 941 | ixgbe_sfp_type_da_act_lmt_core1; |
| 942 | } else { |
| 943 | hw->phy.sfp_type = |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 944 | ixgbe_sfp_type_unknown; |
Don Skidmore | ea0a04d | 2010-05-18 16:00:13 +0000 | [diff] [blame] | 945 | } |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 946 | } else if (comp_codes_10g & |
| 947 | (IXGBE_SFF_10GBASESR_CAPABLE | |
| 948 | IXGBE_SFF_10GBASELR_CAPABLE)) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 949 | if (hw->bus.lan_id == 0) |
| 950 | hw->phy.sfp_type = |
| 951 | ixgbe_sfp_type_srlr_core0; |
| 952 | else |
| 953 | hw->phy.sfp_type = |
| 954 | ixgbe_sfp_type_srlr_core1; |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 955 | } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { |
Don Skidmore | cb836a9 | 2010-06-29 18:30:59 +0000 | [diff] [blame] | 956 | if (hw->bus.lan_id == 0) |
| 957 | hw->phy.sfp_type = |
| 958 | ixgbe_sfp_type_1g_cu_core0; |
| 959 | else |
| 960 | hw->phy.sfp_type = |
| 961 | ixgbe_sfp_type_1g_cu_core1; |
Jacob Keller | a49fda3 | 2012-06-08 06:59:09 +0000 | [diff] [blame] | 962 | } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { |
| 963 | if (hw->bus.lan_id == 0) |
| 964 | hw->phy.sfp_type = |
| 965 | ixgbe_sfp_type_1g_sx_core0; |
| 966 | else |
| 967 | hw->phy.sfp_type = |
| 968 | ixgbe_sfp_type_1g_sx_core1; |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 969 | } else { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 970 | hw->phy.sfp_type = ixgbe_sfp_type_unknown; |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 971 | } |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 972 | } |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 973 | |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 974 | if (hw->phy.sfp_type != stored_sfp_type) |
| 975 | hw->phy.sfp_setup_needed = true; |
| 976 | |
| 977 | /* Determine if the SFP+ PHY is dual speed or not. */ |
Peter P Waskiewicz Jr | 50ac58b | 2009-06-04 11:10:53 +0000 | [diff] [blame] | 978 | hw->phy.multispeed_fiber = false; |
PJ Waskiewicz | 553b449 | 2009-04-09 22:28:15 +0000 | [diff] [blame] | 979 | if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && |
| 980 | (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || |
| 981 | ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && |
| 982 | (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) |
| 983 | hw->phy.multispeed_fiber = true; |
| 984 | |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 985 | /* Determine PHY vendor */ |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 986 | if (hw->phy.type != ixgbe_phy_nl) { |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 987 | hw->phy.id = identifier; |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 988 | status = hw->phy.ops.read_i2c_eeprom(hw, |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 989 | IXGBE_SFF_VENDOR_OUI_BYTE0, |
| 990 | &oui_bytes[0]); |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 991 | |
| 992 | if (status == IXGBE_ERR_SWFW_SYNC || |
| 993 | status == IXGBE_ERR_I2C || |
| 994 | status == IXGBE_ERR_SFP_NOT_PRESENT) |
| 995 | goto err_read_i2c_eeprom; |
| 996 | |
| 997 | status = hw->phy.ops.read_i2c_eeprom(hw, |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 998 | IXGBE_SFF_VENDOR_OUI_BYTE1, |
| 999 | &oui_bytes[1]); |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 1000 | |
| 1001 | if (status == IXGBE_ERR_SWFW_SYNC || |
| 1002 | status == IXGBE_ERR_I2C || |
| 1003 | status == IXGBE_ERR_SFP_NOT_PRESENT) |
| 1004 | goto err_read_i2c_eeprom; |
| 1005 | |
| 1006 | status = hw->phy.ops.read_i2c_eeprom(hw, |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 1007 | IXGBE_SFF_VENDOR_OUI_BYTE2, |
| 1008 | &oui_bytes[2]); |
| 1009 | |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 1010 | if (status == IXGBE_ERR_SWFW_SYNC || |
| 1011 | status == IXGBE_ERR_I2C || |
| 1012 | status == IXGBE_ERR_SFP_NOT_PRESENT) |
| 1013 | goto err_read_i2c_eeprom; |
| 1014 | |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 1015 | vendor_oui = |
| 1016 | ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | |
| 1017 | (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | |
| 1018 | (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); |
| 1019 | |
| 1020 | switch (vendor_oui) { |
| 1021 | case IXGBE_SFF_VENDOR_OUI_TYCO: |
Peter P Waskiewicz Jr | 537d58a | 2009-05-19 09:18:51 +0000 | [diff] [blame] | 1022 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) |
Don Skidmore | ea0a04d | 2010-05-18 16:00:13 +0000 | [diff] [blame] | 1023 | hw->phy.type = |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 1024 | ixgbe_phy_sfp_passive_tyco; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 1025 | break; |
| 1026 | case IXGBE_SFF_VENDOR_OUI_FTL: |
Don Skidmore | ea0a04d | 2010-05-18 16:00:13 +0000 | [diff] [blame] | 1027 | if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) |
| 1028 | hw->phy.type = ixgbe_phy_sfp_ftl_active; |
| 1029 | else |
| 1030 | hw->phy.type = ixgbe_phy_sfp_ftl; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 1031 | break; |
| 1032 | case IXGBE_SFF_VENDOR_OUI_AVAGO: |
| 1033 | hw->phy.type = ixgbe_phy_sfp_avago; |
| 1034 | break; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1035 | case IXGBE_SFF_VENDOR_OUI_INTEL: |
| 1036 | hw->phy.type = ixgbe_phy_sfp_intel; |
| 1037 | break; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 1038 | default: |
Peter P Waskiewicz Jr | 537d58a | 2009-05-19 09:18:51 +0000 | [diff] [blame] | 1039 | if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) |
Don Skidmore | ea0a04d | 2010-05-18 16:00:13 +0000 | [diff] [blame] | 1040 | hw->phy.type = |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 1041 | ixgbe_phy_sfp_passive_unknown; |
Don Skidmore | ea0a04d | 2010-05-18 16:00:13 +0000 | [diff] [blame] | 1042 | else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) |
| 1043 | hw->phy.type = |
| 1044 | ixgbe_phy_sfp_active_unknown; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 1045 | else |
| 1046 | hw->phy.type = ixgbe_phy_sfp_unknown; |
| 1047 | break; |
| 1048 | } |
| 1049 | } |
Waskiewicz Jr, Peter P | fa466e9 | 2009-04-23 11:31:37 +0000 | [diff] [blame] | 1050 | |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 1051 | /* Allow any DA cable vendor */ |
Don Skidmore | ea0a04d | 2010-05-18 16:00:13 +0000 | [diff] [blame] | 1052 | if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | |
| 1053 | IXGBE_SFF_DA_ACTIVE_CABLE)) { |
Waskiewicz Jr, Peter P | fa466e9 | 2009-04-23 11:31:37 +0000 | [diff] [blame] | 1054 | status = 0; |
| 1055 | goto out; |
| 1056 | } |
| 1057 | |
Don Skidmore | cb836a9 | 2010-06-29 18:30:59 +0000 | [diff] [blame] | 1058 | /* Verify supported 1G SFP modules */ |
| 1059 | if (comp_codes_10g == 0 && |
| 1060 | !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || |
Jacob Keller | a49fda3 | 2012-06-08 06:59:09 +0000 | [diff] [blame] | 1061 | hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || |
| 1062 | hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || |
| 1063 | hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { |
Waskiewicz Jr, Peter P | fa466e9 | 2009-04-23 11:31:37 +0000 | [diff] [blame] | 1064 | hw->phy.type = ixgbe_phy_sfp_unsupported; |
| 1065 | status = IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 1066 | goto out; |
| 1067 | } |
| 1068 | |
| 1069 | /* Anything else 82598-based is supported */ |
| 1070 | if (hw->mac.type == ixgbe_mac_82598EB) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1071 | status = 0; |
| 1072 | goto out; |
| 1073 | } |
| 1074 | |
Peter P Waskiewicz Jr | 0419305 | 2009-04-09 22:28:50 +0000 | [diff] [blame] | 1075 | hw->mac.ops.get_device_caps(hw, &enforce_sfp); |
Don Skidmore | cb836a9 | 2010-06-29 18:30:59 +0000 | [diff] [blame] | 1076 | if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && |
| 1077 | !((hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0) || |
Jacob Keller | a49fda3 | 2012-06-08 06:59:09 +0000 | [diff] [blame] | 1078 | (hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1) || |
| 1079 | (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0) || |
| 1080 | (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1))) { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1081 | /* Make sure we're a supported PHY type */ |
| 1082 | if (hw->phy.type == ixgbe_phy_sfp_intel) { |
| 1083 | status = 0; |
| 1084 | } else { |
Peter P Waskiewicz Jr | 8ef78ad | 2012-02-01 09:19:21 +0000 | [diff] [blame] | 1085 | if (hw->allow_unsupported_sfp) { |
| 1086 | e_warn(drv, "WARNING: Intel (R) Network Connections are quality tested using Intel (R) Ethernet Optics. Using untested modules is not supported and may cause unstable operation or damage to the module or the adapter. Intel Corporation is not responsible for any harm caused by using untested modules."); |
| 1087 | status = 0; |
| 1088 | } else { |
| 1089 | hw_dbg(hw, |
| 1090 | "SFP+ module not supported\n"); |
| 1091 | hw->phy.type = |
| 1092 | ixgbe_phy_sfp_unsupported; |
| 1093 | status = IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 1094 | } |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1095 | } |
| 1096 | } else { |
| 1097 | status = 0; |
| 1098 | } |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 1099 | } |
| 1100 | |
| 1101 | out: |
| 1102 | return status; |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 1103 | |
| 1104 | err_read_i2c_eeprom: |
| 1105 | hw->phy.sfp_type = ixgbe_sfp_type_not_present; |
| 1106 | if (hw->phy.type != ixgbe_phy_nl) { |
| 1107 | hw->phy.id = 0; |
| 1108 | hw->phy.type = ixgbe_phy_unknown; |
| 1109 | } |
| 1110 | return IXGBE_ERR_SFP_NOT_PRESENT; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 1111 | } |
| 1112 | |
| 1113 | /** |
Emil Tantilov | 76d97dd | 2011-02-16 10:14:00 +0000 | [diff] [blame] | 1114 | * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 1115 | * @hw: pointer to hardware structure |
| 1116 | * @list_offset: offset to the SFP ID list |
| 1117 | * @data_offset: offset to the SFP data block |
Emil Tantilov | 75f19c3 | 2011-02-19 08:43:55 +0000 | [diff] [blame] | 1118 | * |
| 1119 | * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if |
| 1120 | * so it returns the offsets to the phy init sequence block. |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 1121 | **/ |
| 1122 | s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, |
| 1123 | u16 *list_offset, |
| 1124 | u16 *data_offset) |
| 1125 | { |
| 1126 | u16 sfp_id; |
Don Skidmore | cb836a9 | 2010-06-29 18:30:59 +0000 | [diff] [blame] | 1127 | u16 sfp_type = hw->phy.sfp_type; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 1128 | |
| 1129 | if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) |
| 1130 | return IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 1131 | |
| 1132 | if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) |
| 1133 | return IXGBE_ERR_SFP_NOT_PRESENT; |
| 1134 | |
| 1135 | if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && |
| 1136 | (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) |
| 1137 | return IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 1138 | |
Don Skidmore | cb836a9 | 2010-06-29 18:30:59 +0000 | [diff] [blame] | 1139 | /* |
| 1140 | * Limiting active cables and 1G Phys must be initialized as |
| 1141 | * SR modules |
| 1142 | */ |
| 1143 | if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || |
Jacob Keller | a49fda3 | 2012-06-08 06:59:09 +0000 | [diff] [blame] | 1144 | sfp_type == ixgbe_sfp_type_1g_cu_core0 || |
| 1145 | sfp_type == ixgbe_sfp_type_1g_sx_core0) |
Don Skidmore | cb836a9 | 2010-06-29 18:30:59 +0000 | [diff] [blame] | 1146 | sfp_type = ixgbe_sfp_type_srlr_core0; |
| 1147 | else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || |
Jacob Keller | a49fda3 | 2012-06-08 06:59:09 +0000 | [diff] [blame] | 1148 | sfp_type == ixgbe_sfp_type_1g_cu_core1 || |
| 1149 | sfp_type == ixgbe_sfp_type_1g_sx_core1) |
Don Skidmore | cb836a9 | 2010-06-29 18:30:59 +0000 | [diff] [blame] | 1150 | sfp_type = ixgbe_sfp_type_srlr_core1; |
| 1151 | |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 1152 | /* Read offset to PHY init contents */ |
| 1153 | hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset); |
| 1154 | |
| 1155 | if ((!*list_offset) || (*list_offset == 0xFFFF)) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1156 | return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 1157 | |
| 1158 | /* Shift offset to first ID word */ |
| 1159 | (*list_offset)++; |
| 1160 | |
| 1161 | /* |
| 1162 | * Find the matching SFP ID in the EEPROM |
| 1163 | * and program the init sequence |
| 1164 | */ |
| 1165 | hw->eeprom.ops.read(hw, *list_offset, &sfp_id); |
| 1166 | |
| 1167 | while (sfp_id != IXGBE_PHY_INIT_END_NL) { |
Don Skidmore | cb836a9 | 2010-06-29 18:30:59 +0000 | [diff] [blame] | 1168 | if (sfp_id == sfp_type) { |
Donald Skidmore | c4900be | 2008-11-20 21:11:42 -0800 | [diff] [blame] | 1169 | (*list_offset)++; |
| 1170 | hw->eeprom.ops.read(hw, *list_offset, data_offset); |
| 1171 | if ((!*data_offset) || (*data_offset == 0xFFFF)) { |
| 1172 | hw_dbg(hw, "SFP+ module not supported\n"); |
| 1173 | return IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 1174 | } else { |
| 1175 | break; |
| 1176 | } |
| 1177 | } else { |
| 1178 | (*list_offset) += 2; |
| 1179 | if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) |
| 1180 | return IXGBE_ERR_PHY; |
| 1181 | } |
| 1182 | } |
| 1183 | |
| 1184 | if (sfp_id == IXGBE_PHY_INIT_END_NL) { |
| 1185 | hw_dbg(hw, "No matching SFP+ module found\n"); |
| 1186 | return IXGBE_ERR_SFP_NOT_SUPPORTED; |
| 1187 | } |
| 1188 | |
| 1189 | return 0; |
| 1190 | } |
| 1191 | |
| 1192 | /** |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1193 | * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface |
| 1194 | * @hw: pointer to hardware structure |
| 1195 | * @byte_offset: EEPROM byte offset to read |
| 1196 | * @eeprom_data: value read |
| 1197 | * |
| 1198 | * Performs byte read operation to SFP module's EEPROM over I2C interface. |
| 1199 | **/ |
| 1200 | s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, |
| 1201 | u8 *eeprom_data) |
| 1202 | { |
| 1203 | return hw->phy.ops.read_i2c_byte(hw, byte_offset, |
| 1204 | IXGBE_I2C_EEPROM_DEV_ADDR, |
| 1205 | eeprom_data); |
| 1206 | } |
| 1207 | |
| 1208 | /** |
| 1209 | * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface |
| 1210 | * @hw: pointer to hardware structure |
| 1211 | * @byte_offset: EEPROM byte offset to write |
| 1212 | * @eeprom_data: value to write |
| 1213 | * |
| 1214 | * Performs byte write operation to SFP module's EEPROM over I2C interface. |
| 1215 | **/ |
| 1216 | s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, |
| 1217 | u8 eeprom_data) |
| 1218 | { |
| 1219 | return hw->phy.ops.write_i2c_byte(hw, byte_offset, |
| 1220 | IXGBE_I2C_EEPROM_DEV_ADDR, |
| 1221 | eeprom_data); |
| 1222 | } |
| 1223 | |
| 1224 | /** |
| 1225 | * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C |
| 1226 | * @hw: pointer to hardware structure |
| 1227 | * @byte_offset: byte offset to read |
| 1228 | * @data: value read |
| 1229 | * |
| 1230 | * Performs byte read operation to SFP module's EEPROM over I2C interface at |
Emil Tantilov | 3fbaa3a | 2011-08-30 13:33:51 +0000 | [diff] [blame] | 1231 | * a specified device address. |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1232 | **/ |
| 1233 | s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, |
| 1234 | u8 dev_addr, u8 *data) |
| 1235 | { |
| 1236 | s32 status = 0; |
Emil Tantilov | 75f19c3 | 2011-02-19 08:43:55 +0000 | [diff] [blame] | 1237 | u32 max_retry = 10; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1238 | u32 retry = 0; |
Emil Tantilov | 75f19c3 | 2011-02-19 08:43:55 +0000 | [diff] [blame] | 1239 | u16 swfw_mask = 0; |
Rusty Russell | 3db1cd5 | 2011-12-19 13:56:45 +0000 | [diff] [blame] | 1240 | bool nack = true; |
Emil Tantilov | 3fbaa3a | 2011-08-30 13:33:51 +0000 | [diff] [blame] | 1241 | *data = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1242 | |
Emil Tantilov | 75f19c3 | 2011-02-19 08:43:55 +0000 | [diff] [blame] | 1243 | if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) |
| 1244 | swfw_mask = IXGBE_GSSR_PHY1_SM; |
| 1245 | else |
| 1246 | swfw_mask = IXGBE_GSSR_PHY0_SM; |
| 1247 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1248 | do { |
Emil Tantilov | 6d980c3 | 2011-04-13 04:56:15 +0000 | [diff] [blame] | 1249 | if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) { |
Emil Tantilov | 75f19c3 | 2011-02-19 08:43:55 +0000 | [diff] [blame] | 1250 | status = IXGBE_ERR_SWFW_SYNC; |
| 1251 | goto read_byte_out; |
| 1252 | } |
| 1253 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1254 | ixgbe_i2c_start(hw); |
| 1255 | |
| 1256 | /* Device Address and write indication */ |
| 1257 | status = ixgbe_clock_out_i2c_byte(hw, dev_addr); |
| 1258 | if (status != 0) |
| 1259 | goto fail; |
| 1260 | |
| 1261 | status = ixgbe_get_i2c_ack(hw); |
| 1262 | if (status != 0) |
| 1263 | goto fail; |
| 1264 | |
| 1265 | status = ixgbe_clock_out_i2c_byte(hw, byte_offset); |
| 1266 | if (status != 0) |
| 1267 | goto fail; |
| 1268 | |
| 1269 | status = ixgbe_get_i2c_ack(hw); |
| 1270 | if (status != 0) |
| 1271 | goto fail; |
| 1272 | |
| 1273 | ixgbe_i2c_start(hw); |
| 1274 | |
| 1275 | /* Device Address and read indication */ |
| 1276 | status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); |
| 1277 | if (status != 0) |
| 1278 | goto fail; |
| 1279 | |
| 1280 | status = ixgbe_get_i2c_ack(hw); |
| 1281 | if (status != 0) |
| 1282 | goto fail; |
| 1283 | |
| 1284 | status = ixgbe_clock_in_i2c_byte(hw, data); |
| 1285 | if (status != 0) |
| 1286 | goto fail; |
| 1287 | |
| 1288 | status = ixgbe_clock_out_i2c_bit(hw, nack); |
| 1289 | if (status != 0) |
| 1290 | goto fail; |
| 1291 | |
| 1292 | ixgbe_i2c_stop(hw); |
| 1293 | break; |
| 1294 | |
| 1295 | fail: |
Emil Tantilov | 6d980c3 | 2011-04-13 04:56:15 +0000 | [diff] [blame] | 1296 | hw->mac.ops.release_swfw_sync(hw, swfw_mask); |
Emil Tantilov | 75f19c3 | 2011-02-19 08:43:55 +0000 | [diff] [blame] | 1297 | msleep(100); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1298 | ixgbe_i2c_bus_clear(hw); |
| 1299 | retry++; |
| 1300 | if (retry < max_retry) |
| 1301 | hw_dbg(hw, "I2C byte read error - Retrying.\n"); |
| 1302 | else |
| 1303 | hw_dbg(hw, "I2C byte read error.\n"); |
| 1304 | |
| 1305 | } while (retry < max_retry); |
| 1306 | |
Emil Tantilov | 6d980c3 | 2011-04-13 04:56:15 +0000 | [diff] [blame] | 1307 | hw->mac.ops.release_swfw_sync(hw, swfw_mask); |
Emil Tantilov | 75f19c3 | 2011-02-19 08:43:55 +0000 | [diff] [blame] | 1308 | |
| 1309 | read_byte_out: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1310 | return status; |
| 1311 | } |
| 1312 | |
| 1313 | /** |
| 1314 | * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C |
| 1315 | * @hw: pointer to hardware structure |
| 1316 | * @byte_offset: byte offset to write |
| 1317 | * @data: value to write |
| 1318 | * |
| 1319 | * Performs byte write operation to SFP module's EEPROM over I2C interface at |
| 1320 | * a specified device address. |
| 1321 | **/ |
| 1322 | s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, |
| 1323 | u8 dev_addr, u8 data) |
| 1324 | { |
| 1325 | s32 status = 0; |
| 1326 | u32 max_retry = 1; |
| 1327 | u32 retry = 0; |
Emil Tantilov | 75f19c3 | 2011-02-19 08:43:55 +0000 | [diff] [blame] | 1328 | u16 swfw_mask = 0; |
| 1329 | |
| 1330 | if (IXGBE_READ_REG(hw, IXGBE_STATUS) & IXGBE_STATUS_LAN_ID_1) |
| 1331 | swfw_mask = IXGBE_GSSR_PHY1_SM; |
| 1332 | else |
| 1333 | swfw_mask = IXGBE_GSSR_PHY0_SM; |
| 1334 | |
Emil Tantilov | 6d980c3 | 2011-04-13 04:56:15 +0000 | [diff] [blame] | 1335 | if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 0) { |
Emil Tantilov | 75f19c3 | 2011-02-19 08:43:55 +0000 | [diff] [blame] | 1336 | status = IXGBE_ERR_SWFW_SYNC; |
| 1337 | goto write_byte_out; |
| 1338 | } |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1339 | |
| 1340 | do { |
| 1341 | ixgbe_i2c_start(hw); |
| 1342 | |
| 1343 | status = ixgbe_clock_out_i2c_byte(hw, dev_addr); |
| 1344 | if (status != 0) |
| 1345 | goto fail; |
| 1346 | |
| 1347 | status = ixgbe_get_i2c_ack(hw); |
| 1348 | if (status != 0) |
| 1349 | goto fail; |
| 1350 | |
| 1351 | status = ixgbe_clock_out_i2c_byte(hw, byte_offset); |
| 1352 | if (status != 0) |
| 1353 | goto fail; |
| 1354 | |
| 1355 | status = ixgbe_get_i2c_ack(hw); |
| 1356 | if (status != 0) |
| 1357 | goto fail; |
| 1358 | |
| 1359 | status = ixgbe_clock_out_i2c_byte(hw, data); |
| 1360 | if (status != 0) |
| 1361 | goto fail; |
| 1362 | |
| 1363 | status = ixgbe_get_i2c_ack(hw); |
| 1364 | if (status != 0) |
| 1365 | goto fail; |
| 1366 | |
| 1367 | ixgbe_i2c_stop(hw); |
| 1368 | break; |
| 1369 | |
| 1370 | fail: |
| 1371 | ixgbe_i2c_bus_clear(hw); |
| 1372 | retry++; |
| 1373 | if (retry < max_retry) |
| 1374 | hw_dbg(hw, "I2C byte write error - Retrying.\n"); |
| 1375 | else |
| 1376 | hw_dbg(hw, "I2C byte write error.\n"); |
| 1377 | } while (retry < max_retry); |
| 1378 | |
Emil Tantilov | 6d980c3 | 2011-04-13 04:56:15 +0000 | [diff] [blame] | 1379 | hw->mac.ops.release_swfw_sync(hw, swfw_mask); |
Emil Tantilov | 75f19c3 | 2011-02-19 08:43:55 +0000 | [diff] [blame] | 1380 | |
| 1381 | write_byte_out: |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1382 | return status; |
| 1383 | } |
| 1384 | |
| 1385 | /** |
| 1386 | * ixgbe_i2c_start - Sets I2C start condition |
| 1387 | * @hw: pointer to hardware structure |
| 1388 | * |
| 1389 | * Sets I2C start condition (High -> Low on SDA while SCL is High) |
| 1390 | **/ |
| 1391 | static void ixgbe_i2c_start(struct ixgbe_hw *hw) |
| 1392 | { |
| 1393 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1394 | |
| 1395 | /* Start condition must begin with data and clock high */ |
| 1396 | ixgbe_set_i2c_data(hw, &i2cctl, 1); |
| 1397 | ixgbe_raise_i2c_clk(hw, &i2cctl); |
| 1398 | |
| 1399 | /* Setup time for start condition (4.7us) */ |
| 1400 | udelay(IXGBE_I2C_T_SU_STA); |
| 1401 | |
| 1402 | ixgbe_set_i2c_data(hw, &i2cctl, 0); |
| 1403 | |
| 1404 | /* Hold time for start condition (4us) */ |
| 1405 | udelay(IXGBE_I2C_T_HD_STA); |
| 1406 | |
| 1407 | ixgbe_lower_i2c_clk(hw, &i2cctl); |
| 1408 | |
| 1409 | /* Minimum low period of clock is 4.7 us */ |
| 1410 | udelay(IXGBE_I2C_T_LOW); |
| 1411 | |
| 1412 | } |
| 1413 | |
| 1414 | /** |
| 1415 | * ixgbe_i2c_stop - Sets I2C stop condition |
| 1416 | * @hw: pointer to hardware structure |
| 1417 | * |
| 1418 | * Sets I2C stop condition (Low -> High on SDA while SCL is High) |
| 1419 | **/ |
| 1420 | static void ixgbe_i2c_stop(struct ixgbe_hw *hw) |
| 1421 | { |
| 1422 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1423 | |
| 1424 | /* Stop condition must begin with data low and clock high */ |
| 1425 | ixgbe_set_i2c_data(hw, &i2cctl, 0); |
| 1426 | ixgbe_raise_i2c_clk(hw, &i2cctl); |
| 1427 | |
| 1428 | /* Setup time for stop condition (4us) */ |
| 1429 | udelay(IXGBE_I2C_T_SU_STO); |
| 1430 | |
| 1431 | ixgbe_set_i2c_data(hw, &i2cctl, 1); |
| 1432 | |
| 1433 | /* bus free time between stop and start (4.7us)*/ |
| 1434 | udelay(IXGBE_I2C_T_BUF); |
| 1435 | } |
| 1436 | |
| 1437 | /** |
| 1438 | * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C |
| 1439 | * @hw: pointer to hardware structure |
| 1440 | * @data: data byte to clock in |
| 1441 | * |
| 1442 | * Clocks in one byte data via I2C data/clock |
| 1443 | **/ |
| 1444 | static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) |
| 1445 | { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1446 | s32 i; |
Rusty Russell | 3db1cd5 | 2011-12-19 13:56:45 +0000 | [diff] [blame] | 1447 | bool bit = false; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1448 | |
| 1449 | for (i = 7; i >= 0; i--) { |
Emil Tantilov | e1befd7 | 2011-08-27 07:18:47 +0000 | [diff] [blame] | 1450 | ixgbe_clock_in_i2c_bit(hw, &bit); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1451 | *data |= bit << i; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1452 | } |
| 1453 | |
Emil Tantilov | e1befd7 | 2011-08-27 07:18:47 +0000 | [diff] [blame] | 1454 | return 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1455 | } |
| 1456 | |
| 1457 | /** |
| 1458 | * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C |
| 1459 | * @hw: pointer to hardware structure |
| 1460 | * @data: data byte clocked out |
| 1461 | * |
| 1462 | * Clocks out one byte data via I2C data/clock |
| 1463 | **/ |
| 1464 | static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) |
| 1465 | { |
| 1466 | s32 status = 0; |
| 1467 | s32 i; |
| 1468 | u32 i2cctl; |
Rusty Russell | 3db1cd5 | 2011-12-19 13:56:45 +0000 | [diff] [blame] | 1469 | bool bit = false; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1470 | |
| 1471 | for (i = 7; i >= 0; i--) { |
| 1472 | bit = (data >> i) & 0x1; |
| 1473 | status = ixgbe_clock_out_i2c_bit(hw, bit); |
| 1474 | |
| 1475 | if (status != 0) |
| 1476 | break; |
| 1477 | } |
| 1478 | |
| 1479 | /* Release SDA line (set high) */ |
| 1480 | i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1481 | i2cctl |= IXGBE_I2C_DATA_OUT; |
| 1482 | IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, i2cctl); |
Emil Tantilov | 176f950 | 2011-11-04 06:43:23 +0000 | [diff] [blame] | 1483 | IXGBE_WRITE_FLUSH(hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1484 | |
| 1485 | return status; |
| 1486 | } |
| 1487 | |
| 1488 | /** |
| 1489 | * ixgbe_get_i2c_ack - Polls for I2C ACK |
| 1490 | * @hw: pointer to hardware structure |
| 1491 | * |
| 1492 | * Clocks in/out one bit via I2C data/clock |
| 1493 | **/ |
| 1494 | static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) |
| 1495 | { |
Emil Tantilov | e1befd7 | 2011-08-27 07:18:47 +0000 | [diff] [blame] | 1496 | s32 status = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1497 | u32 i = 0; |
| 1498 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1499 | u32 timeout = 10; |
Rusty Russell | 3db1cd5 | 2011-12-19 13:56:45 +0000 | [diff] [blame] | 1500 | bool ack = true; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1501 | |
Emil Tantilov | e1befd7 | 2011-08-27 07:18:47 +0000 | [diff] [blame] | 1502 | ixgbe_raise_i2c_clk(hw, &i2cctl); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1503 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1504 | |
| 1505 | /* Minimum high period of clock is 4us */ |
| 1506 | udelay(IXGBE_I2C_T_HIGH); |
| 1507 | |
| 1508 | /* Poll for ACK. Note that ACK in I2C spec is |
| 1509 | * transition from 1 to 0 */ |
| 1510 | for (i = 0; i < timeout; i++) { |
| 1511 | i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1512 | ack = ixgbe_get_i2c_data(&i2cctl); |
| 1513 | |
| 1514 | udelay(1); |
| 1515 | if (ack == 0) |
| 1516 | break; |
| 1517 | } |
| 1518 | |
| 1519 | if (ack == 1) { |
| 1520 | hw_dbg(hw, "I2C ack was not received.\n"); |
| 1521 | status = IXGBE_ERR_I2C; |
| 1522 | } |
| 1523 | |
| 1524 | ixgbe_lower_i2c_clk(hw, &i2cctl); |
| 1525 | |
| 1526 | /* Minimum low period of clock is 4.7 us */ |
| 1527 | udelay(IXGBE_I2C_T_LOW); |
| 1528 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1529 | return status; |
| 1530 | } |
| 1531 | |
| 1532 | /** |
| 1533 | * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock |
| 1534 | * @hw: pointer to hardware structure |
| 1535 | * @data: read data value |
| 1536 | * |
| 1537 | * Clocks in one bit via I2C data/clock |
| 1538 | **/ |
| 1539 | static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) |
| 1540 | { |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1541 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1542 | |
Emil Tantilov | e1befd7 | 2011-08-27 07:18:47 +0000 | [diff] [blame] | 1543 | ixgbe_raise_i2c_clk(hw, &i2cctl); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1544 | |
| 1545 | /* Minimum high period of clock is 4us */ |
| 1546 | udelay(IXGBE_I2C_T_HIGH); |
| 1547 | |
| 1548 | i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1549 | *data = ixgbe_get_i2c_data(&i2cctl); |
| 1550 | |
| 1551 | ixgbe_lower_i2c_clk(hw, &i2cctl); |
| 1552 | |
| 1553 | /* Minimum low period of clock is 4.7 us */ |
| 1554 | udelay(IXGBE_I2C_T_LOW); |
| 1555 | |
Emil Tantilov | e1befd7 | 2011-08-27 07:18:47 +0000 | [diff] [blame] | 1556 | return 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1557 | } |
| 1558 | |
| 1559 | /** |
| 1560 | * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock |
| 1561 | * @hw: pointer to hardware structure |
| 1562 | * @data: data value to write |
| 1563 | * |
| 1564 | * Clocks out one bit via I2C data/clock |
| 1565 | **/ |
| 1566 | static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) |
| 1567 | { |
| 1568 | s32 status; |
| 1569 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1570 | |
| 1571 | status = ixgbe_set_i2c_data(hw, &i2cctl, data); |
| 1572 | if (status == 0) { |
Emil Tantilov | e1befd7 | 2011-08-27 07:18:47 +0000 | [diff] [blame] | 1573 | ixgbe_raise_i2c_clk(hw, &i2cctl); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1574 | |
| 1575 | /* Minimum high period of clock is 4us */ |
| 1576 | udelay(IXGBE_I2C_T_HIGH); |
| 1577 | |
| 1578 | ixgbe_lower_i2c_clk(hw, &i2cctl); |
| 1579 | |
| 1580 | /* Minimum low period of clock is 4.7 us. |
| 1581 | * This also takes care of the data hold time. |
| 1582 | */ |
| 1583 | udelay(IXGBE_I2C_T_LOW); |
| 1584 | } else { |
| 1585 | status = IXGBE_ERR_I2C; |
| 1586 | hw_dbg(hw, "I2C data was not set to %X\n", data); |
| 1587 | } |
| 1588 | |
| 1589 | return status; |
| 1590 | } |
| 1591 | /** |
| 1592 | * ixgbe_raise_i2c_clk - Raises the I2C SCL clock |
| 1593 | * @hw: pointer to hardware structure |
| 1594 | * @i2cctl: Current value of I2CCTL register |
| 1595 | * |
| 1596 | * Raises the I2C clock line '0'->'1' |
| 1597 | **/ |
Emil Tantilov | e1befd7 | 2011-08-27 07:18:47 +0000 | [diff] [blame] | 1598 | static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1599 | { |
Don Skidmore | 8f56e4b | 2012-03-15 07:36:37 +0000 | [diff] [blame] | 1600 | u32 i = 0; |
| 1601 | u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; |
| 1602 | u32 i2cctl_r = 0; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1603 | |
Don Skidmore | 8f56e4b | 2012-03-15 07:36:37 +0000 | [diff] [blame] | 1604 | for (i = 0; i < timeout; i++) { |
| 1605 | *i2cctl |= IXGBE_I2C_CLK_OUT; |
| 1606 | IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); |
| 1607 | IXGBE_WRITE_FLUSH(hw); |
| 1608 | /* SCL rise time (1000ns) */ |
| 1609 | udelay(IXGBE_I2C_T_RISE); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1610 | |
Don Skidmore | 8f56e4b | 2012-03-15 07:36:37 +0000 | [diff] [blame] | 1611 | i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1612 | if (i2cctl_r & IXGBE_I2C_CLK_IN) |
| 1613 | break; |
| 1614 | } |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1615 | } |
| 1616 | |
| 1617 | /** |
| 1618 | * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock |
| 1619 | * @hw: pointer to hardware structure |
| 1620 | * @i2cctl: Current value of I2CCTL register |
| 1621 | * |
| 1622 | * Lowers the I2C clock line '1'->'0' |
| 1623 | **/ |
| 1624 | static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) |
| 1625 | { |
| 1626 | |
| 1627 | *i2cctl &= ~IXGBE_I2C_CLK_OUT; |
| 1628 | |
| 1629 | IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); |
Jesse Brandeburg | 945a515 | 2011-07-20 00:56:21 +0000 | [diff] [blame] | 1630 | IXGBE_WRITE_FLUSH(hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1631 | |
| 1632 | /* SCL fall time (300ns) */ |
| 1633 | udelay(IXGBE_I2C_T_FALL); |
| 1634 | } |
| 1635 | |
| 1636 | /** |
| 1637 | * ixgbe_set_i2c_data - Sets the I2C data bit |
| 1638 | * @hw: pointer to hardware structure |
| 1639 | * @i2cctl: Current value of I2CCTL register |
| 1640 | * @data: I2C data value (0 or 1) to set |
| 1641 | * |
| 1642 | * Sets the I2C data bit |
| 1643 | **/ |
| 1644 | static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) |
| 1645 | { |
| 1646 | s32 status = 0; |
| 1647 | |
| 1648 | if (data) |
| 1649 | *i2cctl |= IXGBE_I2C_DATA_OUT; |
| 1650 | else |
| 1651 | *i2cctl &= ~IXGBE_I2C_DATA_OUT; |
| 1652 | |
| 1653 | IXGBE_WRITE_REG(hw, IXGBE_I2CCTL, *i2cctl); |
Jesse Brandeburg | 945a515 | 2011-07-20 00:56:21 +0000 | [diff] [blame] | 1654 | IXGBE_WRITE_FLUSH(hw); |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1655 | |
| 1656 | /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ |
| 1657 | udelay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); |
| 1658 | |
| 1659 | /* Verify data was set correctly */ |
| 1660 | *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1661 | if (data != ixgbe_get_i2c_data(i2cctl)) { |
| 1662 | status = IXGBE_ERR_I2C; |
| 1663 | hw_dbg(hw, "Error - I2C data was not set to %X.\n", data); |
| 1664 | } |
| 1665 | |
| 1666 | return status; |
| 1667 | } |
| 1668 | |
| 1669 | /** |
| 1670 | * ixgbe_get_i2c_data - Reads the I2C SDA data bit |
| 1671 | * @hw: pointer to hardware structure |
| 1672 | * @i2cctl: Current value of I2CCTL register |
| 1673 | * |
| 1674 | * Returns the I2C data bit value |
| 1675 | **/ |
| 1676 | static bool ixgbe_get_i2c_data(u32 *i2cctl) |
| 1677 | { |
| 1678 | bool data; |
| 1679 | |
| 1680 | if (*i2cctl & IXGBE_I2C_DATA_IN) |
Rusty Russell | 3db1cd5 | 2011-12-19 13:56:45 +0000 | [diff] [blame] | 1681 | data = true; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1682 | else |
Rusty Russell | 3db1cd5 | 2011-12-19 13:56:45 +0000 | [diff] [blame] | 1683 | data = false; |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1684 | |
| 1685 | return data; |
| 1686 | } |
| 1687 | |
| 1688 | /** |
| 1689 | * ixgbe_i2c_bus_clear - Clears the I2C bus |
| 1690 | * @hw: pointer to hardware structure |
| 1691 | * |
| 1692 | * Clears the I2C bus by sending nine clock pulses. |
| 1693 | * Used when data line is stuck low. |
| 1694 | **/ |
| 1695 | static void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) |
| 1696 | { |
| 1697 | u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL); |
| 1698 | u32 i; |
| 1699 | |
Emil Tantilov | 75f19c3 | 2011-02-19 08:43:55 +0000 | [diff] [blame] | 1700 | ixgbe_i2c_start(hw); |
| 1701 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1702 | ixgbe_set_i2c_data(hw, &i2cctl, 1); |
| 1703 | |
| 1704 | for (i = 0; i < 9; i++) { |
| 1705 | ixgbe_raise_i2c_clk(hw, &i2cctl); |
| 1706 | |
| 1707 | /* Min high period of clock is 4us */ |
| 1708 | udelay(IXGBE_I2C_T_HIGH); |
| 1709 | |
| 1710 | ixgbe_lower_i2c_clk(hw, &i2cctl); |
| 1711 | |
| 1712 | /* Min low period of clock is 4.7us*/ |
| 1713 | udelay(IXGBE_I2C_T_LOW); |
| 1714 | } |
| 1715 | |
Emil Tantilov | 75f19c3 | 2011-02-19 08:43:55 +0000 | [diff] [blame] | 1716 | ixgbe_i2c_start(hw); |
| 1717 | |
PJ Waskiewicz | 11afc1b | 2009-02-27 15:44:30 +0000 | [diff] [blame] | 1718 | /* Put the i2c bus back to default state */ |
| 1719 | ixgbe_i2c_stop(hw); |
| 1720 | } |
| 1721 | |
| 1722 | /** |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 1723 | * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. |
Mallikarjuna R Chilakala | 119fc60 | 2010-05-20 23:07:06 -0700 | [diff] [blame] | 1724 | * @hw: pointer to hardware structure |
| 1725 | * |
| 1726 | * Checks if the LASI temp alarm status was triggered due to overtemp |
| 1727 | **/ |
| 1728 | s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) |
| 1729 | { |
| 1730 | s32 status = 0; |
| 1731 | u16 phy_data = 0; |
| 1732 | |
| 1733 | if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) |
| 1734 | goto out; |
| 1735 | |
| 1736 | /* Check that the LASI temp alarm status was triggered */ |
| 1737 | hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, |
| 1738 | MDIO_MMD_PMAPMD, &phy_data); |
| 1739 | |
| 1740 | if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) |
| 1741 | goto out; |
| 1742 | |
| 1743 | status = IXGBE_ERR_OVERTEMP; |
| 1744 | out: |
| 1745 | return status; |
| 1746 | } |