Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved. |
| 3 | * |
| 4 | * This software is available to you under a choice of one of two |
| 5 | * licenses. You may choose to be licensed under the terms of the GNU |
| 6 | * General Public License (GPL) Version 2, available from the file |
| 7 | * COPYING in the main directory of this source tree, or the |
| 8 | * OpenIB.org BSD license below: |
| 9 | * |
| 10 | * Redistribution and use in source and binary forms, with or |
| 11 | * without modification, are permitted provided that the following |
| 12 | * conditions are met: |
| 13 | * |
| 14 | * - Redistributions of source code must retain the above |
| 15 | * copyright notice, this list of conditions and the following |
| 16 | * disclaimer. |
| 17 | * - Redistributions in binary form must reproduce the above |
| 18 | * copyright notice, this list of conditions and the following |
| 19 | * disclaimer in the documentation and/or other materials |
| 20 | * provided with the distribution. |
| 21 | * |
| 22 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 23 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 24 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 25 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 26 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 27 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 28 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 29 | * SOFTWARE. |
| 30 | */ |
| 31 | #ifndef __IW_CXGB4_H__ |
| 32 | #define __IW_CXGB4_H__ |
| 33 | |
| 34 | #include <linux/mutex.h> |
| 35 | #include <linux/list.h> |
| 36 | #include <linux/spinlock.h> |
| 37 | #include <linux/idr.h> |
Steve Wise | c337374 | 2011-05-20 16:25:05 +0000 | [diff] [blame] | 38 | #include <linux/completion.h> |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 39 | #include <linux/netdevice.h> |
| 40 | #include <linux/sched.h> |
| 41 | #include <linux/pci.h> |
| 42 | #include <linux/dma-mapping.h> |
| 43 | #include <linux/inet.h> |
| 44 | #include <linux/wait.h> |
| 45 | #include <linux/kref.h> |
| 46 | #include <linux/timer.h> |
| 47 | #include <linux/io.h> |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 48 | |
| 49 | #include <asm/byteorder.h> |
| 50 | |
| 51 | #include <net/net_namespace.h> |
| 52 | |
| 53 | #include <rdma/ib_verbs.h> |
| 54 | #include <rdma/iw_cm.h> |
Steve Wise | 9eccfe1 | 2014-03-26 17:08:09 -0500 | [diff] [blame] | 55 | #include <rdma/rdma_netlink.h> |
| 56 | #include <rdma/iw_portmap.h> |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 57 | |
| 58 | #include "cxgb4.h" |
| 59 | #include "cxgb4_uld.h" |
| 60 | #include "l2t.h" |
| 61 | #include "user.h" |
| 62 | |
| 63 | #define DRV_NAME "iw_cxgb4" |
| 64 | #define MOD DRV_NAME ":" |
| 65 | |
| 66 | extern int c4iw_debug; |
| 67 | #define PDBG(fmt, args...) \ |
| 68 | do { \ |
| 69 | if (c4iw_debug) \ |
| 70 | printk(MOD fmt, ## args); \ |
| 71 | } while (0) |
| 72 | |
| 73 | #include "t4.h" |
| 74 | |
| 75 | #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->pbl.start) |
| 76 | #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->lldi.vr->rq.start) |
| 77 | |
| 78 | static inline void *cplhdr(struct sk_buff *skb) |
| 79 | { |
| 80 | return skb->data; |
| 81 | } |
| 82 | |
Vipul Pandya | ec3eead | 2012-05-18 15:29:32 +0530 | [diff] [blame] | 83 | #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */ |
| 84 | #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */ |
| 85 | |
| 86 | struct c4iw_id_table { |
| 87 | u32 flags; |
| 88 | u32 start; /* logical minimal id */ |
| 89 | u32 last; /* hint for find */ |
| 90 | u32 max; |
| 91 | spinlock_t lock; |
| 92 | unsigned long *table; |
| 93 | }; |
| 94 | |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 95 | struct c4iw_resource { |
Vipul Pandya | ec3eead | 2012-05-18 15:29:32 +0530 | [diff] [blame] | 96 | struct c4iw_id_table tpt_table; |
| 97 | struct c4iw_id_table qid_table; |
| 98 | struct c4iw_id_table pdid_table; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 99 | }; |
| 100 | |
| 101 | struct c4iw_qid_list { |
| 102 | struct list_head entry; |
| 103 | u32 qid; |
| 104 | }; |
| 105 | |
| 106 | struct c4iw_dev_ucontext { |
| 107 | struct list_head qpids; |
| 108 | struct list_head cqids; |
| 109 | struct mutex lock; |
| 110 | }; |
| 111 | |
| 112 | enum c4iw_rdev_flags { |
| 113 | T4_FATAL_ERROR = (1<<0), |
Steve Wise | 05eb238 | 2014-03-14 21:52:08 +0530 | [diff] [blame] | 114 | T4_STATUS_PAGE_DISABLED = (1<<1), |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 115 | }; |
| 116 | |
Vipul Pandya | 8d81ef3 | 2012-05-18 15:29:27 +0530 | [diff] [blame] | 117 | struct c4iw_stat { |
| 118 | u64 total; |
| 119 | u64 cur; |
| 120 | u64 max; |
Vipul Pandya | ec3eead | 2012-05-18 15:29:32 +0530 | [diff] [blame] | 121 | u64 fail; |
Vipul Pandya | 8d81ef3 | 2012-05-18 15:29:27 +0530 | [diff] [blame] | 122 | }; |
| 123 | |
| 124 | struct c4iw_stats { |
| 125 | struct mutex lock; |
| 126 | struct c4iw_stat qid; |
| 127 | struct c4iw_stat pd; |
| 128 | struct c4iw_stat stag; |
| 129 | struct c4iw_stat pbl; |
| 130 | struct c4iw_stat rqt; |
| 131 | struct c4iw_stat ocqp; |
Vipul Pandya | 2c97478 | 2012-05-18 15:29:28 +0530 | [diff] [blame] | 132 | u64 db_full; |
| 133 | u64 db_empty; |
| 134 | u64 db_drop; |
Vipul Pandya | 422eea0 | 2012-05-18 15:29:30 +0530 | [diff] [blame] | 135 | u64 db_state_transitions; |
Steve Wise | 05eb238 | 2014-03-14 21:52:08 +0530 | [diff] [blame] | 136 | u64 db_fc_interruptions; |
Vipul Pandya | 5be78ee | 2012-12-10 09:30:54 +0000 | [diff] [blame] | 137 | u64 tcam_full; |
Vipul Pandya | 793dad9 | 2012-12-10 09:30:56 +0000 | [diff] [blame] | 138 | u64 act_ofld_conn_fails; |
| 139 | u64 pas_ofld_conn_fails; |
Vipul Pandya | 8d81ef3 | 2012-05-18 15:29:27 +0530 | [diff] [blame] | 140 | }; |
| 141 | |
Hariprasad Shenai | 04e10e2 | 2014-07-14 21:34:51 +0530 | [diff] [blame^] | 142 | struct c4iw_hw_queue { |
| 143 | int t4_eq_status_entries; |
| 144 | int t4_max_eq_size; |
| 145 | int t4_max_iq_size; |
| 146 | int t4_max_rq_size; |
| 147 | int t4_max_sq_size; |
| 148 | int t4_max_qp_depth; |
| 149 | int t4_max_cq_depth; |
| 150 | int t4_stat_len; |
| 151 | }; |
| 152 | |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 153 | struct c4iw_rdev { |
| 154 | struct c4iw_resource resource; |
| 155 | unsigned long qpshift; |
| 156 | u32 qpmask; |
| 157 | unsigned long cqshift; |
| 158 | u32 cqmask; |
| 159 | struct c4iw_dev_ucontext uctx; |
| 160 | struct gen_pool *pbl_pool; |
| 161 | struct gen_pool *rqt_pool; |
Steve Wise | c6d7b26 | 2010-09-13 11:23:57 -0500 | [diff] [blame] | 162 | struct gen_pool *ocqp_pool; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 163 | u32 flags; |
| 164 | struct cxgb4_lld_info lldi; |
Steve Wise | fa658a9 | 2014-04-09 09:38:25 -0500 | [diff] [blame] | 165 | unsigned long bar2_pa; |
| 166 | void __iomem *bar2_kva; |
Steve Wise | c6d7b26 | 2010-09-13 11:23:57 -0500 | [diff] [blame] | 167 | unsigned long oc_mw_pa; |
| 168 | void __iomem *oc_mw_kva; |
Vipul Pandya | 8d81ef3 | 2012-05-18 15:29:27 +0530 | [diff] [blame] | 169 | struct c4iw_stats stats; |
Hariprasad Shenai | 04e10e2 | 2014-07-14 21:34:51 +0530 | [diff] [blame^] | 170 | struct c4iw_hw_queue hw_queue; |
Steve Wise | 05eb238 | 2014-03-14 21:52:08 +0530 | [diff] [blame] | 171 | struct t4_dev_status_page *status_page; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 172 | }; |
| 173 | |
| 174 | static inline int c4iw_fatal_error(struct c4iw_rdev *rdev) |
| 175 | { |
| 176 | return rdev->flags & T4_FATAL_ERROR; |
| 177 | } |
| 178 | |
| 179 | static inline int c4iw_num_stags(struct c4iw_rdev *rdev) |
| 180 | { |
| 181 | return min((int)T4_MAX_NUM_STAG, (int)(rdev->lldi.vr->stag.size >> 5)); |
| 182 | } |
| 183 | |
Vipul Pandya | 3b174d9 | 2013-03-14 05:09:03 +0000 | [diff] [blame] | 184 | #define C4IW_WR_TO (30*HZ) |
Steve Wise | aadc4df | 2010-09-10 11:15:25 -0500 | [diff] [blame] | 185 | |
| 186 | struct c4iw_wr_wait { |
Steve Wise | c337374 | 2011-05-20 16:25:05 +0000 | [diff] [blame] | 187 | struct completion completion; |
Steve Wise | aadc4df | 2010-09-10 11:15:25 -0500 | [diff] [blame] | 188 | int ret; |
| 189 | }; |
| 190 | |
| 191 | static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp) |
| 192 | { |
| 193 | wr_waitp->ret = 0; |
Steve Wise | c337374 | 2011-05-20 16:25:05 +0000 | [diff] [blame] | 194 | init_completion(&wr_waitp->completion); |
Steve Wise | aadc4df | 2010-09-10 11:15:25 -0500 | [diff] [blame] | 195 | } |
| 196 | |
Steve Wise | d9594d9 | 2011-05-09 22:06:22 -0700 | [diff] [blame] | 197 | static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret) |
| 198 | { |
| 199 | wr_waitp->ret = ret; |
Steve Wise | c337374 | 2011-05-20 16:25:05 +0000 | [diff] [blame] | 200 | complete(&wr_waitp->completion); |
Steve Wise | d9594d9 | 2011-05-09 22:06:22 -0700 | [diff] [blame] | 201 | } |
| 202 | |
Steve Wise | aadc4df | 2010-09-10 11:15:25 -0500 | [diff] [blame] | 203 | static inline int c4iw_wait_for_reply(struct c4iw_rdev *rdev, |
| 204 | struct c4iw_wr_wait *wr_waitp, |
| 205 | u32 hwtid, u32 qpid, |
| 206 | const char *func) |
| 207 | { |
| 208 | unsigned to = C4IW_WR_TO; |
Steve Wise | d9594d9 | 2011-05-09 22:06:22 -0700 | [diff] [blame] | 209 | int ret; |
Steve Wise | aadc4df | 2010-09-10 11:15:25 -0500 | [diff] [blame] | 210 | |
Steve Wise | d9594d9 | 2011-05-09 22:06:22 -0700 | [diff] [blame] | 211 | do { |
Steve Wise | c337374 | 2011-05-20 16:25:05 +0000 | [diff] [blame] | 212 | ret = wait_for_completion_timeout(&wr_waitp->completion, to); |
Steve Wise | d9594d9 | 2011-05-09 22:06:22 -0700 | [diff] [blame] | 213 | if (!ret) { |
Steve Wise | aadc4df | 2010-09-10 11:15:25 -0500 | [diff] [blame] | 214 | printk(KERN_ERR MOD "%s - Device %s not responding - " |
| 215 | "tid %u qpid %u\n", func, |
| 216 | pci_name(rdev->lldi.pdev), hwtid, qpid); |
Steve Wise | 2f25e9a | 2011-05-09 22:06:23 -0700 | [diff] [blame] | 217 | if (c4iw_fatal_error(rdev)) { |
| 218 | wr_waitp->ret = -EIO; |
| 219 | break; |
| 220 | } |
Steve Wise | aadc4df | 2010-09-10 11:15:25 -0500 | [diff] [blame] | 221 | to = to << 2; |
| 222 | } |
Steve Wise | d9594d9 | 2011-05-09 22:06:22 -0700 | [diff] [blame] | 223 | } while (!ret); |
Steve Wise | aadc4df | 2010-09-10 11:15:25 -0500 | [diff] [blame] | 224 | if (wr_waitp->ret) |
Steve Wise | 30c95c2 | 2011-05-09 22:06:22 -0700 | [diff] [blame] | 225 | PDBG("%s: FW reply %d tid %u qpid %u\n", |
| 226 | pci_name(rdev->lldi.pdev), wr_waitp->ret, hwtid, qpid); |
Steve Wise | aadc4df | 2010-09-10 11:15:25 -0500 | [diff] [blame] | 227 | return wr_waitp->ret; |
| 228 | } |
| 229 | |
Vipul Pandya | 2c97478 | 2012-05-18 15:29:28 +0530 | [diff] [blame] | 230 | enum db_state { |
| 231 | NORMAL = 0, |
| 232 | FLOW_CONTROL = 1, |
Steve Wise | 05eb238 | 2014-03-14 21:52:08 +0530 | [diff] [blame] | 233 | RECOVERY = 2, |
| 234 | STOPPED = 3 |
Vipul Pandya | 2c97478 | 2012-05-18 15:29:28 +0530 | [diff] [blame] | 235 | }; |
| 236 | |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 237 | struct c4iw_dev { |
| 238 | struct ib_device ibdev; |
| 239 | struct c4iw_rdev rdev; |
| 240 | u32 device_cap_flags; |
| 241 | struct idr cqidr; |
| 242 | struct idr qpidr; |
| 243 | struct idr mmidr; |
| 244 | spinlock_t lock; |
Vipul Pandya | 2c97478 | 2012-05-18 15:29:28 +0530 | [diff] [blame] | 245 | struct mutex db_mutex; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 246 | struct dentry *debugfs_root; |
Vipul Pandya | 2c97478 | 2012-05-18 15:29:28 +0530 | [diff] [blame] | 247 | enum db_state db_state; |
Vipul Pandya | 793dad9 | 2012-12-10 09:30:56 +0000 | [diff] [blame] | 248 | struct idr hwtid_idr; |
| 249 | struct idr atid_idr; |
| 250 | struct idr stid_idr; |
Steve Wise | 05eb238 | 2014-03-14 21:52:08 +0530 | [diff] [blame] | 251 | struct list_head db_fc_list; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 252 | }; |
| 253 | |
| 254 | static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev) |
| 255 | { |
| 256 | return container_of(ibdev, struct c4iw_dev, ibdev); |
| 257 | } |
| 258 | |
| 259 | static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev) |
| 260 | { |
| 261 | return container_of(rdev, struct c4iw_dev, rdev); |
| 262 | } |
| 263 | |
| 264 | static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid) |
| 265 | { |
| 266 | return idr_find(&rhp->cqidr, cqid); |
| 267 | } |
| 268 | |
| 269 | static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid) |
| 270 | { |
| 271 | return idr_find(&rhp->qpidr, qpid); |
| 272 | } |
| 273 | |
| 274 | static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid) |
| 275 | { |
| 276 | return idr_find(&rhp->mmidr, mmid); |
| 277 | } |
| 278 | |
Vipul Pandya | 2c97478 | 2012-05-18 15:29:28 +0530 | [diff] [blame] | 279 | static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr, |
| 280 | void *handle, u32 id, int lock) |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 281 | { |
| 282 | int ret; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 283 | |
Tejun Heo | e8d4dd6 | 2013-02-27 17:04:20 -0800 | [diff] [blame] | 284 | if (lock) { |
| 285 | idr_preload(GFP_KERNEL); |
| 286 | spin_lock_irq(&rhp->lock); |
| 287 | } |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 288 | |
Tejun Heo | e8d4dd6 | 2013-02-27 17:04:20 -0800 | [diff] [blame] | 289 | ret = idr_alloc(idr, handle, id, id + 1, GFP_ATOMIC); |
| 290 | |
| 291 | if (lock) { |
| 292 | spin_unlock_irq(&rhp->lock); |
| 293 | idr_preload_end(); |
| 294 | } |
| 295 | |
| 296 | BUG_ON(ret == -ENOSPC); |
| 297 | return ret < 0 ? ret : 0; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 298 | } |
| 299 | |
Vipul Pandya | 2c97478 | 2012-05-18 15:29:28 +0530 | [diff] [blame] | 300 | static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr, |
| 301 | void *handle, u32 id) |
| 302 | { |
| 303 | return _insert_handle(rhp, idr, handle, id, 1); |
| 304 | } |
| 305 | |
| 306 | static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr, |
| 307 | void *handle, u32 id) |
| 308 | { |
| 309 | return _insert_handle(rhp, idr, handle, id, 0); |
| 310 | } |
| 311 | |
Vipul Pandya | 422eea0 | 2012-05-18 15:29:30 +0530 | [diff] [blame] | 312 | static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr, |
| 313 | u32 id, int lock) |
| 314 | { |
| 315 | if (lock) |
| 316 | spin_lock_irq(&rhp->lock); |
| 317 | idr_remove(idr, id); |
| 318 | if (lock) |
| 319 | spin_unlock_irq(&rhp->lock); |
| 320 | } |
| 321 | |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 322 | static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id) |
| 323 | { |
Vipul Pandya | 422eea0 | 2012-05-18 15:29:30 +0530 | [diff] [blame] | 324 | _remove_handle(rhp, idr, id, 1); |
| 325 | } |
| 326 | |
| 327 | static inline void remove_handle_nolock(struct c4iw_dev *rhp, |
| 328 | struct idr *idr, u32 id) |
| 329 | { |
| 330 | _remove_handle(rhp, idr, id, 0); |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 331 | } |
| 332 | |
| 333 | struct c4iw_pd { |
| 334 | struct ib_pd ibpd; |
| 335 | u32 pdid; |
| 336 | struct c4iw_dev *rhp; |
| 337 | }; |
| 338 | |
| 339 | static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd) |
| 340 | { |
| 341 | return container_of(ibpd, struct c4iw_pd, ibpd); |
| 342 | } |
| 343 | |
| 344 | struct tpt_attributes { |
| 345 | u64 len; |
| 346 | u64 va_fbo; |
| 347 | enum fw_ri_mem_perms perms; |
| 348 | u32 stag; |
| 349 | u32 pdid; |
| 350 | u32 qpid; |
| 351 | u32 pbl_addr; |
| 352 | u32 pbl_size; |
| 353 | u32 state:1; |
| 354 | u32 type:2; |
| 355 | u32 rsvd:1; |
| 356 | u32 remote_invaliate_disable:1; |
| 357 | u32 zbva:1; |
| 358 | u32 mw_bind_enable:1; |
| 359 | u32 page_size:5; |
| 360 | }; |
| 361 | |
| 362 | struct c4iw_mr { |
| 363 | struct ib_mr ibmr; |
| 364 | struct ib_umem *umem; |
| 365 | struct c4iw_dev *rhp; |
| 366 | u64 kva; |
| 367 | struct tpt_attributes attr; |
| 368 | }; |
| 369 | |
| 370 | static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr) |
| 371 | { |
| 372 | return container_of(ibmr, struct c4iw_mr, ibmr); |
| 373 | } |
| 374 | |
| 375 | struct c4iw_mw { |
| 376 | struct ib_mw ibmw; |
| 377 | struct c4iw_dev *rhp; |
| 378 | u64 kva; |
| 379 | struct tpt_attributes attr; |
| 380 | }; |
| 381 | |
| 382 | static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw) |
| 383 | { |
| 384 | return container_of(ibmw, struct c4iw_mw, ibmw); |
| 385 | } |
| 386 | |
| 387 | struct c4iw_fr_page_list { |
| 388 | struct ib_fast_reg_page_list ibpl; |
FUJITA Tomonori | f38926a | 2010-06-03 05:37:50 +0000 | [diff] [blame] | 389 | DEFINE_DMA_UNMAP_ADDR(mapping); |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 390 | dma_addr_t dma_addr; |
| 391 | struct c4iw_dev *dev; |
Steve Wise | eda6d1d | 2014-03-19 17:44:45 +0530 | [diff] [blame] | 392 | int pll_len; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 393 | }; |
| 394 | |
| 395 | static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list( |
| 396 | struct ib_fast_reg_page_list *ibpl) |
| 397 | { |
| 398 | return container_of(ibpl, struct c4iw_fr_page_list, ibpl); |
| 399 | } |
| 400 | |
| 401 | struct c4iw_cq { |
| 402 | struct ib_cq ibcq; |
| 403 | struct c4iw_dev *rhp; |
| 404 | struct t4_cq cq; |
| 405 | spinlock_t lock; |
Kumar Sanghvi | 581bbe2 | 2011-10-24 21:20:21 +0530 | [diff] [blame] | 406 | spinlock_t comp_handler_lock; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 407 | atomic_t refcnt; |
| 408 | wait_queue_head_t wait; |
| 409 | }; |
| 410 | |
| 411 | static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq) |
| 412 | { |
| 413 | return container_of(ibcq, struct c4iw_cq, ibcq); |
| 414 | } |
| 415 | |
| 416 | struct c4iw_mpa_attributes { |
| 417 | u8 initiator; |
| 418 | u8 recv_marker_enabled; |
| 419 | u8 xmit_marker_enabled; |
| 420 | u8 crc_enabled; |
Kumar Sanghvi | d2fe99e | 2011-09-25 20:17:44 +0530 | [diff] [blame] | 421 | u8 enhanced_rdma_conn; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 422 | u8 version; |
| 423 | u8 p2p_type; |
| 424 | }; |
| 425 | |
| 426 | struct c4iw_qp_attributes { |
| 427 | u32 scq; |
| 428 | u32 rcq; |
| 429 | u32 sq_num_entries; |
| 430 | u32 rq_num_entries; |
| 431 | u32 sq_max_sges; |
| 432 | u32 sq_max_sges_rdma_write; |
| 433 | u32 rq_max_sges; |
| 434 | u32 state; |
| 435 | u8 enable_rdma_read; |
| 436 | u8 enable_rdma_write; |
| 437 | u8 enable_bind; |
| 438 | u8 enable_mmid0_fastreg; |
| 439 | u32 max_ord; |
| 440 | u32 max_ird; |
| 441 | u32 pd; |
| 442 | u32 next_state; |
| 443 | char terminate_buffer[52]; |
| 444 | u32 terminate_msg_len; |
| 445 | u8 is_terminate_local; |
| 446 | struct c4iw_mpa_attributes mpa_attr; |
| 447 | struct c4iw_ep *llp_stream_handle; |
Kumar Sanghvi | d2fe99e | 2011-09-25 20:17:44 +0530 | [diff] [blame] | 448 | u8 layer_etype; |
| 449 | u8 ecode; |
Vipul Pandya | 2c97478 | 2012-05-18 15:29:28 +0530 | [diff] [blame] | 450 | u16 sq_db_inc; |
| 451 | u16 rq_db_inc; |
Steve Wise | cc18b93 | 2014-04-24 14:31:53 -0500 | [diff] [blame] | 452 | u8 send_term; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 453 | }; |
| 454 | |
| 455 | struct c4iw_qp { |
| 456 | struct ib_qp ibqp; |
Steve Wise | 05eb238 | 2014-03-14 21:52:08 +0530 | [diff] [blame] | 457 | struct list_head db_fc_entry; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 458 | struct c4iw_dev *rhp; |
| 459 | struct c4iw_ep *ep; |
| 460 | struct c4iw_qp_attributes attr; |
| 461 | struct t4_wq wq; |
| 462 | spinlock_t lock; |
Steve Wise | 2f5b48c | 2010-09-10 11:15:36 -0500 | [diff] [blame] | 463 | struct mutex mutex; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 464 | atomic_t refcnt; |
| 465 | wait_queue_head_t wait; |
| 466 | struct timer_list timer; |
Steve Wise | ba32de9 | 2014-03-19 17:44:43 +0530 | [diff] [blame] | 467 | int sq_sig_all; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 468 | }; |
| 469 | |
| 470 | static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp) |
| 471 | { |
| 472 | return container_of(ibqp, struct c4iw_qp, ibqp); |
| 473 | } |
| 474 | |
| 475 | struct c4iw_ucontext { |
| 476 | struct ib_ucontext ibucontext; |
| 477 | struct c4iw_dev_ucontext uctx; |
| 478 | u32 key; |
| 479 | spinlock_t mmap_lock; |
| 480 | struct list_head mmaps; |
| 481 | }; |
| 482 | |
| 483 | static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c) |
| 484 | { |
| 485 | return container_of(c, struct c4iw_ucontext, ibucontext); |
| 486 | } |
| 487 | |
| 488 | struct c4iw_mm_entry { |
| 489 | struct list_head entry; |
| 490 | u64 addr; |
| 491 | u32 key; |
| 492 | unsigned len; |
| 493 | }; |
| 494 | |
| 495 | static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext, |
| 496 | u32 key, unsigned len) |
| 497 | { |
| 498 | struct list_head *pos, *nxt; |
| 499 | struct c4iw_mm_entry *mm; |
| 500 | |
| 501 | spin_lock(&ucontext->mmap_lock); |
| 502 | list_for_each_safe(pos, nxt, &ucontext->mmaps) { |
| 503 | |
| 504 | mm = list_entry(pos, struct c4iw_mm_entry, entry); |
| 505 | if (mm->key == key && mm->len == len) { |
| 506 | list_del_init(&mm->entry); |
| 507 | spin_unlock(&ucontext->mmap_lock); |
| 508 | PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__, |
| 509 | key, (unsigned long long) mm->addr, mm->len); |
| 510 | return mm; |
| 511 | } |
| 512 | } |
| 513 | spin_unlock(&ucontext->mmap_lock); |
| 514 | return NULL; |
| 515 | } |
| 516 | |
| 517 | static inline void insert_mmap(struct c4iw_ucontext *ucontext, |
| 518 | struct c4iw_mm_entry *mm) |
| 519 | { |
| 520 | spin_lock(&ucontext->mmap_lock); |
| 521 | PDBG("%s key 0x%x addr 0x%llx len %d\n", __func__, |
| 522 | mm->key, (unsigned long long) mm->addr, mm->len); |
| 523 | list_add_tail(&mm->entry, &ucontext->mmaps); |
| 524 | spin_unlock(&ucontext->mmap_lock); |
| 525 | } |
| 526 | |
| 527 | enum c4iw_qp_attr_mask { |
| 528 | C4IW_QP_ATTR_NEXT_STATE = 1 << 0, |
Vipul Pandya | 2c97478 | 2012-05-18 15:29:28 +0530 | [diff] [blame] | 529 | C4IW_QP_ATTR_SQ_DB = 1<<1, |
| 530 | C4IW_QP_ATTR_RQ_DB = 1<<2, |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 531 | C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7, |
| 532 | C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8, |
| 533 | C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9, |
| 534 | C4IW_QP_ATTR_MAX_ORD = 1 << 11, |
| 535 | C4IW_QP_ATTR_MAX_IRD = 1 << 12, |
| 536 | C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22, |
| 537 | C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23, |
| 538 | C4IW_QP_ATTR_MPA_ATTR = 1 << 24, |
| 539 | C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25, |
| 540 | C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ | |
| 541 | C4IW_QP_ATTR_ENABLE_RDMA_WRITE | |
| 542 | C4IW_QP_ATTR_MAX_ORD | |
| 543 | C4IW_QP_ATTR_MAX_IRD | |
| 544 | C4IW_QP_ATTR_LLP_STREAM_HANDLE | |
| 545 | C4IW_QP_ATTR_STREAM_MSG_BUFFER | |
| 546 | C4IW_QP_ATTR_MPA_ATTR | |
| 547 | C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE) |
| 548 | }; |
| 549 | |
| 550 | int c4iw_modify_qp(struct c4iw_dev *rhp, |
| 551 | struct c4iw_qp *qhp, |
| 552 | enum c4iw_qp_attr_mask mask, |
| 553 | struct c4iw_qp_attributes *attrs, |
| 554 | int internal); |
| 555 | |
| 556 | enum c4iw_qp_state { |
| 557 | C4IW_QP_STATE_IDLE, |
| 558 | C4IW_QP_STATE_RTS, |
| 559 | C4IW_QP_STATE_ERROR, |
| 560 | C4IW_QP_STATE_TERMINATE, |
| 561 | C4IW_QP_STATE_CLOSING, |
| 562 | C4IW_QP_STATE_TOT |
| 563 | }; |
| 564 | |
| 565 | static inline int c4iw_convert_state(enum ib_qp_state ib_state) |
| 566 | { |
| 567 | switch (ib_state) { |
| 568 | case IB_QPS_RESET: |
| 569 | case IB_QPS_INIT: |
| 570 | return C4IW_QP_STATE_IDLE; |
| 571 | case IB_QPS_RTS: |
| 572 | return C4IW_QP_STATE_RTS; |
| 573 | case IB_QPS_SQD: |
| 574 | return C4IW_QP_STATE_CLOSING; |
| 575 | case IB_QPS_SQE: |
| 576 | return C4IW_QP_STATE_TERMINATE; |
| 577 | case IB_QPS_ERR: |
| 578 | return C4IW_QP_STATE_ERROR; |
| 579 | default: |
| 580 | return -1; |
| 581 | } |
| 582 | } |
| 583 | |
Vipul Pandya | 67bbc05 | 2012-05-18 15:29:33 +0530 | [diff] [blame] | 584 | static inline int to_ib_qp_state(int c4iw_qp_state) |
| 585 | { |
| 586 | switch (c4iw_qp_state) { |
| 587 | case C4IW_QP_STATE_IDLE: |
| 588 | return IB_QPS_INIT; |
| 589 | case C4IW_QP_STATE_RTS: |
| 590 | return IB_QPS_RTS; |
| 591 | case C4IW_QP_STATE_CLOSING: |
| 592 | return IB_QPS_SQD; |
| 593 | case C4IW_QP_STATE_TERMINATE: |
| 594 | return IB_QPS_SQE; |
| 595 | case C4IW_QP_STATE_ERROR: |
| 596 | return IB_QPS_ERR; |
| 597 | } |
| 598 | return IB_QPS_ERR; |
| 599 | } |
| 600 | |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 601 | static inline u32 c4iw_ib_to_tpt_access(int a) |
| 602 | { |
| 603 | return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | |
| 604 | (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) | |
| 605 | (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) | |
| 606 | FW_RI_MEM_ACCESS_LOCAL_READ; |
| 607 | } |
| 608 | |
| 609 | static inline u32 c4iw_ib_to_tpt_bind_access(int acc) |
| 610 | { |
| 611 | return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) | |
| 612 | (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0); |
| 613 | } |
| 614 | |
| 615 | enum c4iw_mmid_state { |
| 616 | C4IW_STAG_STATE_VALID, |
| 617 | C4IW_STAG_STATE_INVALID |
| 618 | }; |
| 619 | |
| 620 | #define C4IW_NODE_DESC "cxgb4 Chelsio Communications" |
| 621 | |
| 622 | #define MPA_KEY_REQ "MPA ID Req Frame" |
| 623 | #define MPA_KEY_REP "MPA ID Rep Frame" |
| 624 | |
| 625 | #define MPA_MAX_PRIVATE_DATA 256 |
Kumar Sanghvi | d2fe99e | 2011-09-25 20:17:44 +0530 | [diff] [blame] | 626 | #define MPA_ENHANCED_RDMA_CONN 0x10 |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 627 | #define MPA_REJECT 0x20 |
| 628 | #define MPA_CRC 0x40 |
| 629 | #define MPA_MARKERS 0x80 |
| 630 | #define MPA_FLAGS_MASK 0xE0 |
| 631 | |
Kumar Sanghvi | d2fe99e | 2011-09-25 20:17:44 +0530 | [diff] [blame] | 632 | #define MPA_V2_PEER2PEER_MODEL 0x8000 |
| 633 | #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000 |
| 634 | #define MPA_V2_RDMA_WRITE_RTR 0x8000 |
| 635 | #define MPA_V2_RDMA_READ_RTR 0x4000 |
| 636 | #define MPA_V2_IRD_ORD_MASK 0x3FFF |
| 637 | |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 638 | #define c4iw_put_ep(ep) { \ |
| 639 | PDBG("put_ep (via %s:%u) ep %p refcnt %d\n", __func__, __LINE__, \ |
| 640 | ep, atomic_read(&((ep)->kref.refcount))); \ |
| 641 | WARN_ON(atomic_read(&((ep)->kref.refcount)) < 1); \ |
| 642 | kref_put(&((ep)->kref), _c4iw_free_ep); \ |
| 643 | } |
| 644 | |
| 645 | #define c4iw_get_ep(ep) { \ |
| 646 | PDBG("get_ep (via %s:%u) ep %p, refcnt %d\n", __func__, __LINE__, \ |
| 647 | ep, atomic_read(&((ep)->kref.refcount))); \ |
| 648 | kref_get(&((ep)->kref)); \ |
| 649 | } |
| 650 | void _c4iw_free_ep(struct kref *kref); |
| 651 | |
| 652 | struct mpa_message { |
| 653 | u8 key[16]; |
| 654 | u8 flags; |
| 655 | u8 revision; |
| 656 | __be16 private_data_size; |
| 657 | u8 private_data[0]; |
| 658 | }; |
| 659 | |
Kumar Sanghvi | d2fe99e | 2011-09-25 20:17:44 +0530 | [diff] [blame] | 660 | struct mpa_v2_conn_params { |
| 661 | __be16 ird; |
| 662 | __be16 ord; |
| 663 | }; |
| 664 | |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 665 | struct terminate_message { |
| 666 | u8 layer_etype; |
| 667 | u8 ecode; |
| 668 | __be16 hdrct_rsvd; |
| 669 | u8 len_hdrs[0]; |
| 670 | }; |
| 671 | |
| 672 | #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28) |
| 673 | |
| 674 | enum c4iw_layers_types { |
| 675 | LAYER_RDMAP = 0x00, |
| 676 | LAYER_DDP = 0x10, |
| 677 | LAYER_MPA = 0x20, |
| 678 | RDMAP_LOCAL_CATA = 0x00, |
| 679 | RDMAP_REMOTE_PROT = 0x01, |
| 680 | RDMAP_REMOTE_OP = 0x02, |
| 681 | DDP_LOCAL_CATA = 0x00, |
| 682 | DDP_TAGGED_ERR = 0x01, |
| 683 | DDP_UNTAGGED_ERR = 0x02, |
| 684 | DDP_LLP = 0x03 |
| 685 | }; |
| 686 | |
| 687 | enum c4iw_rdma_ecodes { |
| 688 | RDMAP_INV_STAG = 0x00, |
| 689 | RDMAP_BASE_BOUNDS = 0x01, |
| 690 | RDMAP_ACC_VIOL = 0x02, |
| 691 | RDMAP_STAG_NOT_ASSOC = 0x03, |
| 692 | RDMAP_TO_WRAP = 0x04, |
| 693 | RDMAP_INV_VERS = 0x05, |
| 694 | RDMAP_INV_OPCODE = 0x06, |
| 695 | RDMAP_STREAM_CATA = 0x07, |
| 696 | RDMAP_GLOBAL_CATA = 0x08, |
| 697 | RDMAP_CANT_INV_STAG = 0x09, |
| 698 | RDMAP_UNSPECIFIED = 0xff |
| 699 | }; |
| 700 | |
| 701 | enum c4iw_ddp_ecodes { |
| 702 | DDPT_INV_STAG = 0x00, |
| 703 | DDPT_BASE_BOUNDS = 0x01, |
| 704 | DDPT_STAG_NOT_ASSOC = 0x02, |
| 705 | DDPT_TO_WRAP = 0x03, |
| 706 | DDPT_INV_VERS = 0x04, |
| 707 | DDPU_INV_QN = 0x01, |
| 708 | DDPU_INV_MSN_NOBUF = 0x02, |
| 709 | DDPU_INV_MSN_RANGE = 0x03, |
| 710 | DDPU_INV_MO = 0x04, |
| 711 | DDPU_MSG_TOOBIG = 0x05, |
| 712 | DDPU_INV_VERS = 0x06 |
| 713 | }; |
| 714 | |
| 715 | enum c4iw_mpa_ecodes { |
| 716 | MPA_CRC_ERR = 0x02, |
Kumar Sanghvi | d2fe99e | 2011-09-25 20:17:44 +0530 | [diff] [blame] | 717 | MPA_MARKER_ERR = 0x03, |
| 718 | MPA_LOCAL_CATA = 0x05, |
| 719 | MPA_INSUFF_IRD = 0x06, |
| 720 | MPA_NOMATCH_RTR = 0x07, |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 721 | }; |
| 722 | |
| 723 | enum c4iw_ep_state { |
| 724 | IDLE = 0, |
| 725 | LISTEN, |
| 726 | CONNECTING, |
| 727 | MPA_REQ_WAIT, |
| 728 | MPA_REQ_SENT, |
| 729 | MPA_REQ_RCVD, |
| 730 | MPA_REP_SENT, |
| 731 | FPDU_MODE, |
| 732 | ABORTING, |
| 733 | CLOSING, |
| 734 | MORIBUND, |
| 735 | DEAD, |
| 736 | }; |
| 737 | |
| 738 | enum c4iw_ep_flags { |
| 739 | PEER_ABORT_IN_PROGRESS = 0, |
| 740 | ABORT_REQ_IN_PROGRESS = 1, |
| 741 | RELEASE_RESOURCES = 2, |
| 742 | CLOSE_SENT = 3, |
Vipul Pandya | 1ec779c | 2013-01-07 13:11:56 +0000 | [diff] [blame] | 743 | TIMEOUT = 4, |
Vipul Pandya | 325abea | 2013-01-07 13:11:53 +0000 | [diff] [blame] | 744 | QP_REFERENCED = 5, |
Steve Wise | 9eccfe1 | 2014-03-26 17:08:09 -0500 | [diff] [blame] | 745 | RELEASE_MAPINFO = 6, |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 746 | }; |
| 747 | |
Vipul Pandya | 793dad9 | 2012-12-10 09:30:56 +0000 | [diff] [blame] | 748 | enum c4iw_ep_history { |
| 749 | ACT_OPEN_REQ = 0, |
| 750 | ACT_OFLD_CONN = 1, |
| 751 | ACT_OPEN_RPL = 2, |
| 752 | ACT_ESTAB = 3, |
| 753 | PASS_ACCEPT_REQ = 4, |
| 754 | PASS_ESTAB = 5, |
| 755 | ABORT_UPCALL = 6, |
| 756 | ESTAB_UPCALL = 7, |
| 757 | CLOSE_UPCALL = 8, |
| 758 | ULP_ACCEPT = 9, |
| 759 | ULP_REJECT = 10, |
| 760 | TIMEDOUT = 11, |
| 761 | PEER_ABORT = 12, |
| 762 | PEER_CLOSE = 13, |
| 763 | CONNREQ_UPCALL = 14, |
| 764 | ABORT_CONN = 15, |
| 765 | DISCONN_UPCALL = 16, |
| 766 | EP_DISC_CLOSE = 17, |
| 767 | EP_DISC_ABORT = 18, |
| 768 | CONN_RPL_UPCALL = 19, |
| 769 | ACT_RETRY_NOMEM = 20, |
| 770 | ACT_RETRY_INUSE = 21 |
| 771 | }; |
| 772 | |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 773 | struct c4iw_ep_common { |
| 774 | struct iw_cm_id *cm_id; |
| 775 | struct c4iw_qp *qp; |
| 776 | struct c4iw_dev *dev; |
| 777 | enum c4iw_ep_state state; |
| 778 | struct kref kref; |
Steve Wise | 2f5b48c | 2010-09-10 11:15:36 -0500 | [diff] [blame] | 779 | struct mutex mutex; |
Vipul Pandya | 830662f | 2013-07-04 16:10:47 +0530 | [diff] [blame] | 780 | struct sockaddr_storage local_addr; |
| 781 | struct sockaddr_storage remote_addr; |
Steve Wise | 9eccfe1 | 2014-03-26 17:08:09 -0500 | [diff] [blame] | 782 | struct sockaddr_storage mapped_local_addr; |
| 783 | struct sockaddr_storage mapped_remote_addr; |
Steve Wise | aadc4df | 2010-09-10 11:15:25 -0500 | [diff] [blame] | 784 | struct c4iw_wr_wait wr_wait; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 785 | unsigned long flags; |
Vipul Pandya | 793dad9 | 2012-12-10 09:30:56 +0000 | [diff] [blame] | 786 | unsigned long history; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 787 | }; |
| 788 | |
| 789 | struct c4iw_listen_ep { |
| 790 | struct c4iw_ep_common com; |
| 791 | unsigned int stid; |
| 792 | int backlog; |
| 793 | }; |
| 794 | |
| 795 | struct c4iw_ep { |
| 796 | struct c4iw_ep_common com; |
| 797 | struct c4iw_ep *parent_ep; |
| 798 | struct timer_list timer; |
Roland Dreier | be4c9ba | 2010-05-05 14:45:40 -0700 | [diff] [blame] | 799 | struct list_head entry; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 800 | unsigned int atid; |
| 801 | u32 hwtid; |
| 802 | u32 snd_seq; |
| 803 | u32 rcv_seq; |
| 804 | struct l2t_entry *l2t; |
| 805 | struct dst_entry *dst; |
| 806 | struct sk_buff *mpa_skb; |
| 807 | struct c4iw_mpa_attributes mpa_attr; |
| 808 | u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA]; |
| 809 | unsigned int mpa_pkt_len; |
| 810 | u32 ird; |
| 811 | u32 ord; |
| 812 | u32 smac_idx; |
| 813 | u32 tx_chan; |
| 814 | u32 mtu; |
| 815 | u16 mss; |
| 816 | u16 emss; |
| 817 | u16 plen; |
| 818 | u16 rss_qid; |
| 819 | u16 txq_idx; |
Steve Wise | d4f1a5c | 2010-07-23 19:12:32 +0000 | [diff] [blame] | 820 | u16 ctrlq_idx; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 821 | u8 tos; |
Kumar Sanghvi | d2fe99e | 2011-09-25 20:17:44 +0530 | [diff] [blame] | 822 | u8 retry_with_mpa_v1; |
| 823 | u8 tried_with_mpa_v1; |
Vipul Pandya | 793dad9 | 2012-12-10 09:30:56 +0000 | [diff] [blame] | 824 | unsigned int retry_count; |
Hariprasad Shenai | b408ff2 | 2014-06-06 21:40:44 +0530 | [diff] [blame] | 825 | int snd_win; |
| 826 | int rcv_win; |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 827 | }; |
| 828 | |
Steve Wise | 9eccfe1 | 2014-03-26 17:08:09 -0500 | [diff] [blame] | 829 | static inline void print_addr(struct c4iw_ep_common *epc, const char *func, |
| 830 | const char *msg) |
| 831 | { |
| 832 | |
| 833 | #define SINA(a) (&(((struct sockaddr_in *)(a))->sin_addr.s_addr)) |
| 834 | #define SINP(a) ntohs(((struct sockaddr_in *)(a))->sin_port) |
| 835 | #define SIN6A(a) (&(((struct sockaddr_in6 *)(a))->sin6_addr)) |
| 836 | #define SIN6P(a) ntohs(((struct sockaddr_in6 *)(a))->sin6_port) |
| 837 | |
| 838 | if (c4iw_debug) { |
| 839 | switch (epc->local_addr.ss_family) { |
| 840 | case AF_INET: |
| 841 | PDBG("%s %s %pI4:%u/%u <-> %pI4:%u/%u\n", |
| 842 | func, msg, SINA(&epc->local_addr), |
| 843 | SINP(&epc->local_addr), |
| 844 | SINP(&epc->mapped_local_addr), |
| 845 | SINA(&epc->remote_addr), |
| 846 | SINP(&epc->remote_addr), |
| 847 | SINP(&epc->mapped_remote_addr)); |
| 848 | break; |
| 849 | case AF_INET6: |
| 850 | PDBG("%s %s %pI6:%u/%u <-> %pI6:%u/%u\n", |
| 851 | func, msg, SIN6A(&epc->local_addr), |
| 852 | SIN6P(&epc->local_addr), |
| 853 | SIN6P(&epc->mapped_local_addr), |
| 854 | SIN6A(&epc->remote_addr), |
| 855 | SIN6P(&epc->remote_addr), |
| 856 | SIN6P(&epc->mapped_remote_addr)); |
| 857 | break; |
| 858 | default: |
| 859 | break; |
| 860 | } |
| 861 | } |
| 862 | #undef SINA |
| 863 | #undef SINP |
| 864 | #undef SIN6A |
| 865 | #undef SIN6P |
| 866 | } |
| 867 | |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 868 | static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id) |
| 869 | { |
| 870 | return cm_id->provider_data; |
| 871 | } |
| 872 | |
| 873 | static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id) |
| 874 | { |
| 875 | return cm_id->provider_data; |
| 876 | } |
| 877 | |
| 878 | static inline int compute_wscale(int win) |
| 879 | { |
| 880 | int wscale = 0; |
| 881 | |
| 882 | while (wscale < 14 && (65535<<wscale) < win) |
| 883 | wscale++; |
| 884 | return wscale; |
| 885 | } |
| 886 | |
Vipul Pandya | f079af7 | 2013-03-14 05:08:58 +0000 | [diff] [blame] | 887 | static inline int ocqp_supported(const struct cxgb4_lld_info *infop) |
| 888 | { |
| 889 | #if defined(__i386__) || defined(__x86_64__) || defined(CONFIG_PPC64) |
| 890 | return infop->vr->ocq.size > 0; |
| 891 | #else |
| 892 | return 0; |
| 893 | #endif |
| 894 | } |
| 895 | |
Vipul Pandya | ec3eead | 2012-05-18 15:29:32 +0530 | [diff] [blame] | 896 | u32 c4iw_id_alloc(struct c4iw_id_table *alloc); |
| 897 | void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj); |
| 898 | int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num, |
| 899 | u32 reserved, u32 flags); |
| 900 | void c4iw_id_table_free(struct c4iw_id_table *alloc); |
| 901 | |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 902 | typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct sk_buff *skb); |
| 903 | |
| 904 | int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new, |
| 905 | struct l2t_entry *l2t); |
| 906 | void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qpid, |
| 907 | struct c4iw_dev_ucontext *uctx); |
Vipul Pandya | ec3eead | 2012-05-18 15:29:32 +0530 | [diff] [blame] | 908 | u32 c4iw_get_resource(struct c4iw_id_table *id_table); |
| 909 | void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry); |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 910 | int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid); |
| 911 | int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev); |
| 912 | int c4iw_pblpool_create(struct c4iw_rdev *rdev); |
| 913 | int c4iw_rqtpool_create(struct c4iw_rdev *rdev); |
Steve Wise | c6d7b26 | 2010-09-13 11:23:57 -0500 | [diff] [blame] | 914 | int c4iw_ocqp_pool_create(struct c4iw_rdev *rdev); |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 915 | void c4iw_pblpool_destroy(struct c4iw_rdev *rdev); |
| 916 | void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev); |
Steve Wise | c6d7b26 | 2010-09-13 11:23:57 -0500 | [diff] [blame] | 917 | void c4iw_ocqp_pool_destroy(struct c4iw_rdev *rdev); |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 918 | void c4iw_destroy_resource(struct c4iw_resource *rscp); |
| 919 | int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev); |
| 920 | int c4iw_register_device(struct c4iw_dev *dev); |
| 921 | void c4iw_unregister_device(struct c4iw_dev *dev); |
| 922 | int __init c4iw_cm_init(void); |
| 923 | void __exit c4iw_cm_term(void); |
| 924 | void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev, |
| 925 | struct c4iw_dev_ucontext *uctx); |
| 926 | void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev, |
| 927 | struct c4iw_dev_ucontext *uctx); |
| 928 | int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc); |
| 929 | int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr, |
| 930 | struct ib_send_wr **bad_wr); |
| 931 | int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr, |
| 932 | struct ib_recv_wr **bad_wr); |
| 933 | int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, |
| 934 | struct ib_mw_bind *mw_bind); |
| 935 | int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); |
| 936 | int c4iw_create_listen(struct iw_cm_id *cm_id, int backlog); |
| 937 | int c4iw_destroy_listen(struct iw_cm_id *cm_id); |
| 938 | int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); |
| 939 | int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len); |
| 940 | void c4iw_qp_add_ref(struct ib_qp *qp); |
| 941 | void c4iw_qp_rem_ref(struct ib_qp *qp); |
| 942 | void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list); |
| 943 | struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl( |
| 944 | struct ib_device *device, |
| 945 | int page_list_len); |
| 946 | struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth); |
| 947 | int c4iw_dealloc_mw(struct ib_mw *mw); |
Shani Michaeli | 7083e42 | 2013-02-06 16:19:12 +0000 | [diff] [blame] | 948 | struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd, enum ib_mw_type type); |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 949 | struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, |
| 950 | u64 length, u64 virt, int acc, |
| 951 | struct ib_udata *udata); |
| 952 | struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc); |
| 953 | struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd, |
| 954 | struct ib_phys_buf *buffer_list, |
| 955 | int num_phys_buf, |
| 956 | int acc, |
| 957 | u64 *iova_start); |
| 958 | int c4iw_reregister_phys_mem(struct ib_mr *mr, |
| 959 | int mr_rereg_mask, |
| 960 | struct ib_pd *pd, |
| 961 | struct ib_phys_buf *buffer_list, |
| 962 | int num_phys_buf, |
| 963 | int acc, u64 *iova_start); |
| 964 | int c4iw_dereg_mr(struct ib_mr *ib_mr); |
| 965 | int c4iw_destroy_cq(struct ib_cq *ib_cq); |
| 966 | struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries, |
| 967 | int vector, |
| 968 | struct ib_ucontext *ib_context, |
| 969 | struct ib_udata *udata); |
| 970 | int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata); |
| 971 | int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags); |
| 972 | int c4iw_destroy_qp(struct ib_qp *ib_qp); |
| 973 | struct ib_qp *c4iw_create_qp(struct ib_pd *pd, |
| 974 | struct ib_qp_init_attr *attrs, |
| 975 | struct ib_udata *udata); |
| 976 | int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, |
| 977 | int attr_mask, struct ib_udata *udata); |
Vipul Pandya | 67bbc05 | 2012-05-18 15:29:33 +0530 | [diff] [blame] | 978 | int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, |
| 979 | int attr_mask, struct ib_qp_init_attr *init_attr); |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 980 | struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn); |
| 981 | u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size); |
| 982 | void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size); |
| 983 | u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size); |
| 984 | void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size); |
Steve Wise | c6d7b26 | 2010-09-13 11:23:57 -0500 | [diff] [blame] | 985 | u32 c4iw_ocqp_pool_alloc(struct c4iw_rdev *rdev, int size); |
| 986 | void c4iw_ocqp_pool_free(struct c4iw_rdev *rdev, u32 addr, int size); |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 987 | int c4iw_ofld_send(struct c4iw_rdev *rdev, struct sk_buff *skb); |
Steve Wise | 1cf24dc | 2013-08-06 21:04:35 +0530 | [diff] [blame] | 988 | void c4iw_flush_hw_cq(struct c4iw_cq *chp); |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 989 | void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count); |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 990 | int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp); |
| 991 | int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count); |
Steve Wise | 1cf24dc | 2013-08-06 21:04:35 +0530 | [diff] [blame] | 992 | int c4iw_flush_sq(struct c4iw_qp *qhp); |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 993 | int c4iw_ev_handler(struct c4iw_dev *rnicp, u32 qid); |
| 994 | u16 c4iw_rqes_posted(struct c4iw_qp *qhp); |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 995 | int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe); |
| 996 | u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); |
| 997 | void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid, |
| 998 | struct c4iw_dev_ucontext *uctx); |
| 999 | u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx); |
| 1000 | void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid, |
| 1001 | struct c4iw_dev_ucontext *uctx); |
| 1002 | void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe); |
| 1003 | |
| 1004 | extern struct cxgb4_client t4c_client; |
| 1005 | extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS]; |
Roland Dreier | be4c9ba | 2010-05-05 14:45:40 -0700 | [diff] [blame] | 1006 | extern int c4iw_max_read_depth; |
Vipul Pandya | 422eea0 | 2012-05-18 15:29:30 +0530 | [diff] [blame] | 1007 | extern int db_fc_threshold; |
Vipul Pandya | 80ccdd6 | 2013-03-14 05:09:00 +0000 | [diff] [blame] | 1008 | extern int db_coalescing_threshold; |
Vipul Pandya | 42b6a94 | 2013-03-14 05:09:01 +0000 | [diff] [blame] | 1009 | extern int use_dsgl; |
Vipul Pandya | 422eea0 | 2012-05-18 15:29:30 +0530 | [diff] [blame] | 1010 | |
Steve Wise | cfdda9d | 2010-04-21 15:30:06 -0700 | [diff] [blame] | 1011 | |
| 1012 | #endif |