Kelvin Cheung | ca585cf | 2012-07-25 16:17:24 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2011 Zhang, Keguang <keguang.zhang@gmail.com> |
| 3 | * |
| 4 | * Loongson 1 Clock Register Definitions. |
| 5 | * |
Ralf Baechle | 7034228 | 2013-01-22 12:59:30 +0100 | [diff] [blame] | 6 | * This program is free software; you can redistribute it and/or modify it |
| 7 | * under the terms of the GNU General Public License as published by the |
Kelvin Cheung | ca585cf | 2012-07-25 16:17:24 +0200 | [diff] [blame] | 8 | * Free Software Foundation; either version 2 of the License, or (at your |
| 9 | * option) any later version. |
| 10 | */ |
| 11 | |
Huacai Chen | 30ad29b | 2015-04-21 10:00:35 +0800 | [diff] [blame] | 12 | #ifndef __ASM_MACH_LOONGSON32_REGS_CLK_H |
| 13 | #define __ASM_MACH_LOONGSON32_REGS_CLK_H |
Kelvin Cheung | ca585cf | 2012-07-25 16:17:24 +0200 | [diff] [blame] | 14 | |
| 15 | #define LS1X_CLK_REG(x) \ |
| 16 | ((void __iomem *)KSEG1ADDR(LS1X_CLK_BASE + (x))) |
| 17 | |
| 18 | #define LS1X_CLK_PLL_FREQ LS1X_CLK_REG(0x0) |
| 19 | #define LS1X_CLK_PLL_DIV LS1X_CLK_REG(0x4) |
| 20 | |
| 21 | /* Clock PLL Divisor Register Bits */ |
Kelvin Cheung | 9ec88b6 | 2016-04-06 20:34:54 +0800 | [diff] [blame] | 22 | #define DIV_DC_EN BIT(31) |
| 23 | #define DIV_DC_RST BIT(30) |
| 24 | #define DIV_CPU_EN BIT(25) |
| 25 | #define DIV_CPU_RST BIT(24) |
| 26 | #define DIV_DDR_EN BIT(19) |
| 27 | #define DIV_DDR_RST BIT(18) |
| 28 | #define RST_DC_EN BIT(5) |
| 29 | #define RST_DC BIT(4) |
| 30 | #define RST_DDR_EN BIT(3) |
| 31 | #define RST_DDR BIT(2) |
| 32 | #define RST_CPU_EN BIT(1) |
| 33 | #define RST_CPU BIT(0) |
Kelvin Cheung | ca585cf | 2012-07-25 16:17:24 +0200 | [diff] [blame] | 34 | |
| 35 | #define DIV_DC_SHIFT 26 |
| 36 | #define DIV_CPU_SHIFT 20 |
| 37 | #define DIV_DDR_SHIFT 14 |
| 38 | |
Kelvin Cheung | f29ad10 | 2014-10-10 11:40:01 +0800 | [diff] [blame] | 39 | #define DIV_DC_WIDTH 4 |
| 40 | #define DIV_CPU_WIDTH 4 |
| 41 | #define DIV_DDR_WIDTH 4 |
| 42 | |
| 43 | #define BYPASS_DC_SHIFT 12 |
| 44 | #define BYPASS_DDR_SHIFT 10 |
| 45 | #define BYPASS_CPU_SHIFT 8 |
| 46 | |
| 47 | #define BYPASS_DC_WIDTH 1 |
| 48 | #define BYPASS_DDR_WIDTH 1 |
| 49 | #define BYPASS_CPU_WIDTH 1 |
Kelvin Cheung | 17ded0a | 2012-10-23 05:17:00 +0000 | [diff] [blame] | 50 | |
Huacai Chen | 30ad29b | 2015-04-21 10:00:35 +0800 | [diff] [blame] | 51 | #endif /* __ASM_MACH_LOONGSON32_REGS_CLK_H */ |