Abhijeet Dharmapurikar | 9a3a6c3 | 2017-01-06 18:27:29 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved. |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 14 | |
| 15 | #include <linux/i2c.h> |
| 16 | #include <linux/debugfs.h> |
| 17 | #include <linux/errno.h> |
| 18 | #include <linux/module.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/slab.h> |
| 21 | #include <linux/power_supply.h> |
| 22 | #include <linux/regulator/driver.h> |
| 23 | #include <linux/regulator/of_regulator.h> |
| 24 | #include <linux/regulator/machine.h> |
| 25 | #include <linux/of.h> |
| 26 | #include <linux/mutex.h> |
| 27 | #include <linux/delay.h> |
| 28 | #include <linux/qpnp/qpnp-adc.h> |
| 29 | #include <linux/pinctrl/consumer.h> |
| 30 | |
| 31 | /* Mask/Bit helpers */ |
| 32 | #define _SMB1351_MASK(BITS, POS) \ |
| 33 | ((unsigned char)(((1 << (BITS)) - 1) << (POS))) |
| 34 | #define SMB1351_MASK(LEFT_BIT_POS, RIGHT_BIT_POS) \ |
| 35 | _SMB1351_MASK((LEFT_BIT_POS) - (RIGHT_BIT_POS) + 1, \ |
| 36 | (RIGHT_BIT_POS)) |
| 37 | |
| 38 | /* Configuration registers */ |
| 39 | #define CHG_CURRENT_CTRL_REG 0x0 |
| 40 | #define FAST_CHG_CURRENT_MASK SMB1351_MASK(7, 4) |
| 41 | #define AC_INPUT_CURRENT_LIMIT_MASK SMB1351_MASK(3, 0) |
| 42 | |
| 43 | #define CHG_OTH_CURRENT_CTRL_REG 0x1 |
| 44 | #define PRECHG_CURRENT_MASK SMB1351_MASK(7, 5) |
| 45 | #define ITERM_MASK SMB1351_MASK(4, 2) |
| 46 | #define USB_2_3_MODE_SEL_BIT BIT(1) |
| 47 | #define USB_2_3_MODE_SEL_BY_I2C 0 |
| 48 | #define USB_2_3_MODE_SEL_BY_PIN 0x2 |
| 49 | #define USB_5_1_CMD_POLARITY_BIT BIT(0) |
| 50 | #define USB_CMD_POLARITY_500_1_100_0 0 |
| 51 | #define USB_CMD_POLARITY_500_0_100_1 0x1 |
| 52 | |
| 53 | #define VARIOUS_FUNC_REG 0x2 |
| 54 | #define SUSPEND_MODE_CTRL_BIT BIT(7) |
| 55 | #define SUSPEND_MODE_CTRL_BY_PIN 0 |
| 56 | #define SUSPEND_MODE_CTRL_BY_I2C 0x80 |
| 57 | #define BATT_TO_SYS_POWER_CTRL_BIT BIT(6) |
| 58 | #define MAX_SYS_VOLTAGE BIT(5) |
| 59 | #define AICL_EN_BIT BIT(4) |
| 60 | #define AICL_DET_TH_BIT BIT(3) |
| 61 | #define APSD_EN_BIT BIT(2) |
| 62 | #define BATT_OV_BIT BIT(1) |
| 63 | #define VCHG_FUNC_BIT BIT(0) |
| 64 | |
| 65 | #define VFLOAT_REG 0x3 |
| 66 | #define PRECHG_TO_FAST_VOLTAGE_CFG_MASK SMB1351_MASK(7, 6) |
| 67 | #define VFLOAT_MASK SMB1351_MASK(5, 0) |
| 68 | |
| 69 | #define CHG_CTRL_REG 0x4 |
| 70 | #define AUTO_RECHG_BIT BIT(7) |
| 71 | #define AUTO_RECHG_ENABLE 0 |
| 72 | #define AUTO_RECHG_DISABLE 0x80 |
| 73 | #define ITERM_EN_BIT BIT(6) |
| 74 | #define ITERM_ENABLE 0 |
| 75 | #define ITERM_DISABLE 0x40 |
| 76 | #define MAPPED_AC_INPUT_CURRENT_LIMIT_MASK SMB1351_MASK(5, 4) |
| 77 | #define AUTO_RECHG_TH_BIT BIT(3) |
| 78 | #define AUTO_RECHG_TH_50MV 0 |
| 79 | #define AUTO_RECHG_TH_100MV 0x8 |
| 80 | #define AFCV_MASK SMB1351_MASK(2, 0) |
| 81 | |
| 82 | #define CHG_STAT_TIMERS_CTRL_REG 0x5 |
| 83 | #define STAT_OUTPUT_POLARITY_BIT BIT(7) |
| 84 | #define STAT_OUTPUT_MODE_BIT BIT(6) |
| 85 | #define STAT_OUTPUT_CTRL_BIT BIT(5) |
| 86 | #define OTH_CHG_IL_BIT BIT(4) |
| 87 | #define COMPLETE_CHG_TIMEOUT_MASK SMB1351_MASK(3, 2) |
| 88 | #define PRECHG_TIMEOUT_MASK SMB1351_MASK(1, 0) |
| 89 | |
| 90 | #define CHG_PIN_EN_CTRL_REG 0x6 |
| 91 | #define LED_BLINK_FUNC_BIT BIT(7) |
| 92 | #define EN_PIN_CTRL_MASK SMB1351_MASK(6, 5) |
| 93 | #define EN_BY_I2C_0_DISABLE 0 |
| 94 | #define EN_BY_I2C_0_ENABLE 0x20 |
| 95 | #define EN_BY_PIN_HIGH_ENABLE 0x40 |
| 96 | #define EN_BY_PIN_LOW_ENABLE 0x60 |
| 97 | #define USBCS_CTRL_BIT BIT(4) |
| 98 | #define USBCS_CTRL_BY_I2C 0 |
| 99 | #define USBCS_CTRL_BY_PIN 0x10 |
| 100 | #define USBCS_INPUT_STATE_BIT BIT(3) |
| 101 | #define CHG_ERR_BIT BIT(2) |
| 102 | #define APSD_DONE_BIT BIT(1) |
| 103 | #define USB_FAIL_BIT BIT(0) |
| 104 | |
| 105 | #define THERM_A_CTRL_REG 0x7 |
| 106 | #define MIN_SYS_VOLTAGE_MASK SMB1351_MASK(7, 6) |
| 107 | #define LOAD_BATT_10MA_FVC_BIT BIT(5) |
| 108 | #define THERM_MONITOR_BIT BIT(4) |
| 109 | #define THERM_MONITOR_EN 0 |
| 110 | #define SOFT_COLD_TEMP_LIMIT_MASK SMB1351_MASK(3, 2) |
| 111 | #define SOFT_HOT_TEMP_LIMIT_MASK SMB1351_MASK(1, 0) |
| 112 | |
| 113 | #define WDOG_SAFETY_TIMER_CTRL_REG 0x8 |
| 114 | #define AICL_FAIL_OPTION_BIT BIT(7) |
| 115 | #define AICL_FAIL_TO_SUSPEND 0 |
| 116 | #define AICL_FAIL_TO_150_MA 0x80 |
| 117 | #define WDOG_TIMEOUT_MASK SMB1351_MASK(6, 5) |
| 118 | #define WDOG_IRQ_SAFETY_TIMER_MASK SMB1351_MASK(4, 3) |
| 119 | #define WDOG_IRQ_SAFETY_TIMER_EN_BIT BIT(2) |
| 120 | #define WDOG_OPTION_BIT BIT(1) |
| 121 | #define WDOG_TIMER_EN_BIT BIT(0) |
| 122 | |
| 123 | #define OTG_USBIN_AICL_CTRL_REG 0x9 |
| 124 | #define OTG_ID_PIN_CTRL_MASK SMB1351_MASK(7, 6) |
| 125 | #define OTG_PIN_POLARITY_BIT BIT(5) |
| 126 | #define DCIN_IC_GLITCH_FILTER_HV_ADAPTER_MASK SMB1351_MASK(4, 3) |
| 127 | #define DCIN_IC_GLITCH_FILTER_LV_ADAPTER_BIT BIT(2) |
| 128 | #define USBIN_AICL_CFG1_BIT BIT(1) |
| 129 | #define USBIN_AICL_CFG0_BIT BIT(0) |
| 130 | |
| 131 | #define OTG_TLIM_CTRL_REG 0xA |
| 132 | #define SWITCH_FREQ_MASK SMB1351_MASK(7, 6) |
| 133 | #define THERM_LOOP_TEMP_SEL_MASK SMB1351_MASK(5, 4) |
| 134 | #define OTG_OC_LIMIT_MASK SMB1351_MASK(3, 2) |
| 135 | #define OTG_BATT_UVLO_TH_MASK SMB1351_MASK(1, 0) |
| 136 | |
| 137 | #define HARD_SOFT_LIMIT_CELL_TEMP_REG 0xB |
| 138 | #define HARD_LIMIT_COLD_TEMP_ALARM_TRIP_MASK SMB1351_MASK(7, 6) |
| 139 | #define HARD_LIMIT_HOT_TEMP_ALARM_TRIP_MASK SMB1351_MASK(5, 4) |
| 140 | #define SOFT_LIMIT_COLD_TEMP_ALARM_TRIP_MASK SMB1351_MASK(3, 2) |
| 141 | #define SOFT_LIMIT_HOT_TEMP_ALARM_TRIP_MASK SMB1351_MASK(1, 0) |
| 142 | |
| 143 | #define FAULT_INT_REG 0xC |
| 144 | #define HOT_COLD_HARD_LIMIT_BIT BIT(7) |
| 145 | #define HOT_COLD_SOFT_LIMIT_BIT BIT(6) |
| 146 | #define BATT_UVLO_IN_OTG_BIT BIT(5) |
| 147 | #define OTG_OC_BIT BIT(4) |
| 148 | #define INPUT_OVLO_BIT BIT(3) |
| 149 | #define INPUT_UVLO_BIT BIT(2) |
| 150 | #define AICL_DONE_FAIL_BIT BIT(1) |
| 151 | #define INTERNAL_OVER_TEMP_BIT BIT(0) |
| 152 | |
| 153 | #define STATUS_INT_REG 0xD |
| 154 | #define CHG_OR_PRECHG_TIMEOUT_BIT BIT(7) |
| 155 | #define RID_CHANGE_BIT BIT(6) |
| 156 | #define BATT_OVP_BIT BIT(5) |
| 157 | #define FAST_TERM_TAPER_RECHG_INHIBIT_BIT BIT(4) |
| 158 | #define WDOG_TIMER_BIT BIT(3) |
| 159 | #define POK_BIT BIT(2) |
| 160 | #define BATT_MISSING_BIT BIT(1) |
| 161 | #define BATT_LOW_BIT BIT(0) |
| 162 | |
| 163 | #define VARIOUS_FUNC_2_REG 0xE |
| 164 | #define CHG_HOLD_OFF_TIMER_AFTER_PLUGIN_BIT BIT(7) |
| 165 | #define CHG_INHIBIT_BIT BIT(6) |
| 166 | #define FAST_CHG_CC_IN_BATT_SOFT_LIMIT_MODE_BIT BIT(5) |
| 167 | #define FVCL_IN_BATT_SOFT_LIMIT_MODE_MASK SMB1351_MASK(4, 3) |
| 168 | #define HARD_TEMP_LIMIT_BEHAVIOR_BIT BIT(2) |
| 169 | #define PRECHG_TO_FASTCHG_BIT BIT(1) |
| 170 | #define STAT_PIN_CONFIG_BIT BIT(0) |
| 171 | |
| 172 | #define FLEXCHARGER_REG 0x10 |
| 173 | #define AFVC_IRQ_BIT BIT(7) |
| 174 | #define CHG_CONFIG_MASK SMB1351_MASK(6, 4) |
| 175 | #define LOW_BATT_VOLTAGE_DET_TH_MASK SMB1351_MASK(3, 0) |
| 176 | |
| 177 | #define VARIOUS_FUNC_3_REG 0x11 |
| 178 | #define SAFETY_TIMER_EN_MASK SMB1351_MASK(7, 6) |
| 179 | #define BLOCK_SUSPEND_DURING_VBATT_LOW_BIT BIT(5) |
| 180 | #define TIMEOUT_SEL_FOR_APSD_BIT BIT(4) |
| 181 | #define SDP_SUSPEND_BIT BIT(3) |
| 182 | #define QC_2P1_AUTO_INCREMENT_MODE_BIT BIT(2) |
| 183 | #define QC_2P1_AUTH_ALGO_BIT BIT(1) |
| 184 | #define DCD_EN_BIT BIT(0) |
| 185 | |
| 186 | #define HVDCP_BATT_MISSING_CTRL_REG 0x12 |
| 187 | #define HVDCP_ADAPTER_SEL_MASK SMB1351_MASK(7, 6) |
| 188 | #define HVDCP_EN_BIT BIT(5) |
| 189 | #define HVDCP_AUTO_INCREMENT_LIMIT_BIT BIT(4) |
| 190 | #define BATT_MISSING_ON_INPUT_PLUGIN_BIT BIT(3) |
| 191 | #define BATT_MISSING_2P6S_POLLER_BIT BIT(2) |
| 192 | #define BATT_MISSING_ALGO_BIT BIT(1) |
| 193 | #define BATT_MISSING_THERM_PIN_SOURCE_BIT BIT(0) |
| 194 | |
| 195 | #define PON_OPTIONS_REG 0x13 |
| 196 | #define SYSOK_INOK_POLARITY_BIT BIT(7) |
| 197 | #define SYSOK_OPTIONS_MASK SMB1351_MASK(6, 4) |
| 198 | #define INPUT_MISSING_POLLER_CONFIG_BIT BIT(3) |
| 199 | #define VBATT_LOW_DISABLED_OR_RESET_STATE_BIT BIT(2) |
| 200 | #define QC_2P1_AUTH_ALGO_IRQ_EN_BIT BIT(0) |
| 201 | |
| 202 | #define OTG_MODE_POWER_OPTIONS_REG 0x14 |
| 203 | #define ADAPTER_CONFIG_MASK SMB1351_MASK(7, 6) |
| 204 | #define MAP_HVDCP_BIT BIT(5) |
| 205 | #define SDP_LOW_BATT_FORCE_USB5_OVER_USB1_BIT BIT(4) |
| 206 | #define OTG_HICCUP_MODE_BIT BIT(2) |
| 207 | #define INPUT_CURRENT_LIMIT_MASK SMB1351_MASK(1, 0) |
| 208 | |
| 209 | #define CHARGER_I2C_CTRL_REG 0x15 |
| 210 | #define FULLON_MODE_EN_BIT BIT(7) |
| 211 | #define I2C_HS_MODE_EN_BIT BIT(6) |
| 212 | #define SYSON_LDO_OUTPUT_SEL_BIT BIT(5) |
| 213 | #define VBATT_TRACKING_VOLTAGE_DIFF_BIT BIT(4) |
| 214 | #define DISABLE_AFVC_WHEN_ENTER_TAPER_BIT BIT(3) |
| 215 | #define VCHG_IINV_BIT BIT(2) |
| 216 | #define AFVC_OVERRIDE_BIT BIT(1) |
| 217 | #define SYSOK_PIN_CONFIG_BIT BIT(0) |
| 218 | |
| 219 | #define VERSION_REG 0x2E |
| 220 | #define VERSION_MASK BIT(1) |
| 221 | |
| 222 | /* Command registers */ |
| 223 | #define CMD_I2C_REG 0x30 |
| 224 | #define CMD_RELOAD_BIT BIT(7) |
| 225 | #define CMD_BQ_CFG_ACCESS_BIT BIT(6) |
| 226 | |
| 227 | #define CMD_INPUT_LIMIT_REG 0x31 |
| 228 | #define CMD_OVERRIDE_BIT BIT(7) |
| 229 | #define CMD_SUSPEND_MODE_BIT BIT(6) |
| 230 | #define CMD_INPUT_CURRENT_MODE_BIT BIT(3) |
| 231 | #define CMD_INPUT_CURRENT_MODE_APSD 0 |
| 232 | #define CMD_INPUT_CURRENT_MODE_CMD 0x08 |
| 233 | #define CMD_USB_2_3_SEL_BIT BIT(2) |
| 234 | #define CMD_USB_2_MODE 0 |
| 235 | #define CMD_USB_3_MODE 0x4 |
| 236 | #define CMD_USB_1_5_AC_CTRL_MASK SMB1351_MASK(1, 0) |
| 237 | #define CMD_USB_100_MODE 0 |
| 238 | #define CMD_USB_500_MODE 0x2 |
| 239 | #define CMD_USB_AC_MODE 0x1 |
| 240 | |
| 241 | #define CMD_CHG_REG 0x32 |
| 242 | #define CMD_DISABLE_THERM_MONITOR_BIT BIT(4) |
| 243 | #define CMD_TURN_OFF_STAT_PIN_BIT BIT(3) |
| 244 | #define CMD_PRE_TO_FAST_EN_BIT BIT(2) |
| 245 | #define CMD_CHG_EN_BIT BIT(1) |
| 246 | #define CMD_CHG_DISABLE 0 |
| 247 | #define CMD_CHG_ENABLE 0x2 |
| 248 | #define CMD_OTG_EN_BIT BIT(0) |
| 249 | |
| 250 | #define CMD_DEAD_BATT_REG 0x33 |
| 251 | #define CMD_STOP_DEAD_BATT_TIMER_MASK SMB1351_MASK(7, 0) |
| 252 | |
| 253 | #define CMD_HVDCP_REG 0x34 |
| 254 | #define CMD_APSD_RE_RUN_BIT BIT(7) |
| 255 | #define CMD_FORCE_HVDCP_2P0_BIT BIT(5) |
| 256 | #define CMD_HVDCP_MODE_MASK SMB1351_MASK(5, 0) |
| 257 | |
| 258 | /* Status registers */ |
| 259 | #define STATUS_0_REG 0x36 |
| 260 | #define STATUS_AICL_BIT BIT(7) |
| 261 | #define STATUS_INPUT_CURRENT_LIMIT_MASK SMB1351_MASK(6, 5) |
| 262 | #define STATUS_DCIN_INPUT_CURRENT_LIMIT_MASK SMB1351_MASK(4, 0) |
| 263 | |
| 264 | #define STATUS_1_REG 0x37 |
| 265 | #define STATUS_INPUT_RANGE_MASK SMB1351_MASK(7, 4) |
| 266 | #define STATUS_INPUT_USB_BIT BIT(0) |
| 267 | |
| 268 | #define STATUS_2_REG 0x38 |
| 269 | #define STATUS_FAST_CHG_BIT BIT(7) |
| 270 | #define STATUS_HARD_LIMIT_BIT BIT(6) |
| 271 | #define STATUS_FLOAT_VOLTAGE_MASK SMB1351_MASK(5, 0) |
| 272 | |
| 273 | #define STATUS_3_REG 0x39 |
| 274 | #define STATUS_CHG_BIT BIT(7) |
| 275 | #define STATUS_PRECHG_CURRENT_MASK SMB1351_MASK(6, 4) |
| 276 | #define STATUS_FAST_CHG_CURRENT_MASK SMB1351_MASK(3, 0) |
| 277 | |
| 278 | #define STATUS_4_REG 0x3A |
| 279 | #define STATUS_OTG_BIT BIT(7) |
| 280 | #define STATUS_AFVC_BIT BIT(6) |
| 281 | #define STATUS_DONE_BIT BIT(5) |
| 282 | #define STATUS_BATT_LESS_THAN_2V_BIT BIT(4) |
| 283 | #define STATUS_HOLD_OFF_BIT BIT(3) |
| 284 | #define STATUS_CHG_MASK SMB1351_MASK(2, 1) |
| 285 | #define STATUS_NO_CHARGING 0 |
| 286 | #define STATUS_FAST_CHARGING 0x4 |
| 287 | #define STATUS_PRE_CHARGING 0x2 |
| 288 | #define STATUS_TAPER_CHARGING 0x6 |
| 289 | #define STATUS_CHG_EN_STATUS_BIT BIT(0) |
| 290 | |
| 291 | #define STATUS_5_REG 0x3B |
| 292 | #define STATUS_SOURCE_DETECTED_MASK SMB1351_MASK(7, 0) |
| 293 | #define STATUS_PORT_CDP 0x80 |
| 294 | #define STATUS_PORT_DCP 0x40 |
| 295 | #define STATUS_PORT_OTHER 0x20 |
| 296 | #define STATUS_PORT_SDP 0x10 |
| 297 | #define STATUS_PORT_ACA_A 0x8 |
| 298 | #define STATUS_PORT_ACA_B 0x4 |
| 299 | #define STATUS_PORT_ACA_C 0x2 |
| 300 | #define STATUS_PORT_ACA_DOCK 0x1 |
| 301 | |
| 302 | #define STATUS_6_REG 0x3C |
| 303 | #define STATUS_DCD_TIMEOUT_BIT BIT(7) |
| 304 | #define STATUS_DCD_GOOD_DG_BIT BIT(6) |
| 305 | #define STATUS_OCD_GOOD_DG_BIT BIT(5) |
| 306 | #define STATUS_RID_ABD_DG_BIT BIT(4) |
| 307 | #define STATUS_RID_FLOAT_STATE_MACHINE_BIT BIT(3) |
| 308 | #define STATUS_RID_A_STATE_MACHINE_BIT BIT(2) |
| 309 | #define STATUS_RID_B_STATE_MACHINE_BIT BIT(1) |
| 310 | #define STATUS_RID_C_STATE_MACHINE_BIT BIT(0) |
| 311 | |
| 312 | #define STATUS_7_REG 0x3D |
| 313 | #define STATUS_HVDCP_MASK SMB1351_MASK(7, 0) |
| 314 | |
| 315 | #define STATUS_8_REG 0x3E |
| 316 | #define STATUS_USNIN_HV_INPUT_SEL_BIT BIT(5) |
| 317 | #define STATUS_USBIN_LV_UNDER_INPUT_SEL_BIT BIT(4) |
| 318 | #define STATUS_USBIN_LV_INPUT_SEL_BIT BIT(3) |
| 319 | |
| 320 | /* Revision register */ |
| 321 | #define CHG_REVISION_REG 0x3F |
| 322 | #define GUI_REVISION_MASK SMB1351_MASK(7, 4) |
| 323 | #define DEVICE_REVISION_MASK SMB1351_MASK(3, 0) |
| 324 | |
| 325 | /* IRQ status registers */ |
| 326 | #define IRQ_A_REG 0x40 |
| 327 | #define IRQ_HOT_HARD_BIT BIT(6) |
| 328 | #define IRQ_COLD_HARD_BIT BIT(4) |
| 329 | #define IRQ_HOT_SOFT_BIT BIT(2) |
| 330 | #define IRQ_COLD_SOFT_BIT BIT(0) |
| 331 | |
| 332 | #define IRQ_B_REG 0x41 |
| 333 | #define IRQ_BATT_TERMINAL_REMOVED_BIT BIT(6) |
| 334 | #define IRQ_BATT_MISSING_BIT BIT(4) |
| 335 | #define IRQ_LOW_BATT_VOLTAGE_BIT BIT(2) |
| 336 | #define IRQ_INTERNAL_TEMP_LIMIT_BIT BIT(0) |
| 337 | |
| 338 | #define IRQ_C_REG 0x42 |
| 339 | #define IRQ_PRE_TO_FAST_VOLTAGE_BIT BIT(6) |
| 340 | #define IRQ_RECHG_BIT BIT(4) |
| 341 | #define IRQ_TAPER_BIT BIT(2) |
| 342 | #define IRQ_TERM_BIT BIT(0) |
| 343 | |
| 344 | #define IRQ_D_REG 0x43 |
| 345 | #define IRQ_BATT_OV_BIT BIT(6) |
| 346 | #define IRQ_CHG_ERROR_BIT BIT(4) |
| 347 | #define IRQ_CHG_TIMEOUT_BIT BIT(2) |
| 348 | #define IRQ_PRECHG_TIMEOUT_BIT BIT(0) |
| 349 | |
| 350 | #define IRQ_E_REG 0x44 |
| 351 | #define IRQ_USBIN_OV_BIT BIT(6) |
| 352 | #define IRQ_USBIN_UV_BIT BIT(4) |
| 353 | #define IRQ_AFVC_BIT BIT(2) |
| 354 | #define IRQ_POWER_OK_BIT BIT(0) |
| 355 | |
| 356 | #define IRQ_F_REG 0x45 |
| 357 | #define IRQ_OTG_OVER_CURRENT_BIT BIT(6) |
| 358 | #define IRQ_OTG_FAIL_BIT BIT(4) |
| 359 | #define IRQ_RID_BIT BIT(2) |
| 360 | #define IRQ_OTG_OC_RETRY_BIT BIT(0) |
| 361 | |
| 362 | #define IRQ_G_REG 0x46 |
| 363 | #define IRQ_SOURCE_DET_BIT BIT(6) |
| 364 | #define IRQ_AICL_DONE_BIT BIT(4) |
| 365 | #define IRQ_AICL_FAIL_BIT BIT(2) |
| 366 | #define IRQ_CHG_INHIBIT_BIT BIT(0) |
| 367 | |
| 368 | #define IRQ_H_REG 0x47 |
| 369 | #define IRQ_IC_LIMIT_STATUS_BIT BIT(5) |
| 370 | #define IRQ_HVDCP_2P1_STATUS_BIT BIT(4) |
| 371 | #define IRQ_HVDCP_AUTH_DONE_BIT BIT(2) |
| 372 | #define IRQ_WDOG_TIMEOUT_BIT BIT(0) |
| 373 | |
| 374 | /* constants */ |
| 375 | #define USB2_MIN_CURRENT_MA 100 |
| 376 | #define USB2_MAX_CURRENT_MA 500 |
| 377 | #define USB3_MIN_CURRENT_MA 150 |
| 378 | #define USB3_MAX_CURRENT_MA 900 |
| 379 | #define SMB1351_IRQ_REG_COUNT 8 |
| 380 | #define SMB1351_CHG_PRE_MIN_MA 100 |
| 381 | #define SMB1351_CHG_FAST_MIN_MA 1000 |
| 382 | #define SMB1351_CHG_FAST_MAX_MA 4500 |
| 383 | #define SMB1351_CHG_PRE_SHIFT 5 |
| 384 | #define SMB1351_CHG_FAST_SHIFT 4 |
| 385 | #define DEFAULT_BATT_CAPACITY 50 |
| 386 | #define DEFAULT_BATT_TEMP 250 |
| 387 | #define SUSPEND_CURRENT_MA 2 |
| 388 | |
| 389 | #define CHG_ITERM_200MA 0x0 |
| 390 | #define CHG_ITERM_300MA 0x04 |
| 391 | #define CHG_ITERM_400MA 0x08 |
| 392 | #define CHG_ITERM_500MA 0x0C |
| 393 | #define CHG_ITERM_600MA 0x10 |
| 394 | #define CHG_ITERM_700MA 0x14 |
| 395 | |
| 396 | #define ADC_TM_WARM_COOL_THR_ENABLE ADC_TM_HIGH_LOW_THR_ENABLE |
| 397 | |
| 398 | enum reason { |
| 399 | USER = BIT(0), |
| 400 | THERMAL = BIT(1), |
| 401 | CURRENT = BIT(2), |
| 402 | SOC = BIT(3), |
| 403 | }; |
| 404 | |
| 405 | static char *pm_batt_supplied_to[] = { |
| 406 | "bms", |
| 407 | }; |
| 408 | |
| 409 | struct smb1351_regulator { |
| 410 | struct regulator_desc rdesc; |
| 411 | struct regulator_dev *rdev; |
| 412 | }; |
| 413 | |
| 414 | enum chip_version { |
| 415 | SMB_UNKNOWN = 0, |
| 416 | SMB1350, |
| 417 | SMB1351, |
| 418 | SMB_MAX_TYPE, |
| 419 | }; |
| 420 | |
| 421 | static const char *smb1351_version_str[SMB_MAX_TYPE] = { |
| 422 | [SMB_UNKNOWN] = "Unknown", |
| 423 | [SMB1350] = "SMB1350", |
| 424 | [SMB1351] = "SMB1351", |
| 425 | }; |
| 426 | |
| 427 | struct smb1351_charger { |
| 428 | struct i2c_client *client; |
| 429 | struct device *dev; |
| 430 | |
| 431 | bool recharge_disabled; |
| 432 | int recharge_mv; |
| 433 | bool iterm_disabled; |
| 434 | int iterm_ma; |
| 435 | int vfloat_mv; |
| 436 | int chg_present; |
| 437 | int fake_battery_soc; |
| 438 | bool chg_autonomous_mode; |
| 439 | bool disable_apsd; |
| 440 | bool using_pmic_therm; |
| 441 | bool jeita_supported; |
| 442 | bool battery_missing; |
| 443 | const char *bms_psy_name; |
| 444 | bool resume_completed; |
| 445 | bool irq_waiting; |
| 446 | struct delayed_work chg_remove_work; |
| 447 | struct delayed_work hvdcp_det_work; |
| 448 | |
| 449 | /* status tracking */ |
| 450 | bool batt_full; |
| 451 | bool batt_hot; |
| 452 | bool batt_cold; |
| 453 | bool batt_warm; |
| 454 | bool batt_cool; |
| 455 | |
| 456 | int battchg_disabled_status; |
| 457 | int usb_suspended_status; |
| 458 | int target_fastchg_current_max_ma; |
| 459 | int fastchg_current_max_ma; |
| 460 | int workaround_flags; |
| 461 | |
| 462 | int parallel_pin_polarity_setting; |
| 463 | bool parallel_charger; |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 464 | bool parallel_charger_suspended; |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 465 | bool bms_controlled_charging; |
| 466 | bool apsd_rerun; |
| 467 | bool usbin_ov; |
| 468 | bool chg_remove_work_scheduled; |
| 469 | bool force_hvdcp_2p0; |
| 470 | enum chip_version version; |
| 471 | |
| 472 | /* psy */ |
| 473 | struct power_supply *usb_psy; |
| 474 | int usb_psy_ma; |
| 475 | struct power_supply *bms_psy; |
| 476 | struct power_supply_desc batt_psy_d; |
| 477 | struct power_supply *batt_psy; |
| 478 | struct power_supply *parallel_psy; |
| 479 | struct power_supply_desc parallel_psy_d; |
| 480 | |
| 481 | struct smb1351_regulator otg_vreg; |
| 482 | struct mutex irq_complete; |
| 483 | |
| 484 | struct dentry *debug_root; |
| 485 | u32 peek_poke_address; |
| 486 | |
| 487 | /* adc_tm parameters */ |
| 488 | struct qpnp_vadc_chip *vadc_dev; |
| 489 | struct qpnp_adc_tm_chip *adc_tm_dev; |
| 490 | struct qpnp_adc_tm_btm_param adc_param; |
| 491 | |
| 492 | /* jeita parameters */ |
| 493 | int batt_hot_decidegc; |
| 494 | int batt_cold_decidegc; |
| 495 | int batt_warm_decidegc; |
| 496 | int batt_cool_decidegc; |
| 497 | int batt_missing_decidegc; |
| 498 | unsigned int batt_warm_ma; |
| 499 | unsigned int batt_warm_mv; |
| 500 | unsigned int batt_cool_ma; |
| 501 | unsigned int batt_cool_mv; |
| 502 | |
| 503 | /* pinctrl parameters */ |
| 504 | const char *pinctrl_state_name; |
| 505 | struct pinctrl *smb_pinctrl; |
| 506 | }; |
| 507 | |
| 508 | struct smb_irq_info { |
| 509 | const char *name; |
| 510 | int (*smb_irq)(struct smb1351_charger *chip, u8 rt_stat); |
| 511 | int high; |
| 512 | int low; |
| 513 | }; |
| 514 | |
| 515 | struct irq_handler_info { |
| 516 | u8 stat_reg; |
| 517 | u8 val; |
| 518 | u8 prev_val; |
| 519 | struct smb_irq_info irq_info[4]; |
| 520 | }; |
| 521 | |
| 522 | /* USB input charge current */ |
| 523 | static int usb_chg_current[] = { |
| 524 | 500, 685, 1000, 1100, 1200, 1300, 1500, 1600, |
| 525 | 1700, 1800, 2000, 2200, 2500, 3000, |
| 526 | }; |
| 527 | |
| 528 | static int fast_chg_current[] = { |
| 529 | 1000, 1200, 1400, 1600, 1800, 2000, 2200, |
| 530 | 2400, 2600, 2800, 3000, 3400, 3600, 3800, |
| 531 | 4000, 4640, |
| 532 | }; |
| 533 | |
| 534 | static int pre_chg_current[] = { |
| 535 | 200, 300, 400, 500, 600, 700, |
| 536 | }; |
| 537 | |
| 538 | struct battery_status { |
| 539 | bool batt_hot; |
| 540 | bool batt_warm; |
| 541 | bool batt_cool; |
| 542 | bool batt_cold; |
| 543 | bool batt_present; |
| 544 | }; |
| 545 | |
| 546 | enum { |
| 547 | BATT_HOT = 0, |
| 548 | BATT_WARM, |
| 549 | BATT_NORMAL, |
| 550 | BATT_COOL, |
| 551 | BATT_COLD, |
| 552 | BATT_MISSING, |
| 553 | BATT_STATUS_MAX, |
| 554 | }; |
| 555 | |
| 556 | static struct battery_status batt_s[] = { |
| 557 | [BATT_HOT] = {1, 0, 0, 0, 1}, |
| 558 | [BATT_WARM] = {0, 1, 0, 0, 1}, |
| 559 | [BATT_NORMAL] = {0, 0, 0, 0, 1}, |
| 560 | [BATT_COOL] = {0, 0, 1, 0, 1}, |
| 561 | [BATT_COLD] = {0, 0, 0, 1, 1}, |
| 562 | [BATT_MISSING] = {0, 0, 0, 1, 0}, |
| 563 | }; |
| 564 | |
| 565 | static int smb1351_read_reg(struct smb1351_charger *chip, int reg, u8 *val) |
| 566 | { |
| 567 | s32 ret; |
| 568 | |
| 569 | pm_stay_awake(chip->dev); |
| 570 | ret = i2c_smbus_read_byte_data(chip->client, reg); |
| 571 | if (ret < 0) { |
| 572 | pr_err("i2c read fail: can't read from %02x: %d\n", reg, ret); |
| 573 | pm_relax(chip->dev); |
| 574 | return ret; |
| 575 | } |
| 576 | |
| 577 | *val = ret; |
| 578 | |
| 579 | pm_relax(chip->dev); |
| 580 | pr_debug("Reading 0x%02x=0x%02x\n", reg, *val); |
| 581 | return 0; |
| 582 | } |
| 583 | |
| 584 | static int smb1351_write_reg(struct smb1351_charger *chip, int reg, u8 val) |
| 585 | { |
| 586 | s32 ret; |
| 587 | |
| 588 | pm_stay_awake(chip->dev); |
| 589 | ret = i2c_smbus_write_byte_data(chip->client, reg, val); |
| 590 | if (ret < 0) { |
| 591 | pr_err("i2c write fail: can't write %02x to %02x: %d\n", |
| 592 | val, reg, ret); |
| 593 | pm_relax(chip->dev); |
| 594 | return ret; |
| 595 | } |
| 596 | pm_relax(chip->dev); |
| 597 | pr_debug("Writing 0x%02x=0x%02x\n", reg, val); |
| 598 | return 0; |
| 599 | } |
| 600 | |
| 601 | static int smb1351_masked_write(struct smb1351_charger *chip, int reg, |
| 602 | u8 mask, u8 val) |
| 603 | { |
| 604 | s32 rc; |
| 605 | u8 temp; |
| 606 | |
| 607 | rc = smb1351_read_reg(chip, reg, &temp); |
| 608 | if (rc) { |
| 609 | pr_err("read failed: reg=%03X, rc=%d\n", reg, rc); |
| 610 | return rc; |
| 611 | } |
| 612 | temp &= ~mask; |
| 613 | temp |= val & mask; |
| 614 | rc = smb1351_write_reg(chip, reg, temp); |
| 615 | if (rc) { |
| 616 | pr_err("write failed: reg=%03X, rc=%d\n", reg, rc); |
| 617 | return rc; |
| 618 | } |
| 619 | return 0; |
| 620 | } |
| 621 | |
| 622 | static int smb1351_enable_volatile_writes(struct smb1351_charger *chip) |
| 623 | { |
| 624 | int rc; |
| 625 | |
| 626 | rc = smb1351_masked_write(chip, CMD_I2C_REG, CMD_BQ_CFG_ACCESS_BIT, |
| 627 | CMD_BQ_CFG_ACCESS_BIT); |
| 628 | if (rc) |
| 629 | pr_err("Couldn't write CMD_BQ_CFG_ACCESS_BIT rc=%d\n", rc); |
| 630 | |
| 631 | return rc; |
| 632 | } |
| 633 | |
| 634 | static int smb1351_usb_suspend(struct smb1351_charger *chip, int reason, |
| 635 | bool suspend) |
| 636 | { |
| 637 | int rc = 0; |
| 638 | int suspended; |
| 639 | |
| 640 | suspended = chip->usb_suspended_status; |
| 641 | |
| 642 | pr_debug("reason = %d requested_suspend = %d suspended_status = %d\n", |
| 643 | reason, suspend, suspended); |
| 644 | |
| 645 | if (suspend == false) |
| 646 | suspended &= ~reason; |
| 647 | else |
| 648 | suspended |= reason; |
| 649 | |
| 650 | pr_debug("new suspended_status = %d\n", suspended); |
| 651 | |
| 652 | rc = smb1351_masked_write(chip, CMD_INPUT_LIMIT_REG, |
| 653 | CMD_SUSPEND_MODE_BIT, |
| 654 | suspended ? CMD_SUSPEND_MODE_BIT : 0); |
| 655 | if (rc) |
| 656 | pr_err("Couldn't suspend rc = %d\n", rc); |
| 657 | else |
| 658 | chip->usb_suspended_status = suspended; |
| 659 | |
| 660 | return rc; |
| 661 | } |
| 662 | |
| 663 | static int smb1351_battchg_disable(struct smb1351_charger *chip, |
| 664 | int reason, int disable) |
| 665 | { |
| 666 | int rc = 0; |
| 667 | int disabled; |
| 668 | |
| 669 | if (chip->chg_autonomous_mode) { |
| 670 | pr_debug("Charger in autonomous mode\n"); |
| 671 | return 0; |
| 672 | } |
| 673 | |
| 674 | disabled = chip->battchg_disabled_status; |
| 675 | |
| 676 | pr_debug("reason = %d requested_disable = %d disabled_status = %d\n", |
| 677 | reason, disable, disabled); |
| 678 | if (disable == true) |
| 679 | disabled |= reason; |
| 680 | else |
| 681 | disabled &= ~reason; |
| 682 | |
| 683 | pr_debug("new disabled_status = %d\n", disabled); |
| 684 | |
| 685 | rc = smb1351_masked_write(chip, CMD_CHG_REG, CMD_CHG_EN_BIT, |
| 686 | disabled ? 0 : CMD_CHG_ENABLE); |
| 687 | if (rc) |
| 688 | pr_err("Couldn't %s charging rc=%d\n", |
| 689 | disable ? "disable" : "enable", rc); |
| 690 | else |
| 691 | chip->battchg_disabled_status = disabled; |
| 692 | |
| 693 | return rc; |
| 694 | } |
| 695 | |
| 696 | static int smb1351_fastchg_current_set(struct smb1351_charger *chip, |
| 697 | unsigned int fastchg_current) |
| 698 | { |
| 699 | int i, rc; |
| 700 | bool is_pre_chg = false; |
| 701 | |
| 702 | |
| 703 | if ((fastchg_current < SMB1351_CHG_PRE_MIN_MA) || |
| 704 | (fastchg_current > SMB1351_CHG_FAST_MAX_MA)) { |
| 705 | pr_err("bad pre_fastchg current mA=%d asked to set\n", |
| 706 | fastchg_current); |
| 707 | return -EINVAL; |
| 708 | } |
| 709 | |
| 710 | /* |
| 711 | * fast chg current could not support less than 1000mA |
| 712 | * use pre chg to instead for the parallel charging |
| 713 | */ |
| 714 | if (fastchg_current < SMB1351_CHG_FAST_MIN_MA) { |
| 715 | is_pre_chg = true; |
| 716 | pr_debug("is_pre_chg true, current is %d\n", fastchg_current); |
| 717 | } |
| 718 | |
| 719 | if (is_pre_chg) { |
| 720 | /* set prechg current */ |
| 721 | for (i = ARRAY_SIZE(pre_chg_current) - 1; i >= 0; i--) { |
| 722 | if (pre_chg_current[i] <= fastchg_current) |
| 723 | break; |
| 724 | } |
| 725 | if (i < 0) |
| 726 | i = 0; |
| 727 | chip->fastchg_current_max_ma = pre_chg_current[i]; |
| 728 | pr_debug("prechg setting %02x\n", i); |
| 729 | |
| 730 | i = i << SMB1351_CHG_PRE_SHIFT; |
| 731 | |
| 732 | rc = smb1351_masked_write(chip, CHG_OTH_CURRENT_CTRL_REG, |
| 733 | PRECHG_CURRENT_MASK, i); |
| 734 | if (rc) |
| 735 | pr_err("Couldn't write CHG_OTH_CURRENT_CTRL_REG rc=%d\n", |
| 736 | rc); |
| 737 | |
| 738 | return smb1351_masked_write(chip, VARIOUS_FUNC_2_REG, |
| 739 | PRECHG_TO_FASTCHG_BIT, PRECHG_TO_FASTCHG_BIT); |
| 740 | } else { |
| 741 | if (chip->version == SMB_UNKNOWN) |
| 742 | return -EINVAL; |
| 743 | |
| 744 | /* SMB1350 supports FCC upto 2600 mA */ |
| 745 | if (chip->version == SMB1350 && fastchg_current > 2600) |
| 746 | fastchg_current = 2600; |
| 747 | |
| 748 | /* set fastchg current */ |
| 749 | for (i = ARRAY_SIZE(fast_chg_current) - 1; i >= 0; i--) { |
| 750 | if (fast_chg_current[i] <= fastchg_current) |
| 751 | break; |
| 752 | } |
| 753 | if (i < 0) |
| 754 | i = 0; |
| 755 | chip->fastchg_current_max_ma = fast_chg_current[i]; |
| 756 | |
| 757 | i = i << SMB1351_CHG_FAST_SHIFT; |
| 758 | pr_debug("fastchg limit=%d setting %02x\n", |
| 759 | chip->fastchg_current_max_ma, i); |
| 760 | |
| 761 | /* make sure pre chg mode is disabled */ |
| 762 | rc = smb1351_masked_write(chip, VARIOUS_FUNC_2_REG, |
| 763 | PRECHG_TO_FASTCHG_BIT, 0); |
| 764 | if (rc) |
| 765 | pr_err("Couldn't write VARIOUS_FUNC_2_REG rc=%d\n", rc); |
| 766 | |
| 767 | return smb1351_masked_write(chip, CHG_CURRENT_CTRL_REG, |
| 768 | FAST_CHG_CURRENT_MASK, i); |
| 769 | } |
| 770 | } |
| 771 | |
| 772 | #define MIN_FLOAT_MV 3500 |
| 773 | #define MAX_FLOAT_MV 4500 |
| 774 | #define VFLOAT_STEP_MV 20 |
| 775 | |
| 776 | static int smb1351_float_voltage_set(struct smb1351_charger *chip, |
| 777 | int vfloat_mv) |
| 778 | { |
| 779 | u8 temp; |
| 780 | |
| 781 | if ((vfloat_mv < MIN_FLOAT_MV) || (vfloat_mv > MAX_FLOAT_MV)) { |
| 782 | pr_err("bad float voltage mv =%d asked to set\n", vfloat_mv); |
| 783 | return -EINVAL; |
| 784 | } |
| 785 | |
| 786 | temp = (vfloat_mv - MIN_FLOAT_MV) / VFLOAT_STEP_MV; |
| 787 | |
| 788 | return smb1351_masked_write(chip, VFLOAT_REG, VFLOAT_MASK, temp); |
| 789 | } |
| 790 | |
| 791 | static int smb1351_iterm_set(struct smb1351_charger *chip, int iterm_ma) |
| 792 | { |
| 793 | int rc; |
| 794 | u8 reg; |
| 795 | |
| 796 | if (iterm_ma <= 200) |
| 797 | reg = CHG_ITERM_200MA; |
| 798 | else if (iterm_ma <= 300) |
| 799 | reg = CHG_ITERM_300MA; |
| 800 | else if (iterm_ma <= 400) |
| 801 | reg = CHG_ITERM_400MA; |
| 802 | else if (iterm_ma <= 500) |
| 803 | reg = CHG_ITERM_500MA; |
| 804 | else if (iterm_ma <= 600) |
| 805 | reg = CHG_ITERM_600MA; |
| 806 | else |
| 807 | reg = CHG_ITERM_700MA; |
| 808 | |
| 809 | rc = smb1351_masked_write(chip, CHG_OTH_CURRENT_CTRL_REG, |
| 810 | ITERM_MASK, reg); |
| 811 | if (rc) { |
| 812 | pr_err("Couldn't set iterm rc = %d\n", rc); |
| 813 | return rc; |
| 814 | } |
| 815 | /* enable the iterm */ |
| 816 | rc = smb1351_masked_write(chip, CHG_CTRL_REG, |
| 817 | ITERM_EN_BIT, ITERM_ENABLE); |
| 818 | if (rc) { |
| 819 | pr_err("Couldn't enable iterm rc = %d\n", rc); |
| 820 | return rc; |
| 821 | } |
| 822 | return 0; |
| 823 | } |
| 824 | |
| 825 | static int smb1351_chg_otg_regulator_enable(struct regulator_dev *rdev) |
| 826 | { |
| 827 | int rc = 0; |
| 828 | struct smb1351_charger *chip = rdev_get_drvdata(rdev); |
| 829 | |
| 830 | rc = smb1351_masked_write(chip, CMD_CHG_REG, CMD_OTG_EN_BIT, |
| 831 | CMD_OTG_EN_BIT); |
| 832 | if (rc) |
| 833 | pr_err("Couldn't enable OTG mode rc=%d\n", rc); |
| 834 | return rc; |
| 835 | } |
| 836 | |
| 837 | static int smb1351_chg_otg_regulator_disable(struct regulator_dev *rdev) |
| 838 | { |
| 839 | int rc = 0; |
| 840 | struct smb1351_charger *chip = rdev_get_drvdata(rdev); |
| 841 | |
| 842 | rc = smb1351_masked_write(chip, CMD_CHG_REG, CMD_OTG_EN_BIT, 0); |
| 843 | if (rc) |
| 844 | pr_err("Couldn't disable OTG mode rc=%d\n", rc); |
| 845 | return rc; |
| 846 | } |
| 847 | |
| 848 | static int smb1351_chg_otg_regulator_is_enable(struct regulator_dev *rdev) |
| 849 | { |
| 850 | int rc = 0; |
| 851 | u8 reg = 0; |
| 852 | struct smb1351_charger *chip = rdev_get_drvdata(rdev); |
| 853 | |
| 854 | rc = smb1351_read_reg(chip, CMD_CHG_REG, ®); |
| 855 | if (rc) { |
| 856 | pr_err("Couldn't read OTG enable bit rc=%d\n", rc); |
| 857 | return rc; |
| 858 | } |
| 859 | |
| 860 | return (reg & CMD_OTG_EN_BIT) ? 1 : 0; |
| 861 | } |
| 862 | |
| 863 | struct regulator_ops smb1351_chg_otg_reg_ops = { |
| 864 | .enable = smb1351_chg_otg_regulator_enable, |
| 865 | .disable = smb1351_chg_otg_regulator_disable, |
| 866 | .is_enabled = smb1351_chg_otg_regulator_is_enable, |
| 867 | }; |
| 868 | |
| 869 | static int smb1351_regulator_init(struct smb1351_charger *chip) |
| 870 | { |
| 871 | int rc = 0; |
| 872 | struct regulator_config cfg = {}; |
| 873 | |
| 874 | chip->otg_vreg.rdesc.owner = THIS_MODULE; |
| 875 | chip->otg_vreg.rdesc.type = REGULATOR_VOLTAGE; |
| 876 | chip->otg_vreg.rdesc.ops = &smb1351_chg_otg_reg_ops; |
| 877 | chip->otg_vreg.rdesc.name = |
| 878 | chip->dev->of_node->name; |
| 879 | chip->otg_vreg.rdesc.of_match = |
| 880 | chip->dev->of_node->name; |
| 881 | |
| 882 | cfg.dev = chip->dev; |
| 883 | cfg.driver_data = chip; |
| 884 | |
| 885 | chip->otg_vreg.rdev = regulator_register( |
| 886 | &chip->otg_vreg.rdesc, &cfg); |
| 887 | if (IS_ERR(chip->otg_vreg.rdev)) { |
| 888 | rc = PTR_ERR(chip->otg_vreg.rdev); |
| 889 | chip->otg_vreg.rdev = NULL; |
| 890 | if (rc != -EPROBE_DEFER) |
| 891 | pr_err("OTG reg failed, rc=%d\n", rc); |
| 892 | } |
| 893 | return rc; |
| 894 | } |
| 895 | |
| 896 | static int smb_chip_get_version(struct smb1351_charger *chip) |
| 897 | { |
| 898 | u8 ver; |
| 899 | int rc = 0; |
| 900 | |
| 901 | if (chip->version == SMB_UNKNOWN) { |
| 902 | rc = smb1351_read_reg(chip, VERSION_REG, &ver); |
| 903 | if (rc) { |
| 904 | pr_err("Couldn't read version rc=%d\n", rc); |
| 905 | return rc; |
| 906 | } |
| 907 | |
| 908 | /* If bit 1 is set, it is SMB1350 */ |
| 909 | if (ver & VERSION_MASK) |
| 910 | chip->version = SMB1350; |
| 911 | else |
| 912 | chip->version = SMB1351; |
| 913 | } |
| 914 | |
| 915 | return rc; |
| 916 | } |
| 917 | |
| 918 | static int smb1351_hw_init(struct smb1351_charger *chip) |
| 919 | { |
| 920 | int rc; |
| 921 | u8 reg = 0, mask = 0; |
| 922 | |
| 923 | /* configure smb_pinctrl to enable irqs */ |
| 924 | if (chip->pinctrl_state_name) { |
| 925 | chip->smb_pinctrl = pinctrl_get_select(chip->dev, |
| 926 | chip->pinctrl_state_name); |
| 927 | if (IS_ERR(chip->smb_pinctrl)) { |
| 928 | pr_err("Could not get/set %s pinctrl state rc = %ld\n", |
| 929 | chip->pinctrl_state_name, |
| 930 | PTR_ERR(chip->smb_pinctrl)); |
| 931 | return PTR_ERR(chip->smb_pinctrl); |
| 932 | } |
| 933 | } |
| 934 | |
| 935 | /* |
| 936 | * If the charger is pre-configured for autonomous operation, |
| 937 | * do not apply additional settings |
| 938 | */ |
| 939 | if (chip->chg_autonomous_mode) { |
| 940 | pr_debug("Charger configured for autonomous mode\n"); |
| 941 | return 0; |
| 942 | } |
| 943 | |
| 944 | rc = smb_chip_get_version(chip); |
| 945 | if (rc) { |
| 946 | pr_err("Couldn't get version rc = %d\n", rc); |
| 947 | return rc; |
| 948 | } |
| 949 | |
| 950 | rc = smb1351_enable_volatile_writes(chip); |
| 951 | if (rc) { |
| 952 | pr_err("Couldn't configure volatile writes rc=%d\n", rc); |
| 953 | return rc; |
| 954 | } |
| 955 | |
| 956 | /* setup battery missing source */ |
| 957 | reg = BATT_MISSING_THERM_PIN_SOURCE_BIT; |
| 958 | mask = BATT_MISSING_THERM_PIN_SOURCE_BIT; |
| 959 | rc = smb1351_masked_write(chip, HVDCP_BATT_MISSING_CTRL_REG, |
| 960 | mask, reg); |
| 961 | if (rc) { |
| 962 | pr_err("Couldn't set HVDCP_BATT_MISSING_CTRL_REG rc=%d\n", rc); |
| 963 | return rc; |
| 964 | } |
| 965 | /* setup defaults for CHG_PIN_EN_CTRL_REG */ |
| 966 | reg = EN_BY_I2C_0_DISABLE | USBCS_CTRL_BY_I2C | CHG_ERR_BIT | |
| 967 | APSD_DONE_BIT | LED_BLINK_FUNC_BIT; |
| 968 | mask = EN_PIN_CTRL_MASK | USBCS_CTRL_BIT | CHG_ERR_BIT | |
| 969 | APSD_DONE_BIT | LED_BLINK_FUNC_BIT; |
| 970 | rc = smb1351_masked_write(chip, CHG_PIN_EN_CTRL_REG, mask, reg); |
| 971 | if (rc) { |
| 972 | pr_err("Couldn't set CHG_PIN_EN_CTRL_REG rc=%d\n", rc); |
| 973 | return rc; |
| 974 | } |
| 975 | /* setup USB 2.0/3.0 detection and USB 500/100 command polarity */ |
| 976 | reg = USB_2_3_MODE_SEL_BY_I2C | USB_CMD_POLARITY_500_1_100_0; |
| 977 | mask = USB_2_3_MODE_SEL_BIT | USB_5_1_CMD_POLARITY_BIT; |
| 978 | rc = smb1351_masked_write(chip, CHG_OTH_CURRENT_CTRL_REG, mask, reg); |
| 979 | if (rc) { |
| 980 | pr_err("Couldn't set CHG_OTH_CURRENT_CTRL_REG rc=%d\n", rc); |
| 981 | return rc; |
| 982 | } |
| 983 | /* setup USB suspend, AICL and APSD */ |
| 984 | reg = SUSPEND_MODE_CTRL_BY_I2C | AICL_EN_BIT; |
| 985 | if (!chip->disable_apsd) |
| 986 | reg |= APSD_EN_BIT; |
| 987 | mask = SUSPEND_MODE_CTRL_BIT | AICL_EN_BIT | APSD_EN_BIT; |
| 988 | rc = smb1351_masked_write(chip, VARIOUS_FUNC_REG, mask, reg); |
| 989 | if (rc) { |
| 990 | pr_err("Couldn't set VARIOUS_FUNC_REG rc=%d\n", rc); |
| 991 | return rc; |
| 992 | } |
| 993 | /* Fault and Status IRQ configuration */ |
| 994 | reg = HOT_COLD_HARD_LIMIT_BIT | HOT_COLD_SOFT_LIMIT_BIT |
| 995 | | INPUT_OVLO_BIT | INPUT_UVLO_BIT | AICL_DONE_FAIL_BIT; |
| 996 | rc = smb1351_write_reg(chip, FAULT_INT_REG, reg); |
| 997 | if (rc) { |
| 998 | pr_err("Couldn't set FAULT_INT_REG rc=%d\n", rc); |
| 999 | return rc; |
| 1000 | } |
| 1001 | reg = CHG_OR_PRECHG_TIMEOUT_BIT | BATT_OVP_BIT | |
| 1002 | FAST_TERM_TAPER_RECHG_INHIBIT_BIT | |
| 1003 | BATT_MISSING_BIT | BATT_LOW_BIT; |
| 1004 | rc = smb1351_write_reg(chip, STATUS_INT_REG, reg); |
| 1005 | if (rc) { |
| 1006 | pr_err("Couldn't set STATUS_INT_REG rc=%d\n", rc); |
| 1007 | return rc; |
| 1008 | } |
| 1009 | /* setup THERM Monitor */ |
| 1010 | if (!chip->using_pmic_therm) { |
| 1011 | rc = smb1351_masked_write(chip, THERM_A_CTRL_REG, |
| 1012 | THERM_MONITOR_BIT, THERM_MONITOR_EN); |
| 1013 | if (rc) { |
| 1014 | pr_err("Couldn't set THERM_A_CTRL_REG rc=%d\n", rc); |
| 1015 | return rc; |
| 1016 | } |
| 1017 | } |
| 1018 | /* set the fast charge current limit */ |
| 1019 | rc = smb1351_fastchg_current_set(chip, |
| 1020 | chip->target_fastchg_current_max_ma); |
| 1021 | if (rc) { |
| 1022 | pr_err("Couldn't set fastchg current rc=%d\n", rc); |
| 1023 | return rc; |
| 1024 | } |
| 1025 | |
| 1026 | /* set the float voltage */ |
| 1027 | if (chip->vfloat_mv != -EINVAL) { |
| 1028 | rc = smb1351_float_voltage_set(chip, chip->vfloat_mv); |
| 1029 | if (rc) { |
| 1030 | pr_err("Couldn't set float voltage rc = %d\n", rc); |
| 1031 | return rc; |
| 1032 | } |
| 1033 | } |
| 1034 | |
| 1035 | /* set iterm */ |
| 1036 | if (chip->iterm_ma != -EINVAL) { |
| 1037 | if (chip->iterm_disabled) { |
| 1038 | pr_err("Error: Both iterm_disabled and iterm_ma set\n"); |
| 1039 | return -EINVAL; |
| 1040 | } |
| 1041 | rc = smb1351_iterm_set(chip, chip->iterm_ma); |
| 1042 | if (rc) { |
| 1043 | pr_err("Couldn't set iterm rc = %d\n", rc); |
| 1044 | return rc; |
| 1045 | } |
| 1046 | } else if (chip->iterm_disabled) { |
| 1047 | rc = smb1351_masked_write(chip, CHG_CTRL_REG, |
| 1048 | ITERM_EN_BIT, ITERM_DISABLE); |
| 1049 | if (rc) { |
| 1050 | pr_err("Couldn't set iterm rc = %d\n", rc); |
| 1051 | return rc; |
| 1052 | } |
| 1053 | } |
| 1054 | |
| 1055 | /* set recharge-threshold */ |
| 1056 | if (chip->recharge_mv != -EINVAL) { |
| 1057 | if (chip->recharge_disabled) { |
| 1058 | pr_err("Error: Both recharge_disabled and recharge_mv set\n"); |
| 1059 | return -EINVAL; |
| 1060 | } |
| 1061 | |
| 1062 | reg = AUTO_RECHG_ENABLE; |
| 1063 | if (chip->recharge_mv > 50) |
| 1064 | reg |= AUTO_RECHG_TH_100MV; |
| 1065 | else |
| 1066 | reg |= AUTO_RECHG_TH_50MV; |
| 1067 | |
| 1068 | rc = smb1351_masked_write(chip, CHG_CTRL_REG, |
| 1069 | AUTO_RECHG_BIT | |
| 1070 | AUTO_RECHG_TH_BIT, reg); |
| 1071 | if (rc) { |
| 1072 | pr_err("Couldn't set rechg-cfg rc = %d\n", rc); |
| 1073 | return rc; |
| 1074 | } |
| 1075 | } else if (chip->recharge_disabled) { |
| 1076 | rc = smb1351_masked_write(chip, CHG_CTRL_REG, |
| 1077 | AUTO_RECHG_BIT, |
| 1078 | AUTO_RECHG_DISABLE); |
| 1079 | if (rc) { |
| 1080 | pr_err("Couldn't disable auto-rechg rc = %d\n", rc); |
| 1081 | return rc; |
| 1082 | } |
| 1083 | } |
| 1084 | |
| 1085 | /* enable/disable charging by suspending usb */ |
| 1086 | rc = smb1351_usb_suspend(chip, USER, chip->usb_suspended_status); |
| 1087 | if (rc) { |
| 1088 | pr_err("Unable to %s battery charging. rc=%d\n", |
| 1089 | chip->usb_suspended_status ? "disable" : "enable", |
| 1090 | rc); |
| 1091 | } |
| 1092 | |
| 1093 | return rc; |
| 1094 | } |
| 1095 | |
| 1096 | static enum power_supply_property smb1351_battery_properties[] = { |
| 1097 | POWER_SUPPLY_PROP_STATUS, |
| 1098 | POWER_SUPPLY_PROP_PRESENT, |
| 1099 | POWER_SUPPLY_PROP_CHARGING_ENABLED, |
| 1100 | POWER_SUPPLY_PROP_BATTERY_CHARGING_ENABLED, |
| 1101 | POWER_SUPPLY_PROP_CHARGE_TYPE, |
| 1102 | POWER_SUPPLY_PROP_CAPACITY, |
| 1103 | POWER_SUPPLY_PROP_HEALTH, |
| 1104 | POWER_SUPPLY_PROP_TEMP, |
| 1105 | POWER_SUPPLY_PROP_TECHNOLOGY, |
| 1106 | POWER_SUPPLY_PROP_MODEL_NAME, |
| 1107 | }; |
| 1108 | |
| 1109 | static int smb1351_get_prop_batt_status(struct smb1351_charger *chip) |
| 1110 | { |
| 1111 | int rc; |
| 1112 | u8 reg = 0; |
| 1113 | |
| 1114 | if (chip->batt_full) |
| 1115 | return POWER_SUPPLY_STATUS_FULL; |
| 1116 | |
| 1117 | rc = smb1351_read_reg(chip, STATUS_4_REG, ®); |
| 1118 | if (rc) { |
| 1119 | pr_err("Couldn't read STATUS_4 rc = %d\n", rc); |
| 1120 | return POWER_SUPPLY_STATUS_UNKNOWN; |
| 1121 | } |
| 1122 | |
| 1123 | pr_debug("STATUS_4_REG(0x3A)=%x\n", reg); |
| 1124 | |
| 1125 | if (reg & STATUS_HOLD_OFF_BIT) |
| 1126 | return POWER_SUPPLY_STATUS_NOT_CHARGING; |
| 1127 | |
| 1128 | if (reg & STATUS_CHG_MASK) |
| 1129 | return POWER_SUPPLY_STATUS_CHARGING; |
| 1130 | |
| 1131 | return POWER_SUPPLY_STATUS_DISCHARGING; |
| 1132 | } |
| 1133 | |
| 1134 | static int smb1351_get_prop_batt_present(struct smb1351_charger *chip) |
| 1135 | { |
| 1136 | return !chip->battery_missing; |
| 1137 | } |
| 1138 | |
| 1139 | static int smb1351_get_prop_batt_capacity(struct smb1351_charger *chip) |
| 1140 | { |
| 1141 | union power_supply_propval ret = {0, }; |
| 1142 | |
| 1143 | if (chip->fake_battery_soc >= 0) |
| 1144 | return chip->fake_battery_soc; |
| 1145 | |
| 1146 | if (chip->bms_psy) { |
| 1147 | power_supply_get_property(chip->bms_psy, |
| 1148 | POWER_SUPPLY_PROP_CAPACITY, &ret); |
| 1149 | return ret.intval; |
| 1150 | } |
| 1151 | pr_debug("return DEFAULT_BATT_CAPACITY\n"); |
| 1152 | return DEFAULT_BATT_CAPACITY; |
| 1153 | } |
| 1154 | |
| 1155 | static int smb1351_get_prop_batt_temp(struct smb1351_charger *chip) |
| 1156 | { |
| 1157 | union power_supply_propval ret = {0, }; |
| 1158 | int rc = 0; |
| 1159 | struct qpnp_vadc_result results; |
| 1160 | |
| 1161 | if (chip->bms_psy) { |
| 1162 | power_supply_get_property(chip->bms_psy, |
| 1163 | POWER_SUPPLY_PROP_TEMP, &ret); |
| 1164 | return ret.intval; |
| 1165 | } |
| 1166 | if (chip->vadc_dev) { |
| 1167 | rc = qpnp_vadc_read(chip->vadc_dev, |
| 1168 | LR_MUX1_BATT_THERM, &results); |
| 1169 | if (rc) |
| 1170 | pr_debug("Unable to read adc batt temp rc=%d\n", rc); |
| 1171 | else |
| 1172 | return (int)results.physical; |
| 1173 | } |
| 1174 | |
| 1175 | pr_debug("return default temperature\n"); |
| 1176 | return DEFAULT_BATT_TEMP; |
| 1177 | } |
| 1178 | |
| 1179 | static int smb1351_get_prop_charge_type(struct smb1351_charger *chip) |
| 1180 | { |
| 1181 | int rc; |
| 1182 | u8 reg = 0; |
| 1183 | |
| 1184 | rc = smb1351_read_reg(chip, STATUS_4_REG, ®); |
| 1185 | if (rc) { |
| 1186 | pr_err("Couldn't read STATUS_4 rc = %d\n", rc); |
| 1187 | return POWER_SUPPLY_CHARGE_TYPE_UNKNOWN; |
| 1188 | } |
| 1189 | |
| 1190 | pr_debug("STATUS_4_REG(0x3A)=%x\n", reg); |
| 1191 | |
| 1192 | reg &= STATUS_CHG_MASK; |
| 1193 | |
| 1194 | if (reg == STATUS_FAST_CHARGING) |
| 1195 | return POWER_SUPPLY_CHARGE_TYPE_FAST; |
| 1196 | else if (reg == STATUS_TAPER_CHARGING) |
| 1197 | return POWER_SUPPLY_CHARGE_TYPE_TAPER; |
| 1198 | else if (reg == STATUS_PRE_CHARGING) |
| 1199 | return POWER_SUPPLY_CHARGE_TYPE_TRICKLE; |
| 1200 | else |
| 1201 | return POWER_SUPPLY_CHARGE_TYPE_NONE; |
| 1202 | } |
| 1203 | |
| 1204 | static int smb1351_get_prop_batt_health(struct smb1351_charger *chip) |
| 1205 | { |
| 1206 | union power_supply_propval ret = {0, }; |
| 1207 | |
| 1208 | if (chip->batt_hot) |
| 1209 | ret.intval = POWER_SUPPLY_HEALTH_OVERHEAT; |
| 1210 | else if (chip->batt_cold) |
| 1211 | ret.intval = POWER_SUPPLY_HEALTH_COLD; |
| 1212 | else if (chip->batt_warm) |
| 1213 | ret.intval = POWER_SUPPLY_HEALTH_WARM; |
| 1214 | else if (chip->batt_cool) |
| 1215 | ret.intval = POWER_SUPPLY_HEALTH_COOL; |
| 1216 | else |
| 1217 | ret.intval = POWER_SUPPLY_HEALTH_GOOD; |
| 1218 | |
| 1219 | return ret.intval; |
| 1220 | } |
| 1221 | |
| 1222 | static int smb1351_set_usb_chg_current(struct smb1351_charger *chip, |
| 1223 | int current_ma) |
| 1224 | { |
| 1225 | int i, rc = 0; |
| 1226 | u8 reg = 0, mask = 0; |
| 1227 | |
| 1228 | pr_debug("USB current_ma = %d\n", current_ma); |
| 1229 | |
| 1230 | if (chip->chg_autonomous_mode) { |
| 1231 | pr_debug("Charger in autonomous mode\n"); |
| 1232 | return 0; |
| 1233 | } |
| 1234 | |
| 1235 | /* set suspend bit when urrent_ma <= 2 */ |
| 1236 | if (current_ma <= SUSPEND_CURRENT_MA) { |
| 1237 | smb1351_usb_suspend(chip, CURRENT, true); |
| 1238 | pr_debug("USB suspend\n"); |
| 1239 | return 0; |
| 1240 | } |
| 1241 | |
| 1242 | if (current_ma > SUSPEND_CURRENT_MA && |
| 1243 | current_ma < USB2_MIN_CURRENT_MA) |
| 1244 | current_ma = USB2_MIN_CURRENT_MA; |
| 1245 | |
| 1246 | if (current_ma == USB2_MIN_CURRENT_MA) { |
| 1247 | /* USB 2.0 - 100mA */ |
| 1248 | reg = CMD_USB_2_MODE | CMD_USB_100_MODE; |
| 1249 | } else if (current_ma == USB3_MIN_CURRENT_MA) { |
| 1250 | /* USB 3.0 - 150mA */ |
| 1251 | reg = CMD_USB_3_MODE | CMD_USB_100_MODE; |
| 1252 | } else if (current_ma == USB2_MAX_CURRENT_MA) { |
| 1253 | /* USB 2.0 - 500mA */ |
| 1254 | reg = CMD_USB_2_MODE | CMD_USB_500_MODE; |
| 1255 | } else if (current_ma == USB3_MAX_CURRENT_MA) { |
| 1256 | /* USB 3.0 - 900mA */ |
| 1257 | reg = CMD_USB_3_MODE | CMD_USB_500_MODE; |
| 1258 | } else if (current_ma > USB2_MAX_CURRENT_MA) { |
| 1259 | /* HC mode - if none of the above */ |
| 1260 | reg = CMD_USB_AC_MODE; |
| 1261 | |
| 1262 | for (i = ARRAY_SIZE(usb_chg_current) - 1; i >= 0; i--) { |
| 1263 | if (usb_chg_current[i] <= current_ma) |
| 1264 | break; |
| 1265 | } |
| 1266 | if (i < 0) |
| 1267 | i = 0; |
| 1268 | rc = smb1351_masked_write(chip, CHG_CURRENT_CTRL_REG, |
| 1269 | AC_INPUT_CURRENT_LIMIT_MASK, i); |
| 1270 | if (rc) { |
| 1271 | pr_err("Couldn't set input mA rc=%d\n", rc); |
| 1272 | return rc; |
| 1273 | } |
| 1274 | } |
| 1275 | /* control input current mode by command */ |
| 1276 | reg |= CMD_INPUT_CURRENT_MODE_CMD; |
| 1277 | mask = CMD_INPUT_CURRENT_MODE_BIT | CMD_USB_2_3_SEL_BIT | |
| 1278 | CMD_USB_1_5_AC_CTRL_MASK; |
| 1279 | rc = smb1351_masked_write(chip, CMD_INPUT_LIMIT_REG, mask, reg); |
| 1280 | if (rc) { |
| 1281 | pr_err("Couldn't set charging mode rc = %d\n", rc); |
| 1282 | return rc; |
| 1283 | } |
| 1284 | |
| 1285 | /* unset the suspend bit here */ |
| 1286 | smb1351_usb_suspend(chip, CURRENT, false); |
| 1287 | |
| 1288 | return rc; |
| 1289 | } |
| 1290 | |
| 1291 | static int smb1351_batt_property_is_writeable(struct power_supply *psy, |
| 1292 | enum power_supply_property psp) |
| 1293 | { |
| 1294 | switch (psp) { |
| 1295 | case POWER_SUPPLY_PROP_CHARGING_ENABLED: |
| 1296 | case POWER_SUPPLY_PROP_BATTERY_CHARGING_ENABLED: |
| 1297 | case POWER_SUPPLY_PROP_CAPACITY: |
| 1298 | return 1; |
| 1299 | default: |
| 1300 | break; |
| 1301 | } |
| 1302 | return 0; |
| 1303 | } |
| 1304 | |
| 1305 | static int smb1351_battery_set_property(struct power_supply *psy, |
| 1306 | enum power_supply_property prop, |
| 1307 | const union power_supply_propval *val) |
| 1308 | { |
| 1309 | int rc; |
| 1310 | struct smb1351_charger *chip = power_supply_get_drvdata(psy); |
| 1311 | |
| 1312 | switch (prop) { |
| 1313 | case POWER_SUPPLY_PROP_STATUS: |
| 1314 | if (!chip->bms_controlled_charging) |
| 1315 | return -EINVAL; |
| 1316 | switch (val->intval) { |
| 1317 | case POWER_SUPPLY_STATUS_FULL: |
| 1318 | rc = smb1351_battchg_disable(chip, SOC, true); |
| 1319 | if (rc) { |
| 1320 | pr_err("Couldn't disable charging rc = %d\n", |
| 1321 | rc); |
| 1322 | } else { |
| 1323 | chip->batt_full = true; |
| 1324 | pr_debug("status = FULL, batt_full = %d\n", |
| 1325 | chip->batt_full); |
| 1326 | } |
| 1327 | break; |
| 1328 | case POWER_SUPPLY_STATUS_DISCHARGING: |
| 1329 | chip->batt_full = false; |
| 1330 | power_supply_changed(chip->batt_psy); |
| 1331 | pr_debug("status = DISCHARGING, batt_full = %d\n", |
| 1332 | chip->batt_full); |
| 1333 | break; |
| 1334 | case POWER_SUPPLY_STATUS_CHARGING: |
| 1335 | rc = smb1351_battchg_disable(chip, SOC, false); |
| 1336 | if (rc) { |
| 1337 | pr_err("Couldn't enable charging rc = %d\n", |
| 1338 | rc); |
| 1339 | } else { |
| 1340 | chip->batt_full = false; |
| 1341 | pr_debug("status = CHARGING, batt_full = %d\n", |
| 1342 | chip->batt_full); |
| 1343 | } |
| 1344 | break; |
| 1345 | default: |
| 1346 | return -EINVAL; |
| 1347 | } |
| 1348 | break; |
| 1349 | case POWER_SUPPLY_PROP_CHARGING_ENABLED: |
| 1350 | smb1351_usb_suspend(chip, USER, !val->intval); |
| 1351 | break; |
| 1352 | case POWER_SUPPLY_PROP_BATTERY_CHARGING_ENABLED: |
| 1353 | smb1351_battchg_disable(chip, USER, !val->intval); |
| 1354 | break; |
| 1355 | case POWER_SUPPLY_PROP_CAPACITY: |
| 1356 | chip->fake_battery_soc = val->intval; |
| 1357 | power_supply_changed(chip->batt_psy); |
| 1358 | break; |
| 1359 | default: |
| 1360 | return -EINVAL; |
| 1361 | } |
| 1362 | |
| 1363 | return 0; |
| 1364 | } |
| 1365 | |
| 1366 | static int smb1351_battery_get_property(struct power_supply *psy, |
| 1367 | enum power_supply_property prop, |
| 1368 | union power_supply_propval *val) |
| 1369 | { |
| 1370 | struct smb1351_charger *chip = power_supply_get_drvdata(psy); |
| 1371 | |
| 1372 | switch (prop) { |
| 1373 | case POWER_SUPPLY_PROP_STATUS: |
| 1374 | val->intval = smb1351_get_prop_batt_status(chip); |
| 1375 | break; |
| 1376 | case POWER_SUPPLY_PROP_PRESENT: |
| 1377 | val->intval = smb1351_get_prop_batt_present(chip); |
| 1378 | break; |
| 1379 | case POWER_SUPPLY_PROP_CAPACITY: |
| 1380 | val->intval = smb1351_get_prop_batt_capacity(chip); |
| 1381 | break; |
| 1382 | case POWER_SUPPLY_PROP_CHARGING_ENABLED: |
| 1383 | val->intval = !chip->usb_suspended_status; |
| 1384 | break; |
| 1385 | case POWER_SUPPLY_PROP_BATTERY_CHARGING_ENABLED: |
| 1386 | val->intval = !chip->battchg_disabled_status; |
| 1387 | break; |
| 1388 | case POWER_SUPPLY_PROP_CHARGE_TYPE: |
| 1389 | val->intval = smb1351_get_prop_charge_type(chip); |
| 1390 | break; |
| 1391 | case POWER_SUPPLY_PROP_HEALTH: |
| 1392 | val->intval = smb1351_get_prop_batt_health(chip); |
| 1393 | break; |
| 1394 | case POWER_SUPPLY_PROP_TEMP: |
| 1395 | val->intval = smb1351_get_prop_batt_temp(chip); |
| 1396 | break; |
| 1397 | case POWER_SUPPLY_PROP_TECHNOLOGY: |
| 1398 | val->intval = POWER_SUPPLY_TECHNOLOGY_LION; |
| 1399 | break; |
| 1400 | case POWER_SUPPLY_PROP_MODEL_NAME: |
| 1401 | val->strval = "smb1351"; |
| 1402 | break; |
| 1403 | default: |
| 1404 | return -EINVAL; |
| 1405 | } |
| 1406 | return 0; |
| 1407 | } |
| 1408 | |
| 1409 | static enum power_supply_property smb1351_parallel_properties[] = { |
| 1410 | POWER_SUPPLY_PROP_CHARGING_ENABLED, |
| 1411 | POWER_SUPPLY_PROP_STATUS, |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1412 | POWER_SUPPLY_PROP_CURRENT_MAX, |
| 1413 | POWER_SUPPLY_PROP_VOLTAGE_MAX, |
| 1414 | POWER_SUPPLY_PROP_INPUT_CURRENT_LIMITED, |
| 1415 | POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX, |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1416 | POWER_SUPPLY_PROP_CHARGE_TYPE, |
Abhijeet Dharmapurikar | a8bd6f0 | 2017-01-30 15:43:04 -0800 | [diff] [blame] | 1417 | POWER_SUPPLY_PROP_PARALLEL_MODE, |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1418 | }; |
| 1419 | |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1420 | static int smb1351_parallel_set_chg_suspend(struct smb1351_charger *chip, |
| 1421 | int suspend) |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1422 | { |
| 1423 | int rc; |
| 1424 | u8 reg, mask = 0; |
| 1425 | |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1426 | if (chip->parallel_charger_suspended == suspend) { |
| 1427 | pr_debug("Skip same state request suspended = %d suspend=%d\n", |
| 1428 | chip->parallel_charger_suspended, !suspend); |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1429 | return 0; |
| 1430 | } |
| 1431 | |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1432 | if (!suspend) { |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1433 | rc = smb_chip_get_version(chip); |
| 1434 | if (rc) { |
| 1435 | pr_err("Couldn't get version rc = %d\n", rc); |
| 1436 | return rc; |
| 1437 | } |
| 1438 | |
| 1439 | rc = smb1351_enable_volatile_writes(chip); |
| 1440 | if (rc) { |
| 1441 | pr_err("Couldn't configure for volatile rc = %d\n", rc); |
| 1442 | return rc; |
| 1443 | } |
| 1444 | |
| 1445 | /* set the float voltage */ |
| 1446 | if (chip->vfloat_mv != -EINVAL) { |
| 1447 | rc = smb1351_float_voltage_set(chip, chip->vfloat_mv); |
| 1448 | if (rc) { |
| 1449 | pr_err("Couldn't set float voltage rc = %d\n", |
| 1450 | rc); |
| 1451 | return rc; |
| 1452 | } |
| 1453 | } |
| 1454 | |
| 1455 | /* set recharge-threshold and enable auto recharge */ |
| 1456 | if (chip->recharge_mv != -EINVAL) { |
| 1457 | reg = AUTO_RECHG_ENABLE; |
| 1458 | if (chip->recharge_mv > 50) |
| 1459 | reg |= AUTO_RECHG_TH_100MV; |
| 1460 | else |
| 1461 | reg |= AUTO_RECHG_TH_50MV; |
| 1462 | |
| 1463 | rc = smb1351_masked_write(chip, CHG_CTRL_REG, |
| 1464 | AUTO_RECHG_BIT | |
| 1465 | AUTO_RECHG_TH_BIT, reg); |
| 1466 | if (rc) { |
| 1467 | pr_err("Couldn't set rechg-cfg rc = %d\n", rc); |
| 1468 | return rc; |
| 1469 | } |
| 1470 | } |
| 1471 | |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1472 | /* control USB suspend via command bits */ |
| 1473 | rc = smb1351_masked_write(chip, VARIOUS_FUNC_REG, |
| 1474 | APSD_EN_BIT | SUSPEND_MODE_CTRL_BIT, |
| 1475 | SUSPEND_MODE_CTRL_BY_I2C); |
| 1476 | if (rc) { |
| 1477 | pr_err("Couldn't set USB suspend rc=%d\n", rc); |
| 1478 | return rc; |
| 1479 | } |
| 1480 | |
| 1481 | /* |
| 1482 | * When present is being set force USB suspend, start charging |
| 1483 | * only when POWER_SUPPLY_PROP_CURRENT_MAX is set. |
| 1484 | */ |
| 1485 | rc = smb1351_usb_suspend(chip, CURRENT, true); |
| 1486 | if (rc) { |
| 1487 | pr_err("failed to suspend rc=%d\n", rc); |
| 1488 | return rc; |
| 1489 | } |
| 1490 | chip->usb_psy_ma = SUSPEND_CURRENT_MA; |
| 1491 | |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1492 | /* set chg en by pin active low */ |
| 1493 | reg = chip->parallel_pin_polarity_setting | USBCS_CTRL_BY_I2C; |
| 1494 | rc = smb1351_masked_write(chip, CHG_PIN_EN_CTRL_REG, |
| 1495 | EN_PIN_CTRL_MASK | USBCS_CTRL_BIT, reg); |
| 1496 | if (rc) { |
| 1497 | pr_err("Couldn't set en pin rc=%d\n", rc); |
| 1498 | return rc; |
| 1499 | } |
| 1500 | |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1501 | /* |
| 1502 | * setup USB 2.0/3.0 detection and USB 500/100 |
| 1503 | * command polarity |
| 1504 | */ |
| 1505 | reg = USB_2_3_MODE_SEL_BY_I2C | USB_CMD_POLARITY_500_1_100_0; |
| 1506 | mask = USB_2_3_MODE_SEL_BIT | USB_5_1_CMD_POLARITY_BIT; |
| 1507 | rc = smb1351_masked_write(chip, |
| 1508 | CHG_OTH_CURRENT_CTRL_REG, mask, reg); |
| 1509 | if (rc) { |
| 1510 | pr_err("Couldn't set CHG_OTH_CURRENT_CTRL_REG rc=%d\n", |
| 1511 | rc); |
| 1512 | return rc; |
| 1513 | } |
| 1514 | |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1515 | rc = smb1351_fastchg_current_set(chip, |
| 1516 | chip->target_fastchg_current_max_ma); |
| 1517 | if (rc) { |
| 1518 | pr_err("Couldn't set fastchg current rc=%d\n", rc); |
| 1519 | return rc; |
| 1520 | } |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1521 | chip->parallel_charger_suspended = false; |
| 1522 | } else { |
| 1523 | rc = smb1351_usb_suspend(chip, CURRENT, true); |
| 1524 | if (rc) |
| 1525 | pr_debug("failed to suspend rc=%d\n", rc); |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1526 | |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1527 | chip->usb_psy_ma = SUSPEND_CURRENT_MA; |
| 1528 | chip->parallel_charger_suspended = true; |
| 1529 | } |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1530 | |
| 1531 | return 0; |
| 1532 | } |
| 1533 | |
| 1534 | static int smb1351_get_closest_usb_setpoint(int val) |
| 1535 | { |
| 1536 | int i; |
| 1537 | |
| 1538 | for (i = ARRAY_SIZE(usb_chg_current) - 1; i >= 0; i--) { |
| 1539 | if (usb_chg_current[i] <= val) |
| 1540 | break; |
| 1541 | } |
| 1542 | if (i < 0) |
| 1543 | i = 0; |
| 1544 | |
| 1545 | if (i >= ARRAY_SIZE(usb_chg_current) - 1) |
| 1546 | return ARRAY_SIZE(usb_chg_current) - 1; |
| 1547 | |
| 1548 | /* check what is closer, i or i + 1 */ |
| 1549 | if (abs(usb_chg_current[i] - val) < abs(usb_chg_current[i + 1] - val)) |
| 1550 | return i; |
| 1551 | else |
| 1552 | return i + 1; |
| 1553 | } |
| 1554 | |
| 1555 | static bool smb1351_is_input_current_limited(struct smb1351_charger *chip) |
| 1556 | { |
| 1557 | int rc; |
| 1558 | u8 reg; |
| 1559 | |
| 1560 | rc = smb1351_read_reg(chip, IRQ_H_REG, ®); |
| 1561 | if (rc) { |
| 1562 | pr_err("Failed to read IRQ_H_REG for ICL status: %d\n", rc); |
| 1563 | return false; |
| 1564 | } |
| 1565 | |
| 1566 | return !!(reg & IRQ_IC_LIMIT_STATUS_BIT); |
| 1567 | } |
| 1568 | |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1569 | static bool smb1351_is_usb_present(struct smb1351_charger *chip) |
| 1570 | { |
| 1571 | int rc; |
| 1572 | union power_supply_propval val = {0, }; |
| 1573 | |
| 1574 | if (!chip->usb_psy) |
| 1575 | chip->usb_psy = power_supply_get_by_name("usb"); |
| 1576 | if (!chip->usb_psy) { |
| 1577 | pr_err("USB psy not found\n"); |
| 1578 | return false; |
| 1579 | } |
| 1580 | |
| 1581 | rc = power_supply_get_property(chip->usb_psy, |
| 1582 | POWER_SUPPLY_PROP_ONLINE, &val); |
| 1583 | if (rc < 0) { |
| 1584 | pr_err("Failed to get present property rc=%d\n", rc); |
| 1585 | return false; |
| 1586 | } |
| 1587 | |
| 1588 | if (val.intval) |
| 1589 | return true; |
| 1590 | |
| 1591 | return false; |
| 1592 | } |
| 1593 | |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1594 | static int smb1351_parallel_set_property(struct power_supply *psy, |
| 1595 | enum power_supply_property prop, |
| 1596 | const union power_supply_propval *val) |
| 1597 | { |
| 1598 | int rc = 0, index; |
| 1599 | struct smb1351_charger *chip = power_supply_get_drvdata(psy); |
| 1600 | |
| 1601 | switch (prop) { |
| 1602 | case POWER_SUPPLY_PROP_CHARGING_ENABLED: |
| 1603 | /* |
| 1604 | *CHG EN is controlled by pin in the parallel charging. |
| 1605 | *Use suspend if disable charging by command. |
| 1606 | */ |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1607 | if (!chip->parallel_charger_suspended) |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1608 | rc = smb1351_usb_suspend(chip, USER, !val->intval); |
| 1609 | break; |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1610 | case POWER_SUPPLY_PROP_INPUT_SUSPEND: |
| 1611 | rc = smb1351_parallel_set_chg_suspend(chip, val->intval); |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1612 | break; |
| 1613 | case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX: |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1614 | chip->target_fastchg_current_max_ma = |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1615 | val->intval / 1000; |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1616 | if (!chip->parallel_charger_suspended) |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1617 | rc = smb1351_fastchg_current_set(chip, |
| 1618 | chip->target_fastchg_current_max_ma); |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1619 | break; |
| 1620 | case POWER_SUPPLY_PROP_CURRENT_MAX: |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1621 | index = smb1351_get_closest_usb_setpoint(val->intval / 1000); |
| 1622 | chip->usb_psy_ma = usb_chg_current[index]; |
| 1623 | if (!chip->parallel_charger_suspended) |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1624 | rc = smb1351_set_usb_chg_current(chip, |
| 1625 | chip->usb_psy_ma); |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1626 | break; |
| 1627 | case POWER_SUPPLY_PROP_VOLTAGE_MAX: |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1628 | chip->vfloat_mv = val->intval / 1000; |
| 1629 | if (!chip->parallel_charger_suspended) |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1630 | rc = smb1351_float_voltage_set(chip, val->intval); |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1631 | break; |
| 1632 | default: |
| 1633 | return -EINVAL; |
| 1634 | } |
| 1635 | return rc; |
| 1636 | } |
| 1637 | |
| 1638 | static int smb1351_parallel_is_writeable(struct power_supply *psy, |
| 1639 | enum power_supply_property prop) |
| 1640 | { |
| 1641 | switch (prop) { |
| 1642 | case POWER_SUPPLY_PROP_CHARGING_ENABLED: |
| 1643 | return 1; |
| 1644 | default: |
| 1645 | return 0; |
| 1646 | } |
| 1647 | } |
| 1648 | |
| 1649 | static int smb1351_parallel_get_property(struct power_supply *psy, |
| 1650 | enum power_supply_property prop, |
| 1651 | union power_supply_propval *val) |
| 1652 | { |
| 1653 | struct smb1351_charger *chip = power_supply_get_drvdata(psy); |
| 1654 | |
| 1655 | switch (prop) { |
| 1656 | case POWER_SUPPLY_PROP_CHARGING_ENABLED: |
| 1657 | val->intval = !chip->usb_suspended_status; |
| 1658 | break; |
| 1659 | case POWER_SUPPLY_PROP_CURRENT_MAX: |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1660 | if (!chip->parallel_charger_suspended) |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1661 | val->intval = chip->usb_psy_ma * 1000; |
| 1662 | else |
| 1663 | val->intval = 0; |
| 1664 | break; |
| 1665 | case POWER_SUPPLY_PROP_VOLTAGE_MAX: |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1666 | if (!chip->parallel_charger_suspended) |
| 1667 | val->intval = chip->vfloat_mv; |
| 1668 | else |
| 1669 | val->intval = 0; |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1670 | break; |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1671 | case POWER_SUPPLY_PROP_CHARGE_TYPE: |
| 1672 | val->intval = POWER_SUPPLY_CHARGE_TYPE_NONE; |
| 1673 | /* Check if SMB1351 is present */ |
| 1674 | if (smb1351_is_usb_present(chip)) { |
| 1675 | val->intval = smb1351_get_prop_charge_type(chip); |
| 1676 | if (val->intval == POWER_SUPPLY_CHARGE_TYPE_UNKNOWN) { |
| 1677 | pr_debug("Failed to charge type, charger may be absent\n"); |
| 1678 | return -ENODEV; |
| 1679 | } |
| 1680 | } |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1681 | break; |
| 1682 | case POWER_SUPPLY_PROP_CONSTANT_CHARGE_CURRENT_MAX: |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1683 | if (!chip->parallel_charger_suspended) |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1684 | val->intval = chip->fastchg_current_max_ma * 1000; |
| 1685 | else |
| 1686 | val->intval = 0; |
| 1687 | break; |
| 1688 | case POWER_SUPPLY_PROP_STATUS: |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1689 | if (!chip->parallel_charger_suspended) |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1690 | val->intval = smb1351_get_prop_batt_status(chip); |
| 1691 | else |
| 1692 | val->intval = POWER_SUPPLY_STATUS_DISCHARGING; |
| 1693 | break; |
| 1694 | case POWER_SUPPLY_PROP_INPUT_CURRENT_LIMITED: |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1695 | if (!chip->parallel_charger_suspended) |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1696 | val->intval = |
| 1697 | smb1351_is_input_current_limited(chip) ? 1 : 0; |
| 1698 | else |
| 1699 | val->intval = 0; |
| 1700 | break; |
Abhijeet Dharmapurikar | a8bd6f0 | 2017-01-30 15:43:04 -0800 | [diff] [blame] | 1701 | case POWER_SUPPLY_PROP_PARALLEL_MODE: |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 1702 | val->intval = POWER_SUPPLY_PARALLEL_USBIN_USBIN; |
Abhijeet Dharmapurikar | a8bd6f0 | 2017-01-30 15:43:04 -0800 | [diff] [blame] | 1703 | break; |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1704 | default: |
| 1705 | return -EINVAL; |
| 1706 | } |
| 1707 | return 0; |
| 1708 | } |
| 1709 | |
| 1710 | static void smb1351_chg_set_appropriate_battery_current( |
| 1711 | struct smb1351_charger *chip) |
| 1712 | { |
| 1713 | int rc; |
| 1714 | unsigned int current_max = chip->target_fastchg_current_max_ma; |
| 1715 | |
| 1716 | if (chip->batt_cool) |
| 1717 | current_max = min(current_max, chip->batt_cool_ma); |
| 1718 | if (chip->batt_warm) |
| 1719 | current_max = min(current_max, chip->batt_warm_ma); |
| 1720 | |
| 1721 | pr_debug("setting %dmA", current_max); |
| 1722 | |
| 1723 | rc = smb1351_fastchg_current_set(chip, current_max); |
| 1724 | if (rc) |
| 1725 | pr_err("Couldn't set charging current rc = %d\n", rc); |
| 1726 | } |
| 1727 | |
| 1728 | static void smb1351_chg_set_appropriate_vddmax(struct smb1351_charger *chip) |
| 1729 | { |
| 1730 | int rc; |
| 1731 | unsigned int vddmax = chip->vfloat_mv; |
| 1732 | |
| 1733 | if (chip->batt_cool) |
| 1734 | vddmax = min(vddmax, chip->batt_cool_mv); |
| 1735 | if (chip->batt_warm) |
| 1736 | vddmax = min(vddmax, chip->batt_warm_mv); |
| 1737 | |
| 1738 | pr_debug("setting %dmV\n", vddmax); |
| 1739 | |
| 1740 | rc = smb1351_float_voltage_set(chip, vddmax); |
| 1741 | if (rc) |
| 1742 | pr_err("Couldn't set float voltage rc = %d\n", rc); |
| 1743 | } |
| 1744 | |
| 1745 | static void smb1351_chg_ctrl_in_jeita(struct smb1351_charger *chip) |
| 1746 | { |
| 1747 | union power_supply_propval ret = {0, }; |
| 1748 | int rc; |
| 1749 | |
| 1750 | /* enable the iterm to prevent the reverse boost */ |
| 1751 | if (chip->iterm_disabled) { |
| 1752 | if (chip->batt_cool || chip->batt_warm) { |
| 1753 | rc = smb1351_iterm_set(chip, 100); |
| 1754 | pr_debug("set the iterm due to JEITA\n"); |
| 1755 | } else { |
| 1756 | rc = smb1351_masked_write(chip, CHG_CTRL_REG, |
| 1757 | ITERM_EN_BIT, ITERM_DISABLE); |
| 1758 | pr_debug("disable the iterm when exits warm/cool\n"); |
| 1759 | } |
| 1760 | if (rc) { |
| 1761 | pr_err("Couldn't set iterm rc = %d\n", rc); |
| 1762 | return; |
| 1763 | } |
| 1764 | } |
| 1765 | /* |
| 1766 | * When JEITA back to normal, the charging maybe disabled due to |
| 1767 | * the current termination. So re-enable the charging if the soc |
| 1768 | * is less than 100 in the normal mode. A 200ms delay is required |
| 1769 | * before the disabe and enable operation. |
| 1770 | */ |
| 1771 | if (chip->bms_psy) { |
| 1772 | rc = power_supply_get_property(chip->bms_psy, |
| 1773 | POWER_SUPPLY_PROP_CAPACITY, &ret); |
| 1774 | if (rc) { |
| 1775 | pr_err("Couldn't read the bms capacity rc = %d\n", |
| 1776 | rc); |
| 1777 | return; |
| 1778 | } |
| 1779 | if (!chip->batt_cool && !chip->batt_warm |
| 1780 | && !chip->batt_cold && !chip->batt_hot |
| 1781 | && ret.intval < 100) { |
| 1782 | rc = smb1351_battchg_disable(chip, THERMAL, true); |
| 1783 | if (rc) { |
| 1784 | pr_err("Couldn't disable charging rc = %d\n", |
| 1785 | rc); |
| 1786 | return; |
| 1787 | } |
| 1788 | /* delay for resetting the charging */ |
| 1789 | msleep(200); |
| 1790 | rc = smb1351_battchg_disable(chip, THERMAL, false); |
| 1791 | if (rc) { |
| 1792 | pr_err("Couldn't enable charging rc = %d\n", |
| 1793 | rc); |
| 1794 | return; |
| 1795 | } |
| 1796 | |
| 1797 | chip->batt_full = false; |
| 1798 | pr_debug("re-enable charging, batt_full = %d\n", |
| 1799 | chip->batt_full); |
| 1800 | power_supply_changed(chip->batt_psy); |
| 1801 | } |
| 1802 | } |
| 1803 | } |
| 1804 | |
| 1805 | #define HYSTERESIS_DECIDEGC 20 |
| 1806 | static void smb1351_chg_adc_notification(enum qpnp_tm_state state, void *ctx) |
| 1807 | { |
| 1808 | struct smb1351_charger *chip = ctx; |
| 1809 | struct battery_status *cur = NULL; |
| 1810 | int temp; |
| 1811 | |
| 1812 | if (state >= ADC_TM_STATE_NUM) { |
| 1813 | pr_err("invalid state parameter %d\n", state); |
| 1814 | return; |
| 1815 | } |
| 1816 | |
| 1817 | temp = smb1351_get_prop_batt_temp(chip); |
| 1818 | |
| 1819 | pr_debug("temp = %d state = %s\n", temp, |
| 1820 | state == ADC_TM_WARM_STATE ? "hot" : "cold"); |
| 1821 | |
| 1822 | /* reset the adc status request */ |
| 1823 | chip->adc_param.state_request = ADC_TM_WARM_COOL_THR_ENABLE; |
| 1824 | |
| 1825 | /* temp from low to high */ |
| 1826 | if (state == ADC_TM_WARM_STATE) { |
| 1827 | /* WARM -> HOT */ |
| 1828 | if (temp >= chip->batt_hot_decidegc) { |
| 1829 | cur = &batt_s[BATT_HOT]; |
| 1830 | chip->adc_param.low_temp = |
| 1831 | chip->batt_hot_decidegc - HYSTERESIS_DECIDEGC; |
| 1832 | chip->adc_param.state_request = ADC_TM_COOL_THR_ENABLE; |
| 1833 | /* NORMAL -> WARM */ |
| 1834 | } else if (temp >= chip->batt_warm_decidegc && |
| 1835 | chip->jeita_supported) { |
| 1836 | cur = &batt_s[BATT_WARM]; |
| 1837 | chip->adc_param.low_temp = |
| 1838 | chip->batt_warm_decidegc - HYSTERESIS_DECIDEGC; |
| 1839 | chip->adc_param.high_temp = chip->batt_hot_decidegc; |
| 1840 | /* COOL -> NORMAL */ |
| 1841 | } else if (temp >= chip->batt_cool_decidegc && |
| 1842 | chip->jeita_supported) { |
| 1843 | cur = &batt_s[BATT_NORMAL]; |
| 1844 | chip->adc_param.low_temp = |
| 1845 | chip->batt_cool_decidegc - HYSTERESIS_DECIDEGC; |
| 1846 | chip->adc_param.high_temp = chip->batt_warm_decidegc; |
| 1847 | /* COLD -> COOL */ |
| 1848 | } else if (temp >= chip->batt_cold_decidegc) { |
| 1849 | cur = &batt_s[BATT_COOL]; |
| 1850 | chip->adc_param.low_temp = |
| 1851 | chip->batt_cold_decidegc - HYSTERESIS_DECIDEGC; |
| 1852 | if (chip->jeita_supported) |
| 1853 | chip->adc_param.high_temp = |
| 1854 | chip->batt_cool_decidegc; |
| 1855 | else |
| 1856 | chip->adc_param.high_temp = |
| 1857 | chip->batt_hot_decidegc; |
| 1858 | /* MISSING -> COLD */ |
| 1859 | } else if (temp >= chip->batt_missing_decidegc) { |
| 1860 | cur = &batt_s[BATT_COLD]; |
| 1861 | chip->adc_param.high_temp = chip->batt_cold_decidegc; |
| 1862 | chip->adc_param.low_temp = chip->batt_missing_decidegc |
| 1863 | - HYSTERESIS_DECIDEGC; |
| 1864 | } |
| 1865 | /* temp from high to low */ |
| 1866 | } else { |
| 1867 | /* COLD -> MISSING */ |
| 1868 | if (temp <= chip->batt_missing_decidegc) { |
| 1869 | cur = &batt_s[BATT_MISSING]; |
| 1870 | chip->adc_param.high_temp = chip->batt_missing_decidegc |
| 1871 | + HYSTERESIS_DECIDEGC; |
| 1872 | chip->adc_param.state_request = ADC_TM_WARM_THR_ENABLE; |
| 1873 | /* COOL -> COLD */ |
| 1874 | } else if (temp <= chip->batt_cold_decidegc) { |
| 1875 | cur = &batt_s[BATT_COLD]; |
| 1876 | chip->adc_param.high_temp = |
| 1877 | chip->batt_cold_decidegc + HYSTERESIS_DECIDEGC; |
| 1878 | /* add low_temp to enable batt present check */ |
| 1879 | chip->adc_param.low_temp = chip->batt_missing_decidegc; |
| 1880 | /* NORMAL -> COOL */ |
| 1881 | } else if (temp <= chip->batt_cool_decidegc && |
| 1882 | chip->jeita_supported) { |
| 1883 | cur = &batt_s[BATT_COOL]; |
| 1884 | chip->adc_param.high_temp = |
| 1885 | chip->batt_cool_decidegc + HYSTERESIS_DECIDEGC; |
| 1886 | chip->adc_param.low_temp = chip->batt_cold_decidegc; |
| 1887 | /* WARM -> NORMAL */ |
| 1888 | } else if (temp <= chip->batt_warm_decidegc && |
| 1889 | chip->jeita_supported) { |
| 1890 | cur = &batt_s[BATT_NORMAL]; |
| 1891 | chip->adc_param.high_temp = |
| 1892 | chip->batt_warm_decidegc + HYSTERESIS_DECIDEGC; |
| 1893 | chip->adc_param.low_temp = chip->batt_cool_decidegc; |
| 1894 | /* HOT -> WARM */ |
| 1895 | } else if (temp <= chip->batt_hot_decidegc) { |
| 1896 | cur = &batt_s[BATT_WARM]; |
| 1897 | if (chip->jeita_supported) |
| 1898 | chip->adc_param.low_temp = |
| 1899 | chip->batt_warm_decidegc; |
| 1900 | else |
| 1901 | chip->adc_param.low_temp = |
| 1902 | chip->batt_cold_decidegc; |
| 1903 | chip->adc_param.high_temp = |
| 1904 | chip->batt_hot_decidegc + HYSTERESIS_DECIDEGC; |
| 1905 | } |
| 1906 | } |
| 1907 | |
Abhijeet Dharmapurikar | 87e0c36b | 2016-09-13 10:36:48 -0700 | [diff] [blame] | 1908 | if (!cur) { |
| 1909 | pr_debug("Couldn't choose batt state, adc state=%d and temp=%d\n", |
| 1910 | state, temp); |
| 1911 | return; |
| 1912 | } |
| 1913 | |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 1914 | if (cur->batt_present) |
| 1915 | chip->battery_missing = false; |
| 1916 | else |
| 1917 | chip->battery_missing = true; |
| 1918 | |
| 1919 | if (cur->batt_hot ^ chip->batt_hot || |
| 1920 | cur->batt_cold ^ chip->batt_cold) { |
| 1921 | chip->batt_hot = cur->batt_hot; |
| 1922 | chip->batt_cold = cur->batt_cold; |
| 1923 | /* stop charging explicitly since we use PMIC thermal pin*/ |
| 1924 | if (cur->batt_hot || cur->batt_cold || |
| 1925 | chip->battery_missing) |
| 1926 | smb1351_battchg_disable(chip, THERMAL, 1); |
| 1927 | else |
| 1928 | smb1351_battchg_disable(chip, THERMAL, 0); |
| 1929 | } |
| 1930 | |
| 1931 | if ((chip->batt_warm ^ cur->batt_warm || |
| 1932 | chip->batt_cool ^ cur->batt_cool) |
| 1933 | && chip->jeita_supported) { |
| 1934 | chip->batt_warm = cur->batt_warm; |
| 1935 | chip->batt_cool = cur->batt_cool; |
| 1936 | smb1351_chg_set_appropriate_battery_current(chip); |
| 1937 | smb1351_chg_set_appropriate_vddmax(chip); |
| 1938 | smb1351_chg_ctrl_in_jeita(chip); |
| 1939 | } |
| 1940 | |
| 1941 | pr_debug("hot %d, cold %d, warm %d, cool %d, soft jeita supported %d, missing %d, low = %d deciDegC, high = %d deciDegC\n", |
| 1942 | chip->batt_hot, chip->batt_cold, chip->batt_warm, |
| 1943 | chip->batt_cool, chip->jeita_supported, |
| 1944 | chip->battery_missing, chip->adc_param.low_temp, |
| 1945 | chip->adc_param.high_temp); |
| 1946 | if (qpnp_adc_tm_channel_measure(chip->adc_tm_dev, &chip->adc_param)) |
| 1947 | pr_err("request ADC error\n"); |
| 1948 | } |
| 1949 | |
| 1950 | static int rerun_apsd(struct smb1351_charger *chip) |
| 1951 | { |
| 1952 | int rc; |
| 1953 | |
| 1954 | pr_debug("Reruning APSD\nDisabling APSD\n"); |
| 1955 | |
| 1956 | rc = smb1351_masked_write(chip, CMD_HVDCP_REG, CMD_APSD_RE_RUN_BIT, |
| 1957 | CMD_APSD_RE_RUN_BIT); |
| 1958 | if (rc) |
| 1959 | pr_err("Couldn't re-run APSD algo\n"); |
| 1960 | |
| 1961 | return 0; |
| 1962 | } |
| 1963 | |
| 1964 | static void smb1351_hvdcp_det_work(struct work_struct *work) |
| 1965 | { |
| 1966 | int rc; |
| 1967 | u8 reg; |
| 1968 | union power_supply_propval pval = {0, }; |
| 1969 | struct smb1351_charger *chip = container_of(work, |
| 1970 | struct smb1351_charger, |
| 1971 | hvdcp_det_work.work); |
| 1972 | |
| 1973 | rc = smb1351_read_reg(chip, STATUS_7_REG, ®); |
| 1974 | if (rc) { |
| 1975 | pr_err("Couldn't read STATUS_7_REG rc == %d\n", rc); |
| 1976 | goto end; |
| 1977 | } |
| 1978 | pr_debug("STATUS_7_REG = 0x%02X\n", reg); |
| 1979 | |
| 1980 | if (reg) { |
| 1981 | pr_debug("HVDCP detected; notifying USB PSY\n"); |
| 1982 | pval.intval = POWER_SUPPLY_TYPE_USB_HVDCP; |
| 1983 | power_supply_set_property(chip->usb_psy, |
| 1984 | POWER_SUPPLY_PROP_TYPE, &pval); |
| 1985 | } |
| 1986 | end: |
| 1987 | pm_relax(chip->dev); |
| 1988 | } |
| 1989 | |
| 1990 | #define HVDCP_NOTIFY_MS 2500 |
| 1991 | static int smb1351_apsd_complete_handler(struct smb1351_charger *chip, |
| 1992 | u8 status) |
| 1993 | { |
| 1994 | int rc; |
| 1995 | u8 reg = 0; |
| 1996 | union power_supply_propval prop = {0, }; |
| 1997 | enum power_supply_type type = POWER_SUPPLY_TYPE_UNKNOWN; |
| 1998 | |
| 1999 | /* |
| 2000 | * If apsd is disabled, charger detection is done by |
| 2001 | * USB phy driver. |
| 2002 | */ |
| 2003 | if (chip->disable_apsd || chip->usbin_ov) { |
| 2004 | pr_debug("APSD %s, status = %d\n", |
| 2005 | chip->disable_apsd ? "disabled" : "enabled", !!status); |
| 2006 | pr_debug("USBIN ov, status = %d\n", chip->usbin_ov); |
| 2007 | return 0; |
| 2008 | } |
| 2009 | |
| 2010 | rc = smb1351_read_reg(chip, STATUS_5_REG, ®); |
| 2011 | if (rc) { |
| 2012 | pr_err("Couldn't read STATUS_5 rc = %d\n", rc); |
| 2013 | return rc; |
| 2014 | } |
| 2015 | |
| 2016 | pr_debug("STATUS_5_REG(0x3B)=%x\n", reg); |
| 2017 | |
| 2018 | switch (reg) { |
| 2019 | case STATUS_PORT_ACA_DOCK: |
| 2020 | case STATUS_PORT_ACA_C: |
| 2021 | case STATUS_PORT_ACA_B: |
| 2022 | case STATUS_PORT_ACA_A: |
| 2023 | type = POWER_SUPPLY_TYPE_USB_ACA; |
| 2024 | break; |
| 2025 | case STATUS_PORT_CDP: |
| 2026 | type = POWER_SUPPLY_TYPE_USB_CDP; |
| 2027 | break; |
| 2028 | case STATUS_PORT_DCP: |
| 2029 | type = POWER_SUPPLY_TYPE_USB_DCP; |
| 2030 | break; |
| 2031 | case STATUS_PORT_SDP: |
| 2032 | type = POWER_SUPPLY_TYPE_USB; |
| 2033 | break; |
| 2034 | case STATUS_PORT_OTHER: |
| 2035 | type = POWER_SUPPLY_TYPE_USB_DCP; |
| 2036 | break; |
| 2037 | default: |
| 2038 | type = POWER_SUPPLY_TYPE_USB; |
| 2039 | break; |
| 2040 | } |
| 2041 | |
| 2042 | if (status) { |
| 2043 | chip->chg_present = true; |
| 2044 | pr_debug("APSD complete. USB type detected=%d chg_present=%d\n", |
| 2045 | type, chip->chg_present); |
| 2046 | if (!chip->battery_missing && !chip->apsd_rerun) { |
| 2047 | if (type == POWER_SUPPLY_TYPE_USB) { |
| 2048 | pr_debug("Setting usb psy dp=f dm=f SDP and rerun\n"); |
| 2049 | prop.intval = POWER_SUPPLY_DP_DM_DPF_DMF; |
| 2050 | power_supply_set_property(chip->usb_psy, |
| 2051 | POWER_SUPPLY_PROP_DP_DM, &prop); |
| 2052 | chip->apsd_rerun = true; |
| 2053 | rerun_apsd(chip); |
| 2054 | return 0; |
| 2055 | } |
| 2056 | pr_debug("Set usb psy dp=f dm=f DCP and no rerun\n"); |
| 2057 | prop.intval = POWER_SUPPLY_DP_DM_DPF_DMF; |
| 2058 | power_supply_set_property(chip->usb_psy, |
| 2059 | POWER_SUPPLY_PROP_DP_DM, &prop); |
| 2060 | } |
| 2061 | /* |
| 2062 | * If defined force hvdcp 2p0 property, |
| 2063 | * we force to hvdcp 2p0 in the APSD handler. |
| 2064 | */ |
| 2065 | if (chip->force_hvdcp_2p0) { |
| 2066 | pr_debug("Force set to HVDCP 2.0 mode\n"); |
| 2067 | smb1351_masked_write(chip, VARIOUS_FUNC_3_REG, |
| 2068 | QC_2P1_AUTH_ALGO_BIT, 0); |
| 2069 | smb1351_masked_write(chip, CMD_HVDCP_REG, |
| 2070 | CMD_FORCE_HVDCP_2P0_BIT, |
| 2071 | CMD_FORCE_HVDCP_2P0_BIT); |
| 2072 | type = POWER_SUPPLY_TYPE_USB_HVDCP; |
| 2073 | } else if (type == POWER_SUPPLY_TYPE_USB_DCP) { |
| 2074 | pr_debug("schedule hvdcp detection worker\n"); |
| 2075 | pm_stay_awake(chip->dev); |
| 2076 | schedule_delayed_work(&chip->hvdcp_det_work, |
| 2077 | msecs_to_jiffies(HVDCP_NOTIFY_MS)); |
| 2078 | } |
| 2079 | |
| 2080 | prop.intval = type; |
| 2081 | power_supply_set_property(chip->usb_psy, |
| 2082 | POWER_SUPPLY_PROP_TYPE, &prop); |
| 2083 | /* |
| 2084 | * SMB is now done sampling the D+/D- lines, |
| 2085 | * indicate USB driver |
| 2086 | */ |
| 2087 | pr_debug("updating usb_psy present=%d\n", chip->chg_present); |
| 2088 | prop.intval = chip->chg_present; |
| 2089 | power_supply_set_property(chip->usb_psy, |
| 2090 | POWER_SUPPLY_PROP_PRESENT, |
| 2091 | &prop); |
| 2092 | chip->apsd_rerun = false; |
| 2093 | } else if (!chip->apsd_rerun) { |
| 2094 | /* Handle Charger removal */ |
| 2095 | prop.intval = POWER_SUPPLY_TYPE_UNKNOWN; |
| 2096 | power_supply_set_property(chip->usb_psy, |
| 2097 | POWER_SUPPLY_PROP_TYPE, &prop); |
| 2098 | |
| 2099 | chip->chg_present = false; |
| 2100 | prop.intval = chip->chg_present; |
| 2101 | power_supply_set_property(chip->usb_psy, |
| 2102 | POWER_SUPPLY_PROP_PRESENT, |
| 2103 | &prop); |
| 2104 | |
| 2105 | pr_debug("Set usb psy dm=r df=r\n"); |
| 2106 | prop.intval = POWER_SUPPLY_DP_DM_DPR_DMR; |
| 2107 | power_supply_set_property(chip->usb_psy, |
| 2108 | POWER_SUPPLY_PROP_DP_DM, &prop); |
| 2109 | } |
| 2110 | |
| 2111 | return 0; |
| 2112 | } |
| 2113 | |
| 2114 | /* |
| 2115 | * As source detect interrupt is not triggered on the falling edge, |
| 2116 | * we need to schedule a work for checking source detect status after |
| 2117 | * charger UV interrupt fired. |
| 2118 | */ |
| 2119 | #define FIRST_CHECK_DELAY 100 |
| 2120 | #define SECOND_CHECK_DELAY 1000 |
| 2121 | static void smb1351_chg_remove_work(struct work_struct *work) |
| 2122 | { |
| 2123 | int rc; |
| 2124 | u8 reg; |
| 2125 | struct smb1351_charger *chip = container_of(work, |
| 2126 | struct smb1351_charger, chg_remove_work.work); |
| 2127 | |
| 2128 | rc = smb1351_read_reg(chip, IRQ_G_REG, ®); |
| 2129 | if (rc) { |
| 2130 | pr_err("Couldn't read IRQ_G_REG rc = %d\n", rc); |
| 2131 | goto end; |
| 2132 | } |
| 2133 | |
| 2134 | if (!(reg & IRQ_SOURCE_DET_BIT)) { |
| 2135 | pr_debug("chg removed\n"); |
| 2136 | smb1351_apsd_complete_handler(chip, 0); |
| 2137 | } else if (!chip->chg_remove_work_scheduled) { |
| 2138 | chip->chg_remove_work_scheduled = true; |
| 2139 | goto reschedule; |
| 2140 | } else { |
| 2141 | pr_debug("charger is present\n"); |
| 2142 | } |
| 2143 | end: |
| 2144 | chip->chg_remove_work_scheduled = false; |
| 2145 | pm_relax(chip->dev); |
| 2146 | return; |
| 2147 | |
| 2148 | reschedule: |
| 2149 | pr_debug("reschedule after 1s\n"); |
| 2150 | schedule_delayed_work(&chip->chg_remove_work, |
| 2151 | msecs_to_jiffies(SECOND_CHECK_DELAY)); |
| 2152 | } |
| 2153 | |
| 2154 | static int smb1351_usbin_uv_handler(struct smb1351_charger *chip, u8 status) |
| 2155 | { |
| 2156 | union power_supply_propval pval = {0, }; |
| 2157 | |
| 2158 | /* use this to detect USB insertion only if !apsd */ |
| 2159 | if (chip->disable_apsd) { |
| 2160 | /* |
| 2161 | * If APSD is disabled, src det interrupt won't trigger. |
| 2162 | * Hence use usbin_uv for removal and insertion notification |
| 2163 | */ |
| 2164 | if (status == 0) { |
| 2165 | chip->chg_present = true; |
| 2166 | pr_debug("updating usb_psy present=%d\n", |
| 2167 | chip->chg_present); |
| 2168 | pval.intval = POWER_SUPPLY_TYPE_USB; |
| 2169 | power_supply_set_property(chip->usb_psy, |
| 2170 | POWER_SUPPLY_PROP_TYPE, &pval); |
| 2171 | |
| 2172 | pval.intval = chip->chg_present; |
| 2173 | power_supply_set_property(chip->usb_psy, |
| 2174 | POWER_SUPPLY_PROP_PRESENT, |
| 2175 | &pval); |
| 2176 | } else { |
| 2177 | chip->chg_present = false; |
| 2178 | |
| 2179 | pval.intval = POWER_SUPPLY_TYPE_UNKNOWN; |
| 2180 | power_supply_set_property(chip->usb_psy, |
| 2181 | POWER_SUPPLY_PROP_TYPE, &pval); |
| 2182 | |
| 2183 | pr_debug("updating usb_psy present=%d\n", |
| 2184 | chip->chg_present); |
| 2185 | pval.intval = chip->chg_present; |
| 2186 | power_supply_set_property(chip->usb_psy, |
| 2187 | POWER_SUPPLY_PROP_PRESENT, |
| 2188 | &pval); |
| 2189 | } |
| 2190 | return 0; |
| 2191 | } |
| 2192 | |
| 2193 | if (status) { |
| 2194 | cancel_delayed_work_sync(&chip->hvdcp_det_work); |
| 2195 | pm_relax(chip->dev); |
| 2196 | pr_debug("schedule charger remove worker\n"); |
| 2197 | schedule_delayed_work(&chip->chg_remove_work, |
| 2198 | msecs_to_jiffies(FIRST_CHECK_DELAY)); |
| 2199 | pm_stay_awake(chip->dev); |
| 2200 | } |
| 2201 | |
| 2202 | pr_debug("chip->chg_present = %d\n", chip->chg_present); |
| 2203 | |
| 2204 | return 0; |
| 2205 | } |
| 2206 | |
| 2207 | static int smb1351_usbin_ov_handler(struct smb1351_charger *chip, u8 status) |
| 2208 | { |
| 2209 | int rc; |
| 2210 | u8 reg; |
| 2211 | union power_supply_propval pval = {0, }; |
| 2212 | |
| 2213 | rc = smb1351_read_reg(chip, IRQ_E_REG, ®); |
| 2214 | if (rc) |
| 2215 | pr_err("Couldn't read IRQ_E rc = %d\n", rc); |
| 2216 | |
| 2217 | if (status != 0) { |
| 2218 | chip->chg_present = false; |
| 2219 | chip->usbin_ov = true; |
| 2220 | |
| 2221 | pval.intval = POWER_SUPPLY_TYPE_UNKNOWN; |
| 2222 | power_supply_set_property(chip->usb_psy, |
| 2223 | POWER_SUPPLY_PROP_TYPE, &pval); |
| 2224 | |
| 2225 | pval.intval = chip->chg_present; |
| 2226 | power_supply_set_property(chip->usb_psy, |
| 2227 | POWER_SUPPLY_PROP_PRESENT, |
| 2228 | &pval); |
| 2229 | } else { |
| 2230 | chip->usbin_ov = false; |
| 2231 | if (reg & IRQ_USBIN_UV_BIT) |
| 2232 | pr_debug("Charger unplugged from OV\n"); |
| 2233 | else |
| 2234 | smb1351_apsd_complete_handler(chip, 1); |
| 2235 | } |
| 2236 | |
| 2237 | if (chip->usb_psy) { |
| 2238 | pval.intval = status ? POWER_SUPPLY_HEALTH_OVERVOLTAGE |
| 2239 | : POWER_SUPPLY_HEALTH_GOOD; |
| 2240 | power_supply_set_property(chip->usb_psy, |
| 2241 | POWER_SUPPLY_PROP_HEALTH, &pval); |
| 2242 | pr_debug("chip ov status is %d\n", pval.intval); |
| 2243 | } |
| 2244 | pr_debug("chip->chg_present = %d\n", chip->chg_present); |
| 2245 | |
| 2246 | return 0; |
| 2247 | } |
| 2248 | |
| 2249 | static int smb1351_fast_chg_handler(struct smb1351_charger *chip, u8 status) |
| 2250 | { |
| 2251 | pr_debug("enter\n"); |
| 2252 | return 0; |
| 2253 | } |
| 2254 | |
| 2255 | static int smb1351_chg_term_handler(struct smb1351_charger *chip, u8 status) |
| 2256 | { |
| 2257 | pr_debug("enter\n"); |
| 2258 | if (!chip->bms_controlled_charging) |
| 2259 | chip->batt_full = !!status; |
| 2260 | return 0; |
| 2261 | } |
| 2262 | |
| 2263 | static int smb1351_safety_timeout_handler(struct smb1351_charger *chip, |
| 2264 | u8 status) |
| 2265 | { |
| 2266 | pr_debug("safety_timeout triggered\n"); |
| 2267 | return 0; |
| 2268 | } |
| 2269 | |
| 2270 | static int smb1351_aicl_done_handler(struct smb1351_charger *chip, u8 status) |
| 2271 | { |
| 2272 | pr_debug("aicl_done triggered\n"); |
| 2273 | return 0; |
| 2274 | } |
| 2275 | |
| 2276 | static int smb1351_hot_hard_handler(struct smb1351_charger *chip, u8 status) |
| 2277 | { |
| 2278 | pr_debug("status = 0x%02x\n", status); |
| 2279 | chip->batt_hot = !!status; |
| 2280 | return 0; |
| 2281 | } |
| 2282 | static int smb1351_cold_hard_handler(struct smb1351_charger *chip, u8 status) |
| 2283 | { |
| 2284 | pr_debug("status = 0x%02x\n", status); |
| 2285 | chip->batt_cold = !!status; |
| 2286 | return 0; |
| 2287 | } |
| 2288 | static int smb1351_hot_soft_handler(struct smb1351_charger *chip, u8 status) |
| 2289 | { |
| 2290 | pr_debug("status = 0x%02x\n", status); |
| 2291 | chip->batt_warm = !!status; |
| 2292 | return 0; |
| 2293 | } |
| 2294 | static int smb1351_cold_soft_handler(struct smb1351_charger *chip, u8 status) |
| 2295 | { |
| 2296 | pr_debug("status = 0x%02x\n", status); |
| 2297 | chip->batt_cool = !!status; |
| 2298 | return 0; |
| 2299 | } |
| 2300 | |
| 2301 | static int smb1351_battery_missing_handler(struct smb1351_charger *chip, |
| 2302 | u8 status) |
| 2303 | { |
| 2304 | if (status) |
| 2305 | chip->battery_missing = true; |
| 2306 | else |
| 2307 | chip->battery_missing = false; |
| 2308 | |
| 2309 | return 0; |
| 2310 | } |
| 2311 | |
| 2312 | static struct irq_handler_info handlers[] = { |
| 2313 | [0] = { |
| 2314 | .stat_reg = IRQ_A_REG, |
| 2315 | .val = 0, |
| 2316 | .prev_val = 0, |
| 2317 | .irq_info = { |
| 2318 | { .name = "cold_soft", |
| 2319 | .smb_irq = smb1351_cold_soft_handler, |
| 2320 | }, |
| 2321 | { .name = "hot_soft", |
| 2322 | .smb_irq = smb1351_hot_soft_handler, |
| 2323 | }, |
| 2324 | { .name = "cold_hard", |
| 2325 | .smb_irq = smb1351_cold_hard_handler, |
| 2326 | }, |
| 2327 | { .name = "hot_hard", |
| 2328 | .smb_irq = smb1351_hot_hard_handler, |
| 2329 | }, |
| 2330 | }, |
| 2331 | }, |
| 2332 | [1] = { |
| 2333 | .stat_reg = IRQ_B_REG, |
| 2334 | .val = 0, |
| 2335 | .prev_val = 0, |
| 2336 | .irq_info = { |
| 2337 | { .name = "internal_temp_limit", |
| 2338 | }, |
| 2339 | { .name = "vbatt_low", |
| 2340 | }, |
| 2341 | { .name = "battery_missing", |
| 2342 | .smb_irq = smb1351_battery_missing_handler, |
| 2343 | }, |
| 2344 | { .name = "batt_therm_removed", |
| 2345 | }, |
| 2346 | }, |
| 2347 | }, |
| 2348 | [2] = { |
| 2349 | .stat_reg = IRQ_C_REG, |
| 2350 | .val = 0, |
| 2351 | .prev_val = 0, |
| 2352 | .irq_info = { |
| 2353 | { .name = "chg_term", |
| 2354 | .smb_irq = smb1351_chg_term_handler, |
| 2355 | }, |
| 2356 | { .name = "taper", |
| 2357 | }, |
| 2358 | { .name = "recharge", |
| 2359 | }, |
| 2360 | { .name = "fast_chg", |
| 2361 | .smb_irq = smb1351_fast_chg_handler, |
| 2362 | }, |
| 2363 | }, |
| 2364 | }, |
| 2365 | [3] = { |
| 2366 | .stat_reg = IRQ_D_REG, |
| 2367 | .val = 0, |
| 2368 | .prev_val = 0, |
| 2369 | .irq_info = { |
| 2370 | { .name = "prechg_timeout", |
| 2371 | }, |
| 2372 | { .name = "safety_timeout", |
| 2373 | .smb_irq = smb1351_safety_timeout_handler, |
| 2374 | }, |
| 2375 | { .name = "chg_error", |
| 2376 | }, |
| 2377 | { .name = "batt_ov", |
| 2378 | }, |
| 2379 | }, |
| 2380 | }, |
| 2381 | [4] = { |
| 2382 | .stat_reg = IRQ_E_REG, |
| 2383 | .val = 0, |
| 2384 | .prev_val = 0, |
| 2385 | .irq_info = { |
| 2386 | { .name = "power_ok", |
| 2387 | }, |
| 2388 | { .name = "afvc", |
| 2389 | }, |
| 2390 | { .name = "usbin_uv", |
| 2391 | .smb_irq = smb1351_usbin_uv_handler, |
| 2392 | }, |
| 2393 | { .name = "usbin_ov", |
| 2394 | .smb_irq = smb1351_usbin_ov_handler, |
| 2395 | }, |
| 2396 | }, |
| 2397 | }, |
| 2398 | [5] = { |
| 2399 | .stat_reg = IRQ_F_REG, |
| 2400 | .val = 0, |
| 2401 | .prev_val = 0, |
| 2402 | .irq_info = { |
| 2403 | { .name = "otg_oc_retry", |
| 2404 | }, |
| 2405 | { .name = "rid", |
| 2406 | }, |
| 2407 | { .name = "otg_fail", |
| 2408 | }, |
| 2409 | { .name = "otg_oc", |
| 2410 | }, |
| 2411 | }, |
| 2412 | }, |
| 2413 | [6] = { |
| 2414 | .stat_reg = IRQ_G_REG, |
| 2415 | .val = 0, |
| 2416 | .prev_val = 0, |
| 2417 | .irq_info = { |
| 2418 | { .name = "chg_inhibit", |
| 2419 | }, |
| 2420 | { .name = "aicl_fail", |
| 2421 | }, |
| 2422 | { .name = "aicl_done", |
| 2423 | .smb_irq = smb1351_aicl_done_handler, |
| 2424 | }, |
| 2425 | { .name = "apsd_complete", |
| 2426 | .smb_irq = smb1351_apsd_complete_handler, |
| 2427 | }, |
| 2428 | }, |
| 2429 | }, |
| 2430 | [7] = { |
| 2431 | .stat_reg = IRQ_H_REG, |
| 2432 | .val = 0, |
| 2433 | .prev_val = 0, |
| 2434 | .irq_info = { |
| 2435 | { .name = "wdog_timeout", |
| 2436 | }, |
| 2437 | { .name = "hvdcp_auth_done", |
| 2438 | }, |
| 2439 | }, |
| 2440 | }, |
| 2441 | }; |
| 2442 | |
| 2443 | #define IRQ_LATCHED_MASK 0x02 |
| 2444 | #define IRQ_STATUS_MASK 0x01 |
| 2445 | #define BITS_PER_IRQ 2 |
| 2446 | static irqreturn_t smb1351_chg_stat_handler(int irq, void *dev_id) |
| 2447 | { |
| 2448 | struct smb1351_charger *chip = dev_id; |
| 2449 | int i, j; |
| 2450 | u8 triggered; |
| 2451 | u8 changed; |
| 2452 | u8 rt_stat, prev_rt_stat; |
| 2453 | int rc; |
| 2454 | int handler_count = 0; |
| 2455 | |
| 2456 | mutex_lock(&chip->irq_complete); |
| 2457 | |
| 2458 | chip->irq_waiting = true; |
| 2459 | if (!chip->resume_completed) { |
| 2460 | pr_debug("IRQ triggered before device-resume\n"); |
| 2461 | disable_irq_nosync(irq); |
| 2462 | mutex_unlock(&chip->irq_complete); |
| 2463 | return IRQ_HANDLED; |
| 2464 | } |
| 2465 | chip->irq_waiting = false; |
| 2466 | |
| 2467 | for (i = 0; i < ARRAY_SIZE(handlers); i++) { |
| 2468 | rc = smb1351_read_reg(chip, handlers[i].stat_reg, |
| 2469 | &handlers[i].val); |
| 2470 | if (rc) { |
| 2471 | pr_err("Couldn't read %d rc = %d\n", |
| 2472 | handlers[i].stat_reg, rc); |
| 2473 | continue; |
| 2474 | } |
| 2475 | |
| 2476 | for (j = 0; j < ARRAY_SIZE(handlers[i].irq_info); j++) { |
| 2477 | triggered = handlers[i].val |
| 2478 | & (IRQ_LATCHED_MASK << (j * BITS_PER_IRQ)); |
| 2479 | rt_stat = handlers[i].val |
| 2480 | & (IRQ_STATUS_MASK << (j * BITS_PER_IRQ)); |
| 2481 | prev_rt_stat = handlers[i].prev_val |
| 2482 | & (IRQ_STATUS_MASK << (j * BITS_PER_IRQ)); |
| 2483 | changed = prev_rt_stat ^ rt_stat; |
| 2484 | |
| 2485 | if (triggered || changed) |
| 2486 | rt_stat ? handlers[i].irq_info[j].high++ : |
| 2487 | handlers[i].irq_info[j].low++; |
| 2488 | |
| 2489 | if ((triggered || changed) |
| 2490 | && handlers[i].irq_info[j].smb_irq != NULL) { |
| 2491 | handler_count++; |
| 2492 | rc = handlers[i].irq_info[j].smb_irq(chip, |
| 2493 | rt_stat); |
| 2494 | if (rc) |
| 2495 | pr_err("Couldn't handle %d irq for reg 0x%02x rc = %d\n", |
| 2496 | j, handlers[i].stat_reg, rc); |
| 2497 | } |
| 2498 | } |
| 2499 | handlers[i].prev_val = handlers[i].val; |
| 2500 | } |
| 2501 | |
| 2502 | pr_debug("handler count = %d\n", handler_count); |
| 2503 | if (handler_count) { |
| 2504 | pr_debug("batt psy changed\n"); |
| 2505 | power_supply_changed(chip->batt_psy); |
| 2506 | } |
| 2507 | |
| 2508 | mutex_unlock(&chip->irq_complete); |
| 2509 | |
| 2510 | return IRQ_HANDLED; |
| 2511 | } |
| 2512 | |
| 2513 | static void smb1351_external_power_changed(struct power_supply *psy) |
| 2514 | { |
| 2515 | struct smb1351_charger *chip = power_supply_get_drvdata(psy); |
| 2516 | union power_supply_propval prop = {0,}; |
| 2517 | int rc, current_limit = 0, online = 0; |
| 2518 | |
| 2519 | if (chip->bms_psy_name) |
| 2520 | chip->bms_psy = |
| 2521 | power_supply_get_by_name((char *)chip->bms_psy_name); |
| 2522 | |
| 2523 | rc = power_supply_get_property(chip->usb_psy, |
| 2524 | POWER_SUPPLY_PROP_ONLINE, &prop); |
| 2525 | if (rc) |
| 2526 | pr_err("Couldn't read USB online property, rc=%d\n", rc); |
| 2527 | else |
| 2528 | online = prop.intval; |
| 2529 | |
| 2530 | rc = power_supply_get_property(chip->usb_psy, |
| 2531 | POWER_SUPPLY_PROP_CURRENT_MAX, &prop); |
| 2532 | if (rc) |
| 2533 | pr_err("Couldn't read USB current_max property, rc=%d\n", rc); |
| 2534 | else |
| 2535 | current_limit = prop.intval / 1000; |
| 2536 | |
| 2537 | pr_debug("online = %d, current_limit = %d\n", online, current_limit); |
| 2538 | |
| 2539 | smb1351_enable_volatile_writes(chip); |
| 2540 | smb1351_set_usb_chg_current(chip, current_limit); |
| 2541 | |
| 2542 | pr_debug("updating batt psy\n"); |
| 2543 | } |
| 2544 | |
| 2545 | #define LAST_CNFG_REG 0x16 |
| 2546 | static int show_cnfg_regs(struct seq_file *m, void *data) |
| 2547 | { |
| 2548 | struct smb1351_charger *chip = m->private; |
| 2549 | int rc; |
| 2550 | u8 reg; |
| 2551 | u8 addr; |
| 2552 | |
| 2553 | for (addr = 0; addr <= LAST_CNFG_REG; addr++) { |
| 2554 | rc = smb1351_read_reg(chip, addr, ®); |
| 2555 | if (!rc) |
| 2556 | seq_printf(m, "0x%02x = 0x%02x\n", addr, reg); |
| 2557 | } |
| 2558 | |
| 2559 | return 0; |
| 2560 | } |
| 2561 | |
| 2562 | static int cnfg_debugfs_open(struct inode *inode, struct file *file) |
| 2563 | { |
| 2564 | struct smb1351_charger *chip = inode->i_private; |
| 2565 | |
| 2566 | return single_open(file, show_cnfg_regs, chip); |
| 2567 | } |
| 2568 | |
| 2569 | static const struct file_operations cnfg_debugfs_ops = { |
| 2570 | .owner = THIS_MODULE, |
| 2571 | .open = cnfg_debugfs_open, |
| 2572 | .read = seq_read, |
| 2573 | .llseek = seq_lseek, |
| 2574 | .release = single_release, |
| 2575 | }; |
| 2576 | |
| 2577 | #define FIRST_CMD_REG 0x30 |
| 2578 | #define LAST_CMD_REG 0x34 |
| 2579 | static int show_cmd_regs(struct seq_file *m, void *data) |
| 2580 | { |
| 2581 | struct smb1351_charger *chip = m->private; |
| 2582 | int rc; |
| 2583 | u8 reg; |
| 2584 | u8 addr; |
| 2585 | |
| 2586 | for (addr = FIRST_CMD_REG; addr <= LAST_CMD_REG; addr++) { |
| 2587 | rc = smb1351_read_reg(chip, addr, ®); |
| 2588 | if (!rc) |
| 2589 | seq_printf(m, "0x%02x = 0x%02x\n", addr, reg); |
| 2590 | } |
| 2591 | |
| 2592 | return 0; |
| 2593 | } |
| 2594 | |
| 2595 | static int cmd_debugfs_open(struct inode *inode, struct file *file) |
| 2596 | { |
| 2597 | struct smb1351_charger *chip = inode->i_private; |
| 2598 | |
| 2599 | return single_open(file, show_cmd_regs, chip); |
| 2600 | } |
| 2601 | |
| 2602 | static const struct file_operations cmd_debugfs_ops = { |
| 2603 | .owner = THIS_MODULE, |
| 2604 | .open = cmd_debugfs_open, |
| 2605 | .read = seq_read, |
| 2606 | .llseek = seq_lseek, |
| 2607 | .release = single_release, |
| 2608 | }; |
| 2609 | |
| 2610 | #define FIRST_STATUS_REG 0x36 |
| 2611 | #define LAST_STATUS_REG 0x3F |
| 2612 | static int show_status_regs(struct seq_file *m, void *data) |
| 2613 | { |
| 2614 | struct smb1351_charger *chip = m->private; |
| 2615 | int rc; |
| 2616 | u8 reg; |
| 2617 | u8 addr; |
| 2618 | |
| 2619 | for (addr = FIRST_STATUS_REG; addr <= LAST_STATUS_REG; addr++) { |
| 2620 | rc = smb1351_read_reg(chip, addr, ®); |
| 2621 | if (!rc) |
| 2622 | seq_printf(m, "0x%02x = 0x%02x\n", addr, reg); |
| 2623 | } |
| 2624 | |
| 2625 | return 0; |
| 2626 | } |
| 2627 | |
| 2628 | static int status_debugfs_open(struct inode *inode, struct file *file) |
| 2629 | { |
| 2630 | struct smb1351_charger *chip = inode->i_private; |
| 2631 | |
| 2632 | return single_open(file, show_status_regs, chip); |
| 2633 | } |
| 2634 | |
| 2635 | static const struct file_operations status_debugfs_ops = { |
| 2636 | .owner = THIS_MODULE, |
| 2637 | .open = status_debugfs_open, |
| 2638 | .read = seq_read, |
| 2639 | .llseek = seq_lseek, |
| 2640 | .release = single_release, |
| 2641 | }; |
| 2642 | |
| 2643 | static int show_irq_count(struct seq_file *m, void *data) |
| 2644 | { |
| 2645 | int i, j, total = 0; |
| 2646 | |
| 2647 | for (i = 0; i < ARRAY_SIZE(handlers); i++) |
| 2648 | for (j = 0; j < 4; j++) { |
| 2649 | seq_printf(m, "%s=%d\t(high=%d low=%d)\n", |
| 2650 | handlers[i].irq_info[j].name, |
| 2651 | handlers[i].irq_info[j].high |
| 2652 | + handlers[i].irq_info[j].low, |
| 2653 | handlers[i].irq_info[j].high, |
| 2654 | handlers[i].irq_info[j].low); |
| 2655 | total += (handlers[i].irq_info[j].high |
| 2656 | + handlers[i].irq_info[j].low); |
| 2657 | } |
| 2658 | |
| 2659 | seq_printf(m, "\n\tTotal = %d\n", total); |
| 2660 | |
| 2661 | return 0; |
| 2662 | } |
| 2663 | |
| 2664 | static int irq_count_debugfs_open(struct inode *inode, struct file *file) |
| 2665 | { |
| 2666 | struct smb1351_charger *chip = inode->i_private; |
| 2667 | |
| 2668 | return single_open(file, show_irq_count, chip); |
| 2669 | } |
| 2670 | |
| 2671 | static const struct file_operations irq_count_debugfs_ops = { |
| 2672 | .owner = THIS_MODULE, |
| 2673 | .open = irq_count_debugfs_open, |
| 2674 | .read = seq_read, |
| 2675 | .llseek = seq_lseek, |
| 2676 | .release = single_release, |
| 2677 | }; |
| 2678 | |
| 2679 | static int get_reg(void *data, u64 *val) |
| 2680 | { |
| 2681 | struct smb1351_charger *chip = data; |
| 2682 | int rc; |
| 2683 | u8 temp; |
| 2684 | |
| 2685 | rc = smb1351_read_reg(chip, chip->peek_poke_address, &temp); |
| 2686 | if (rc) { |
| 2687 | pr_err("Couldn't read reg %x rc = %d\n", |
| 2688 | chip->peek_poke_address, rc); |
| 2689 | return -EAGAIN; |
| 2690 | } |
| 2691 | *val = temp; |
| 2692 | return 0; |
| 2693 | } |
| 2694 | |
| 2695 | static int set_reg(void *data, u64 val) |
| 2696 | { |
| 2697 | struct smb1351_charger *chip = data; |
| 2698 | int rc; |
| 2699 | u8 temp; |
| 2700 | |
| 2701 | temp = (u8) val; |
| 2702 | rc = smb1351_write_reg(chip, chip->peek_poke_address, temp); |
| 2703 | if (rc) { |
| 2704 | pr_err("Couldn't write 0x%02x to 0x%02x rc= %d\n", |
| 2705 | temp, chip->peek_poke_address, rc); |
| 2706 | return -EAGAIN; |
| 2707 | } |
| 2708 | return 0; |
| 2709 | } |
| 2710 | DEFINE_SIMPLE_ATTRIBUTE(poke_poke_debug_ops, get_reg, set_reg, "0x%02llx\n"); |
| 2711 | |
| 2712 | static int force_irq_set(void *data, u64 val) |
| 2713 | { |
| 2714 | struct smb1351_charger *chip = data; |
| 2715 | |
| 2716 | smb1351_chg_stat_handler(chip->client->irq, data); |
| 2717 | return 0; |
| 2718 | } |
| 2719 | DEFINE_SIMPLE_ATTRIBUTE(force_irq_ops, NULL, force_irq_set, "0x%02llx\n"); |
| 2720 | |
| 2721 | #ifdef DEBUG |
| 2722 | static void dump_regs(struct smb1351_charger *chip) |
| 2723 | { |
| 2724 | int rc; |
| 2725 | u8 reg; |
| 2726 | u8 addr; |
| 2727 | |
| 2728 | for (addr = 0; addr <= LAST_CNFG_REG; addr++) { |
| 2729 | rc = smb1351_read_reg(chip, addr, ®); |
| 2730 | if (rc) |
| 2731 | pr_err("Couldn't read 0x%02x rc = %d\n", addr, rc); |
| 2732 | else |
| 2733 | pr_debug("0x%02x = 0x%02x\n", addr, reg); |
| 2734 | } |
| 2735 | |
| 2736 | for (addr = FIRST_STATUS_REG; addr <= LAST_STATUS_REG; addr++) { |
| 2737 | rc = smb1351_read_reg(chip, addr, ®); |
| 2738 | if (rc) |
| 2739 | pr_err("Couldn't read 0x%02x rc = %d\n", addr, rc); |
| 2740 | else |
| 2741 | pr_debug("0x%02x = 0x%02x\n", addr, reg); |
| 2742 | } |
| 2743 | |
| 2744 | for (addr = FIRST_CMD_REG; addr <= LAST_CMD_REG; addr++) { |
| 2745 | rc = smb1351_read_reg(chip, addr, ®); |
| 2746 | if (rc) |
| 2747 | pr_err("Couldn't read 0x%02x rc = %d\n", addr, rc); |
| 2748 | else |
| 2749 | pr_debug("0x%02x = 0x%02x\n", addr, reg); |
| 2750 | } |
| 2751 | } |
| 2752 | #else |
| 2753 | static void dump_regs(struct smb1351_charger *chip) |
| 2754 | { |
| 2755 | } |
| 2756 | #endif |
| 2757 | |
| 2758 | static int smb1351_parse_dt(struct smb1351_charger *chip) |
| 2759 | { |
| 2760 | int rc; |
| 2761 | struct device_node *node = chip->dev->of_node; |
| 2762 | |
| 2763 | if (!node) { |
| 2764 | pr_err("device tree info. missing\n"); |
| 2765 | return -EINVAL; |
| 2766 | } |
| 2767 | |
| 2768 | chip->usb_suspended_status = of_property_read_bool(node, |
| 2769 | "qcom,charging-disabled"); |
| 2770 | |
| 2771 | chip->chg_autonomous_mode = of_property_read_bool(node, |
| 2772 | "qcom,chg-autonomous-mode"); |
| 2773 | |
| 2774 | chip->disable_apsd = of_property_read_bool(node, "qcom,disable-apsd"); |
| 2775 | |
| 2776 | chip->using_pmic_therm = of_property_read_bool(node, |
| 2777 | "qcom,using-pmic-therm"); |
| 2778 | chip->bms_controlled_charging = of_property_read_bool(node, |
| 2779 | "qcom,bms-controlled-charging"); |
| 2780 | chip->force_hvdcp_2p0 = of_property_read_bool(node, |
| 2781 | "qcom,force-hvdcp-2p0"); |
| 2782 | |
| 2783 | rc = of_property_read_string(node, "qcom,bms-psy-name", |
| 2784 | &chip->bms_psy_name); |
| 2785 | if (rc) |
| 2786 | chip->bms_psy_name = NULL; |
| 2787 | |
| 2788 | rc = of_property_read_u32(node, "qcom,fastchg-current-max-ma", |
| 2789 | &chip->target_fastchg_current_max_ma); |
| 2790 | if (rc) |
| 2791 | chip->target_fastchg_current_max_ma = SMB1351_CHG_FAST_MAX_MA; |
| 2792 | |
| 2793 | chip->iterm_disabled = of_property_read_bool(node, |
| 2794 | "qcom,iterm-disabled"); |
| 2795 | |
| 2796 | rc = of_property_read_u32(node, "qcom,iterm-ma", &chip->iterm_ma); |
| 2797 | if (rc) |
| 2798 | chip->iterm_ma = -EINVAL; |
| 2799 | |
| 2800 | rc = of_property_read_u32(node, "qcom,float-voltage-mv", |
| 2801 | &chip->vfloat_mv); |
| 2802 | if (rc) |
| 2803 | chip->vfloat_mv = -EINVAL; |
| 2804 | |
| 2805 | rc = of_property_read_u32(node, "qcom,recharge-mv", |
| 2806 | &chip->recharge_mv); |
| 2807 | if (rc) |
| 2808 | chip->recharge_mv = -EINVAL; |
| 2809 | |
| 2810 | chip->recharge_disabled = of_property_read_bool(node, |
| 2811 | "qcom,recharge-disabled"); |
| 2812 | |
| 2813 | /* thermal and jeita support */ |
| 2814 | rc = of_property_read_u32(node, "qcom,batt-cold-decidegc", |
| 2815 | &chip->batt_cold_decidegc); |
| 2816 | if (rc < 0) |
| 2817 | chip->batt_cold_decidegc = -EINVAL; |
| 2818 | |
| 2819 | rc = of_property_read_u32(node, "qcom,batt-hot-decidegc", |
| 2820 | &chip->batt_hot_decidegc); |
| 2821 | if (rc < 0) |
| 2822 | chip->batt_hot_decidegc = -EINVAL; |
| 2823 | |
| 2824 | rc = of_property_read_u32(node, "qcom,batt-warm-decidegc", |
| 2825 | &chip->batt_warm_decidegc); |
| 2826 | |
| 2827 | rc |= of_property_read_u32(node, "qcom,batt-cool-decidegc", |
| 2828 | &chip->batt_cool_decidegc); |
| 2829 | |
| 2830 | if (!rc) { |
| 2831 | rc = of_property_read_u32(node, "qcom,batt-cool-mv", |
| 2832 | &chip->batt_cool_mv); |
| 2833 | |
| 2834 | rc |= of_property_read_u32(node, "qcom,batt-warm-mv", |
| 2835 | &chip->batt_warm_mv); |
| 2836 | |
| 2837 | rc |= of_property_read_u32(node, "qcom,batt-cool-ma", |
| 2838 | &chip->batt_cool_ma); |
| 2839 | |
| 2840 | rc |= of_property_read_u32(node, "qcom,batt-warm-ma", |
| 2841 | &chip->batt_warm_ma); |
| 2842 | if (rc) |
| 2843 | chip->jeita_supported = false; |
| 2844 | else |
| 2845 | chip->jeita_supported = true; |
| 2846 | } |
| 2847 | |
| 2848 | pr_debug("jeita_supported = %d\n", chip->jeita_supported); |
| 2849 | |
| 2850 | rc = of_property_read_u32(node, "qcom,batt-missing-decidegc", |
| 2851 | &chip->batt_missing_decidegc); |
| 2852 | |
| 2853 | chip->pinctrl_state_name = of_get_property(node, "pinctrl-names", NULL); |
| 2854 | |
| 2855 | return 0; |
| 2856 | } |
| 2857 | |
| 2858 | static int smb1351_determine_initial_state(struct smb1351_charger *chip) |
| 2859 | { |
| 2860 | int rc; |
| 2861 | u8 reg = 0; |
| 2862 | |
| 2863 | /* |
| 2864 | * It is okay to read the interrupt status here since |
| 2865 | * interrupts aren't requested. Reading interrupt status |
| 2866 | * clears the interrupt so be careful to read interrupt |
| 2867 | * status only in interrupt handling code |
| 2868 | */ |
| 2869 | |
| 2870 | rc = smb1351_read_reg(chip, IRQ_B_REG, ®); |
| 2871 | if (rc) { |
| 2872 | pr_err("Couldn't read IRQ_B rc = %d\n", rc); |
| 2873 | goto fail_init_status; |
| 2874 | } |
| 2875 | |
| 2876 | chip->battery_missing = (reg & IRQ_BATT_MISSING_BIT) ? true : false; |
| 2877 | |
| 2878 | rc = smb1351_read_reg(chip, IRQ_C_REG, ®); |
| 2879 | if (rc) { |
| 2880 | pr_err("Couldn't read IRQ_C rc = %d\n", rc); |
| 2881 | goto fail_init_status; |
| 2882 | } |
| 2883 | chip->batt_full = (reg & IRQ_TERM_BIT) ? true : false; |
| 2884 | |
| 2885 | rc = smb1351_read_reg(chip, IRQ_A_REG, ®); |
| 2886 | if (rc) { |
| 2887 | pr_err("Couldn't read irq A rc = %d\n", rc); |
| 2888 | return rc; |
| 2889 | } |
| 2890 | |
| 2891 | if (reg & IRQ_HOT_HARD_BIT) |
| 2892 | chip->batt_hot = true; |
| 2893 | if (reg & IRQ_COLD_HARD_BIT) |
| 2894 | chip->batt_cold = true; |
| 2895 | if (reg & IRQ_HOT_SOFT_BIT) |
| 2896 | chip->batt_warm = true; |
| 2897 | if (reg & IRQ_COLD_SOFT_BIT) |
| 2898 | chip->batt_cool = true; |
| 2899 | |
| 2900 | rc = smb1351_read_reg(chip, IRQ_E_REG, ®); |
| 2901 | if (rc) { |
| 2902 | pr_err("Couldn't read IRQ_E rc = %d\n", rc); |
| 2903 | goto fail_init_status; |
| 2904 | } |
| 2905 | |
| 2906 | if (reg & IRQ_USBIN_UV_BIT) { |
| 2907 | smb1351_usbin_uv_handler(chip, 1); |
| 2908 | } else { |
| 2909 | smb1351_usbin_uv_handler(chip, 0); |
| 2910 | smb1351_apsd_complete_handler(chip, 1); |
| 2911 | } |
| 2912 | |
| 2913 | rc = smb1351_read_reg(chip, IRQ_G_REG, ®); |
| 2914 | if (rc) { |
| 2915 | pr_err("Couldn't read IRQ_G rc = %d\n", rc); |
| 2916 | goto fail_init_status; |
| 2917 | } |
| 2918 | |
| 2919 | if (reg & IRQ_SOURCE_DET_BIT) |
| 2920 | smb1351_apsd_complete_handler(chip, 1); |
| 2921 | |
| 2922 | return 0; |
| 2923 | |
| 2924 | fail_init_status: |
| 2925 | pr_err("Couldn't determine initial status\n"); |
| 2926 | return rc; |
| 2927 | } |
| 2928 | |
| 2929 | static int is_parallel_charger(struct i2c_client *client) |
| 2930 | { |
| 2931 | struct device_node *node = client->dev.of_node; |
| 2932 | |
| 2933 | return of_property_read_bool(node, "qcom,parallel-charger"); |
| 2934 | } |
| 2935 | |
| 2936 | static int create_debugfs_entries(struct smb1351_charger *chip) |
| 2937 | { |
| 2938 | struct dentry *ent; |
| 2939 | |
| 2940 | chip->debug_root = debugfs_create_dir("smb1351", NULL); |
| 2941 | if (!chip->debug_root) { |
| 2942 | pr_err("Couldn't create debug dir\n"); |
| 2943 | } else { |
| 2944 | ent = debugfs_create_file("config_registers", S_IFREG | 0444, |
| 2945 | chip->debug_root, chip, |
| 2946 | &cnfg_debugfs_ops); |
| 2947 | if (!ent) |
| 2948 | pr_err("Couldn't create cnfg debug file\n"); |
| 2949 | |
| 2950 | ent = debugfs_create_file("status_registers", S_IFREG | 0444, |
| 2951 | chip->debug_root, chip, |
| 2952 | &status_debugfs_ops); |
| 2953 | if (!ent) |
| 2954 | pr_err("Couldn't create status debug file\n"); |
| 2955 | |
| 2956 | ent = debugfs_create_file("cmd_registers", S_IFREG | 0444, |
| 2957 | chip->debug_root, chip, |
| 2958 | &cmd_debugfs_ops); |
| 2959 | if (!ent) |
| 2960 | pr_err("Couldn't create cmd debug file\n"); |
| 2961 | |
| 2962 | ent = debugfs_create_x32("address", S_IFREG | 0644, |
| 2963 | chip->debug_root, |
| 2964 | &(chip->peek_poke_address)); |
| 2965 | if (!ent) |
| 2966 | pr_err("Couldn't create address debug file\n"); |
| 2967 | |
| 2968 | ent = debugfs_create_file("data", S_IFREG | 0644, |
| 2969 | chip->debug_root, chip, |
| 2970 | &poke_poke_debug_ops); |
| 2971 | if (!ent) |
| 2972 | pr_err("Couldn't create data debug file\n"); |
| 2973 | |
| 2974 | ent = debugfs_create_file("force_irq", |
| 2975 | S_IFREG | 0644, |
| 2976 | chip->debug_root, chip, |
| 2977 | &force_irq_ops); |
| 2978 | if (!ent) |
| 2979 | pr_err("Couldn't create data debug file\n"); |
| 2980 | |
| 2981 | ent = debugfs_create_file("irq_count", S_IFREG | 0444, |
| 2982 | chip->debug_root, chip, |
| 2983 | &irq_count_debugfs_ops); |
| 2984 | if (!ent) |
| 2985 | pr_err("Couldn't create count debug file\n"); |
| 2986 | } |
| 2987 | return 0; |
| 2988 | } |
| 2989 | |
| 2990 | static int smb1351_main_charger_probe(struct i2c_client *client, |
| 2991 | const struct i2c_device_id *id) |
| 2992 | { |
| 2993 | int rc; |
| 2994 | struct smb1351_charger *chip; |
| 2995 | struct power_supply *usb_psy; |
| 2996 | struct power_supply_config batt_psy_cfg = {}; |
| 2997 | u8 reg = 0; |
| 2998 | |
| 2999 | usb_psy = power_supply_get_by_name("usb"); |
| 3000 | if (!usb_psy) { |
| 3001 | pr_debug("USB psy not found; deferring probe\n"); |
| 3002 | return -EPROBE_DEFER; |
| 3003 | } |
| 3004 | |
| 3005 | chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); |
| 3006 | if (!chip) |
| 3007 | return -ENOMEM; |
| 3008 | |
| 3009 | chip->client = client; |
| 3010 | chip->dev = &client->dev; |
| 3011 | chip->usb_psy = usb_psy; |
| 3012 | chip->fake_battery_soc = -EINVAL; |
| 3013 | INIT_DELAYED_WORK(&chip->chg_remove_work, smb1351_chg_remove_work); |
| 3014 | INIT_DELAYED_WORK(&chip->hvdcp_det_work, smb1351_hvdcp_det_work); |
| 3015 | device_init_wakeup(chip->dev, true); |
| 3016 | |
| 3017 | /* probe the device to check if its actually connected */ |
| 3018 | rc = smb1351_read_reg(chip, CHG_REVISION_REG, ®); |
| 3019 | if (rc) { |
| 3020 | pr_err("Failed to detect smb1351, device may be absent\n"); |
| 3021 | return -ENODEV; |
| 3022 | } |
| 3023 | pr_debug("smb1351 chip revision is %d\n", reg); |
| 3024 | |
| 3025 | rc = smb1351_parse_dt(chip); |
| 3026 | if (rc) { |
| 3027 | pr_err("Couldn't parse DT nodes rc=%d\n", rc); |
| 3028 | return rc; |
| 3029 | } |
| 3030 | |
| 3031 | /* using vadc and adc_tm for implementing pmic therm */ |
| 3032 | if (chip->using_pmic_therm) { |
| 3033 | chip->vadc_dev = qpnp_get_vadc(chip->dev, "chg"); |
| 3034 | if (IS_ERR(chip->vadc_dev)) { |
| 3035 | rc = PTR_ERR(chip->vadc_dev); |
| 3036 | if (rc != -EPROBE_DEFER) |
| 3037 | pr_err("vadc property missing\n"); |
| 3038 | return rc; |
| 3039 | } |
| 3040 | chip->adc_tm_dev = qpnp_get_adc_tm(chip->dev, "chg"); |
| 3041 | if (IS_ERR(chip->adc_tm_dev)) { |
| 3042 | rc = PTR_ERR(chip->adc_tm_dev); |
| 3043 | if (rc != -EPROBE_DEFER) |
| 3044 | pr_err("adc_tm property missing\n"); |
| 3045 | return rc; |
| 3046 | } |
| 3047 | } |
| 3048 | |
| 3049 | i2c_set_clientdata(client, chip); |
| 3050 | |
| 3051 | chip->batt_psy_d.name = "battery"; |
| 3052 | chip->batt_psy_d.type = POWER_SUPPLY_TYPE_BATTERY; |
| 3053 | chip->batt_psy_d.get_property = smb1351_battery_get_property; |
| 3054 | chip->batt_psy_d.set_property = smb1351_battery_set_property; |
| 3055 | chip->batt_psy_d.property_is_writeable = |
| 3056 | smb1351_batt_property_is_writeable; |
| 3057 | chip->batt_psy_d.properties = smb1351_battery_properties; |
| 3058 | chip->batt_psy_d.num_properties = |
| 3059 | ARRAY_SIZE(smb1351_battery_properties); |
| 3060 | chip->batt_psy_d.external_power_changed = |
| 3061 | smb1351_external_power_changed; |
| 3062 | |
| 3063 | chip->resume_completed = true; |
| 3064 | mutex_init(&chip->irq_complete); |
| 3065 | |
| 3066 | batt_psy_cfg.drv_data = chip; |
| 3067 | batt_psy_cfg.supplied_to = pm_batt_supplied_to; |
| 3068 | batt_psy_cfg.num_supplicants = ARRAY_SIZE(pm_batt_supplied_to); |
| 3069 | chip->batt_psy = devm_power_supply_register(chip->dev, |
| 3070 | &chip->batt_psy_d, |
| 3071 | &batt_psy_cfg); |
| 3072 | if (IS_ERR(chip->batt_psy)) { |
| 3073 | pr_err("Couldn't register batt psy rc=%ld\n", |
| 3074 | PTR_ERR(chip->batt_psy)); |
| 3075 | return rc; |
| 3076 | } |
| 3077 | |
| 3078 | dump_regs(chip); |
| 3079 | |
| 3080 | rc = smb1351_regulator_init(chip); |
| 3081 | if (rc) { |
| 3082 | pr_err("Couldn't initialize smb1351 ragulator rc=%d\n", rc); |
| 3083 | goto fail_smb1351_regulator_init; |
| 3084 | } |
| 3085 | |
| 3086 | rc = smb1351_hw_init(chip); |
| 3087 | if (rc) { |
| 3088 | pr_err("Couldn't initialize hardware rc=%d\n", rc); |
| 3089 | goto fail_smb1351_hw_init; |
| 3090 | } |
| 3091 | |
| 3092 | rc = smb1351_determine_initial_state(chip); |
| 3093 | if (rc) { |
| 3094 | pr_err("Couldn't determine initial state rc=%d\n", rc); |
| 3095 | goto fail_smb1351_hw_init; |
| 3096 | } |
| 3097 | |
| 3098 | /* STAT irq configuration */ |
| 3099 | if (client->irq) { |
| 3100 | rc = devm_request_threaded_irq(&client->dev, client->irq, NULL, |
| 3101 | smb1351_chg_stat_handler, |
| 3102 | IRQF_TRIGGER_LOW | IRQF_ONESHOT, |
| 3103 | "smb1351_chg_stat_irq", chip); |
| 3104 | if (rc) { |
| 3105 | pr_err("Failed STAT irq=%d request rc = %d\n", |
| 3106 | client->irq, rc); |
| 3107 | goto fail_smb1351_hw_init; |
| 3108 | } |
| 3109 | enable_irq_wake(client->irq); |
| 3110 | } |
| 3111 | |
| 3112 | if (chip->using_pmic_therm) { |
| 3113 | if (!chip->jeita_supported) { |
| 3114 | /* add hot/cold temperature monitor */ |
| 3115 | chip->adc_param.low_temp = chip->batt_cold_decidegc; |
| 3116 | chip->adc_param.high_temp = chip->batt_hot_decidegc; |
| 3117 | } else { |
| 3118 | chip->adc_param.low_temp = chip->batt_cool_decidegc; |
| 3119 | chip->adc_param.high_temp = chip->batt_warm_decidegc; |
| 3120 | } |
Subbaraman Narayanamurthy | 87e9c9a | 2016-12-06 15:13:26 -0800 | [diff] [blame] | 3121 | chip->adc_param.timer_interval = ADC_MEAS1_INTERVAL_500MS; |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 3122 | chip->adc_param.state_request = ADC_TM_WARM_COOL_THR_ENABLE; |
| 3123 | chip->adc_param.btm_ctx = chip; |
| 3124 | chip->adc_param.threshold_notification = |
| 3125 | smb1351_chg_adc_notification; |
| 3126 | chip->adc_param.channel = LR_MUX1_BATT_THERM; |
| 3127 | |
| 3128 | rc = qpnp_adc_tm_channel_measure(chip->adc_tm_dev, |
| 3129 | &chip->adc_param); |
| 3130 | if (rc) { |
| 3131 | pr_err("requesting ADC error %d\n", rc); |
| 3132 | goto fail_smb1351_hw_init; |
| 3133 | } |
| 3134 | } |
| 3135 | |
| 3136 | create_debugfs_entries(chip); |
| 3137 | |
| 3138 | dump_regs(chip); |
| 3139 | |
| 3140 | pr_info("smb1351 successfully probed. charger=%d, batt=%d version=%s\n", |
| 3141 | chip->chg_present, |
| 3142 | smb1351_get_prop_batt_present(chip), |
| 3143 | smb1351_version_str[chip->version]); |
| 3144 | return 0; |
| 3145 | |
| 3146 | fail_smb1351_hw_init: |
| 3147 | regulator_unregister(chip->otg_vreg.rdev); |
| 3148 | fail_smb1351_regulator_init: |
| 3149 | return rc; |
| 3150 | } |
| 3151 | |
| 3152 | static int smb1351_parallel_charger_probe(struct i2c_client *client, |
| 3153 | const struct i2c_device_id *id) |
| 3154 | { |
| 3155 | int rc; |
| 3156 | struct smb1351_charger *chip; |
| 3157 | struct device_node *node = client->dev.of_node; |
| 3158 | struct power_supply_config parallel_psy_cfg = {}; |
| 3159 | |
| 3160 | chip = devm_kzalloc(&client->dev, sizeof(*chip), GFP_KERNEL); |
| 3161 | if (!chip) |
| 3162 | return -ENOMEM; |
| 3163 | |
| 3164 | chip->client = client; |
| 3165 | chip->dev = &client->dev; |
| 3166 | chip->parallel_charger = true; |
Ashay Jaiswal | 0513d34 | 2017-02-07 00:12:08 +0530 | [diff] [blame^] | 3167 | chip->parallel_charger_suspended = true; |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 3168 | |
| 3169 | chip->usb_suspended_status = of_property_read_bool(node, |
| 3170 | "qcom,charging-disabled"); |
| 3171 | rc = of_property_read_u32(node, "qcom,float-voltage-mv", |
| 3172 | &chip->vfloat_mv); |
| 3173 | if (rc) |
| 3174 | chip->vfloat_mv = -EINVAL; |
| 3175 | rc = of_property_read_u32(node, "qcom,recharge-mv", |
| 3176 | &chip->recharge_mv); |
| 3177 | if (rc) |
| 3178 | chip->recharge_mv = -EINVAL; |
| 3179 | |
| 3180 | rc = of_property_read_u32(node, "qcom,parallel-en-pin-polarity", |
| 3181 | &chip->parallel_pin_polarity_setting); |
| 3182 | if (rc) |
| 3183 | chip->parallel_pin_polarity_setting = EN_BY_PIN_LOW_ENABLE; |
| 3184 | else |
| 3185 | chip->parallel_pin_polarity_setting = |
| 3186 | chip->parallel_pin_polarity_setting ? |
| 3187 | EN_BY_PIN_HIGH_ENABLE : EN_BY_PIN_LOW_ENABLE; |
| 3188 | |
| 3189 | i2c_set_clientdata(client, chip); |
| 3190 | |
Abhijeet Dharmapurikar | 9a3a6c3 | 2017-01-06 18:27:29 -0800 | [diff] [blame] | 3191 | chip->parallel_psy_d.name = "parallel"; |
| 3192 | chip->parallel_psy_d.type = POWER_SUPPLY_TYPE_PARALLEL; |
Nicholas Troast | 6e8c038 | 2016-02-12 15:34:57 -0800 | [diff] [blame] | 3193 | chip->parallel_psy_d.get_property = smb1351_parallel_get_property; |
| 3194 | chip->parallel_psy_d.set_property = smb1351_parallel_set_property; |
| 3195 | chip->parallel_psy_d.properties = smb1351_parallel_properties; |
| 3196 | chip->parallel_psy_d.property_is_writeable |
| 3197 | = smb1351_parallel_is_writeable; |
| 3198 | chip->parallel_psy_d.num_properties |
| 3199 | = ARRAY_SIZE(smb1351_parallel_properties); |
| 3200 | |
| 3201 | parallel_psy_cfg.drv_data = chip; |
| 3202 | parallel_psy_cfg.num_supplicants = 0; |
| 3203 | chip->parallel_psy = devm_power_supply_register(chip->dev, |
| 3204 | &chip->parallel_psy_d, |
| 3205 | ¶llel_psy_cfg); |
| 3206 | if (IS_ERR(chip->parallel_psy)) { |
| 3207 | pr_err("Couldn't register parallel psy rc=%ld\n", |
| 3208 | PTR_ERR(chip->parallel_psy)); |
| 3209 | return rc; |
| 3210 | } |
| 3211 | |
| 3212 | chip->resume_completed = true; |
| 3213 | mutex_init(&chip->irq_complete); |
| 3214 | |
| 3215 | create_debugfs_entries(chip); |
| 3216 | |
| 3217 | pr_info("smb1351 parallel successfully probed.\n"); |
| 3218 | |
| 3219 | return 0; |
| 3220 | } |
| 3221 | |
| 3222 | static int smb1351_charger_probe(struct i2c_client *client, |
| 3223 | const struct i2c_device_id *id) |
| 3224 | { |
| 3225 | if (is_parallel_charger(client)) |
| 3226 | return smb1351_parallel_charger_probe(client, id); |
| 3227 | else |
| 3228 | return smb1351_main_charger_probe(client, id); |
| 3229 | } |
| 3230 | |
| 3231 | static int smb1351_charger_remove(struct i2c_client *client) |
| 3232 | { |
| 3233 | struct smb1351_charger *chip = i2c_get_clientdata(client); |
| 3234 | |
| 3235 | cancel_delayed_work_sync(&chip->chg_remove_work); |
| 3236 | |
| 3237 | mutex_destroy(&chip->irq_complete); |
| 3238 | debugfs_remove_recursive(chip->debug_root); |
| 3239 | return 0; |
| 3240 | } |
| 3241 | |
| 3242 | static int smb1351_suspend(struct device *dev) |
| 3243 | { |
| 3244 | struct i2c_client *client = to_i2c_client(dev); |
| 3245 | struct smb1351_charger *chip = i2c_get_clientdata(client); |
| 3246 | |
| 3247 | /* no suspend resume activities for parallel charger */ |
| 3248 | if (chip->parallel_charger) |
| 3249 | return 0; |
| 3250 | |
| 3251 | mutex_lock(&chip->irq_complete); |
| 3252 | chip->resume_completed = false; |
| 3253 | mutex_unlock(&chip->irq_complete); |
| 3254 | |
| 3255 | return 0; |
| 3256 | } |
| 3257 | |
| 3258 | static int smb1351_suspend_noirq(struct device *dev) |
| 3259 | { |
| 3260 | struct i2c_client *client = to_i2c_client(dev); |
| 3261 | struct smb1351_charger *chip = i2c_get_clientdata(client); |
| 3262 | |
| 3263 | /* no suspend resume activities for parallel charger */ |
| 3264 | if (chip->parallel_charger) |
| 3265 | return 0; |
| 3266 | |
| 3267 | if (chip->irq_waiting) { |
| 3268 | pr_err_ratelimited("Aborting suspend, an interrupt was detected while suspending\n"); |
| 3269 | return -EBUSY; |
| 3270 | } |
| 3271 | return 0; |
| 3272 | } |
| 3273 | |
| 3274 | static int smb1351_resume(struct device *dev) |
| 3275 | { |
| 3276 | struct i2c_client *client = to_i2c_client(dev); |
| 3277 | struct smb1351_charger *chip = i2c_get_clientdata(client); |
| 3278 | |
| 3279 | /* no suspend resume activities for parallel charger */ |
| 3280 | if (chip->parallel_charger) |
| 3281 | return 0; |
| 3282 | |
| 3283 | mutex_lock(&chip->irq_complete); |
| 3284 | chip->resume_completed = true; |
| 3285 | if (chip->irq_waiting) { |
| 3286 | mutex_unlock(&chip->irq_complete); |
| 3287 | smb1351_chg_stat_handler(client->irq, chip); |
| 3288 | enable_irq(client->irq); |
| 3289 | } else { |
| 3290 | mutex_unlock(&chip->irq_complete); |
| 3291 | } |
| 3292 | return 0; |
| 3293 | } |
| 3294 | |
| 3295 | static const struct dev_pm_ops smb1351_pm_ops = { |
| 3296 | .suspend = smb1351_suspend, |
| 3297 | .suspend_noirq = smb1351_suspend_noirq, |
| 3298 | .resume = smb1351_resume, |
| 3299 | }; |
| 3300 | |
| 3301 | static const struct of_device_id smb1351_match_table[] = { |
| 3302 | { .compatible = "qcom,smb1351-charger",}, |
| 3303 | { }, |
| 3304 | }; |
| 3305 | |
| 3306 | static const struct i2c_device_id smb1351_charger_id[] = { |
| 3307 | {"smb1351-charger", 0}, |
| 3308 | {}, |
| 3309 | }; |
| 3310 | MODULE_DEVICE_TABLE(i2c, smb1351_charger_id); |
| 3311 | |
| 3312 | static struct i2c_driver smb1351_charger_driver = { |
| 3313 | .driver = { |
| 3314 | .name = "smb1351-charger", |
| 3315 | .owner = THIS_MODULE, |
| 3316 | .of_match_table = smb1351_match_table, |
| 3317 | .pm = &smb1351_pm_ops, |
| 3318 | }, |
| 3319 | .probe = smb1351_charger_probe, |
| 3320 | .remove = smb1351_charger_remove, |
| 3321 | .id_table = smb1351_charger_id, |
| 3322 | }; |
| 3323 | |
| 3324 | module_i2c_driver(smb1351_charger_driver); |
| 3325 | |
| 3326 | MODULE_DESCRIPTION("smb1351 Charger"); |
| 3327 | MODULE_LICENSE("GPL v2"); |
| 3328 | MODULE_ALIAS("i2c:smb1351-charger"); |