Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 1 | /* |
Sujith | cee075a | 2009-03-13 09:07:23 +0530 | [diff] [blame] | 2 | * Copyright (c) 2008-2009 Atheros Communications Inc. |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 3 | * |
| 4 | * Permission to use, copy, modify, and/or distribute this software for any |
| 5 | * purpose with or without fee is hereby granted, provided that the above |
| 6 | * copyright notice and this permission notice appear in all copies. |
| 7 | * |
| 8 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES |
| 9 | * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF |
| 10 | * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR |
| 11 | * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES |
| 12 | * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN |
| 13 | * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF |
| 14 | * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. |
| 15 | */ |
| 16 | |
| 17 | #ifndef ANI_H |
| 18 | #define ANI_H |
| 19 | |
| 20 | #define HAL_PROCESS_ANI 0x00000001 |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 21 | |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 22 | #define DO_ANI(ah) (((ah)->proc_phyerr & HAL_PROCESS_ANI)) |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 23 | |
Vasanthakumar Thiagarajan | 22e66a4 | 2009-08-19 16:23:40 +0530 | [diff] [blame] | 24 | #define BEACON_RSSI(ahp) (ahp->stats.avgbrssi) |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 25 | |
| 26 | #define ATH9K_ANI_OFDM_TRIG_HIGH 500 |
| 27 | #define ATH9K_ANI_OFDM_TRIG_LOW 200 |
| 28 | #define ATH9K_ANI_CCK_TRIG_HIGH 200 |
| 29 | #define ATH9K_ANI_CCK_TRIG_LOW 100 |
| 30 | #define ATH9K_ANI_NOISE_IMMUNE_LVL 4 |
| 31 | #define ATH9K_ANI_USE_OFDM_WEAK_SIG true |
| 32 | #define ATH9K_ANI_CCK_WEAK_SIG_THR false |
| 33 | #define ATH9K_ANI_SPUR_IMMUNE_LVL 7 |
| 34 | #define ATH9K_ANI_FIRSTEP_LVL 0 |
| 35 | #define ATH9K_ANI_RSSI_THR_HIGH 40 |
| 36 | #define ATH9K_ANI_RSSI_THR_LOW 7 |
| 37 | #define ATH9K_ANI_PERIOD 100 |
| 38 | |
| 39 | #define HAL_NOISE_IMMUNE_MAX 4 |
| 40 | #define HAL_SPUR_IMMUNE_MAX 7 |
| 41 | #define HAL_FIRST_STEP_MAX 2 |
| 42 | |
| 43 | enum ath9k_ani_cmd { |
| 44 | ATH9K_ANI_PRESENT = 0x1, |
| 45 | ATH9K_ANI_NOISE_IMMUNITY_LEVEL = 0x2, |
| 46 | ATH9K_ANI_OFDM_WEAK_SIGNAL_DETECTION = 0x4, |
| 47 | ATH9K_ANI_CCK_WEAK_SIGNAL_THR = 0x8, |
| 48 | ATH9K_ANI_FIRSTEP_LEVEL = 0x10, |
| 49 | ATH9K_ANI_SPUR_IMMUNITY_LEVEL = 0x20, |
| 50 | ATH9K_ANI_MODE = 0x40, |
| 51 | ATH9K_ANI_PHYERR_RESET = 0x80, |
| 52 | ATH9K_ANI_ALL = 0xff |
| 53 | }; |
| 54 | |
| 55 | struct ath9k_mib_stats { |
| 56 | u32 ackrcv_bad; |
| 57 | u32 rts_bad; |
| 58 | u32 rts_good; |
| 59 | u32 fcs_bad; |
| 60 | u32 beacons; |
| 61 | }; |
| 62 | |
Sujith | ee6e8d1 | 2009-02-09 13:29:49 +0530 | [diff] [blame] | 63 | struct ar5416AniState { |
| 64 | struct ath9k_channel *c; |
| 65 | u8 noiseImmunityLevel; |
| 66 | u8 spurImmunityLevel; |
| 67 | u8 firstepLevel; |
| 68 | u8 ofdmWeakSigDetectOff; |
| 69 | u8 cckWeakSigThreshold; |
| 70 | u32 listenTime; |
| 71 | u32 ofdmTrigHigh; |
| 72 | u32 ofdmTrigLow; |
| 73 | int32_t cckTrigHigh; |
| 74 | int32_t cckTrigLow; |
| 75 | int32_t rssiThrLow; |
| 76 | int32_t rssiThrHigh; |
| 77 | u32 noiseFloor; |
| 78 | u32 txFrameCount; |
| 79 | u32 rxFrameCount; |
| 80 | u32 cycleCount; |
| 81 | u32 ofdmPhyErrCount; |
| 82 | u32 cckPhyErrCount; |
| 83 | u32 ofdmPhyErrBase; |
| 84 | u32 cckPhyErrBase; |
| 85 | int16_t pktRssi[2]; |
| 86 | int16_t ofdmErrRssi[2]; |
| 87 | int16_t cckErrRssi[2]; |
| 88 | }; |
| 89 | |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 90 | struct ar5416Stats { |
| 91 | u32 ast_ani_niup; |
| 92 | u32 ast_ani_nidown; |
| 93 | u32 ast_ani_spurup; |
| 94 | u32 ast_ani_spurdown; |
| 95 | u32 ast_ani_ofdmon; |
| 96 | u32 ast_ani_ofdmoff; |
| 97 | u32 ast_ani_cckhigh; |
| 98 | u32 ast_ani_ccklow; |
| 99 | u32 ast_ani_stepup; |
| 100 | u32 ast_ani_stepdown; |
| 101 | u32 ast_ani_ofdmerrs; |
| 102 | u32 ast_ani_cckerrs; |
| 103 | u32 ast_ani_reset; |
| 104 | u32 ast_ani_lzero; |
| 105 | u32 ast_ani_lneg; |
Vasanthakumar Thiagarajan | 22e66a4 | 2009-08-19 16:23:40 +0530 | [diff] [blame] | 106 | u32 avgbrssi; |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 107 | struct ath9k_mib_stats ast_mibstats; |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 108 | }; |
Sujith | 2660b81 | 2009-02-09 13:27:26 +0530 | [diff] [blame] | 109 | #define ah_mibStats stats.ast_mibstats |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 110 | |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 111 | void ath9k_ani_reset(struct ath_hw *ah); |
| 112 | void ath9k_hw_ani_monitor(struct ath_hw *ah, |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 113 | struct ath9k_channel *chan); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 114 | void ath9k_enable_mib_counters(struct ath_hw *ah); |
| 115 | void ath9k_hw_disable_mib_counters(struct ath_hw *ah); |
| 116 | u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah, u32 *rxc_pcnt, |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 117 | u32 *rxf_pcnt, u32 *txf_pcnt); |
Vasanthakumar Thiagarajan | 22e66a4 | 2009-08-19 16:23:40 +0530 | [diff] [blame] | 118 | void ath9k_hw_procmibevent(struct ath_hw *ah); |
Sujith | cbe61d8 | 2009-02-09 13:27:12 +0530 | [diff] [blame] | 119 | void ath9k_hw_ani_setup(struct ath_hw *ah); |
Luis R. Rodriguez | f637cfd | 2009-08-03 12:24:46 -0700 | [diff] [blame] | 120 | void ath9k_hw_ani_init(struct ath_hw *ah); |
Luis R. Rodriguez | e70c0cf | 2009-08-03 12:24:51 -0700 | [diff] [blame] | 121 | void ath9k_hw_ani_disable(struct ath_hw *ah); |
Sujith | 394cf0a | 2009-02-09 13:26:54 +0530 | [diff] [blame] | 122 | |
| 123 | #endif /* ANI_H */ |