| Antoine Ténart | a2418f4 | 2014-06-04 18:03:44 +0200 | [diff] [blame] | 1 | ======================================================== |
| 2 | Secondary CPU enable-method "marvell,berlin-smp" binding |
| 3 | ======================================================== |
| 4 | |
| 5 | This document describes the "marvell,berlin-smp" method for enabling secondary |
| 6 | CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should |
| 7 | be defined in the "cpus" node. |
| 8 | |
| 9 | Enable method name: "marvell,berlin-smp" |
| 10 | Compatible machines: "marvell,berlin2" and "marvell,berlin2q" |
| 11 | Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9" |
| 12 | Related properties: (none) |
| 13 | |
| 14 | Note: |
| 15 | This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and |
| 16 | "marvell,berlin-cpu-ctrl"[1]. |
| 17 | |
| 18 | Example: |
| 19 | |
| 20 | cpus { |
| 21 | #address-cells = <1>; |
| 22 | #size-cells = <0>; |
| 23 | enable-method = "marvell,berlin-smp"; |
| 24 | |
| 25 | cpu@0 { |
| 26 | compatible = "marvell,pj4b"; |
| 27 | device_type = "cpu"; |
| 28 | next-level-cache = <&l2>; |
| 29 | reg = <0>; |
| 30 | }; |
| 31 | |
| 32 | cpu@1 { |
| 33 | compatible = "marvell,pj4b"; |
| 34 | device_type = "cpu"; |
| 35 | next-level-cache = <&l2>; |
| 36 | reg = <1>; |
| 37 | }; |
| 38 | }; |
| 39 | |
| 40 | -- |
| 41 | [1] arm/marvell,berlin.txt |