blob: 1e6bdba2675639568443cc1afb7ca5e603ae151a [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * linux/drivers/mmc/mmci.c - ARM PrimeCell MMCI PL180/1 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#include <linux/config.h>
11#include <linux/module.h>
12#include <linux/moduleparam.h>
13#include <linux/init.h>
14#include <linux/ioport.h>
15#include <linux/device.h>
16#include <linux/interrupt.h>
17#include <linux/delay.h>
18#include <linux/err.h>
19#include <linux/highmem.h>
20#include <linux/mmc/host.h>
21#include <linux/mmc/protocol.h>
22
Russell King7b09cda2005-07-01 12:02:59 +010023#include <asm/div64.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070024#include <asm/io.h>
25#include <asm/irq.h>
26#include <asm/scatterlist.h>
Russell Kingc6b8fda2005-10-28 14:05:16 +010027#include <asm/sizes.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070028#include <asm/hardware/amba.h>
29#include <asm/hardware/clock.h>
30#include <asm/mach/mmc.h>
31
32#include "mmci.h"
33
34#define DRIVER_NAME "mmci-pl18x"
35
36#ifdef CONFIG_MMC_DEBUG
37#define DBG(host,fmt,args...) \
Russell Kingd366b642005-08-19 09:40:08 +010038 pr_debug("%s: %s: " fmt, mmc_hostname(host->mmc), __func__ , args)
Linus Torvalds1da177e2005-04-16 15:20:36 -070039#else
40#define DBG(host,fmt,args...) do { } while (0)
41#endif
42
43static unsigned int fmax = 515633;
44
45static void
46mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
47{
48 writel(0, host->base + MMCICOMMAND);
49
50 host->mrq = NULL;
51 host->cmd = NULL;
52
53 if (mrq->data)
54 mrq->data->bytes_xfered = host->data_xfered;
55
56 /*
57 * Need to drop the host lock here; mmc_request_done may call
58 * back into the driver...
59 */
60 spin_unlock(&host->lock);
61 mmc_request_done(host->mmc, mrq);
62 spin_lock(&host->lock);
63}
64
65static void mmci_stop_data(struct mmci_host *host)
66{
67 writel(0, host->base + MMCIDATACTRL);
68 writel(0, host->base + MMCIMASK1);
69 host->data = NULL;
70}
71
72static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
73{
74 unsigned int datactrl, timeout, irqmask;
Russell King7b09cda2005-07-01 12:02:59 +010075 unsigned long long clks;
Linus Torvalds1da177e2005-04-16 15:20:36 -070076 void __iomem *base;
77
78 DBG(host, "blksz %04x blks %04x flags %08x\n",
79 1 << data->blksz_bits, data->blocks, data->flags);
80
81 host->data = data;
82 host->size = data->blocks << data->blksz_bits;
83 host->data_xfered = 0;
84
85 mmci_init_sg(host, data);
86
Russell King7b09cda2005-07-01 12:02:59 +010087 clks = (unsigned long long)data->timeout_ns * host->cclk;
88 do_div(clks, 1000000000UL);
89
90 timeout = data->timeout_clks + (unsigned int)clks;
Linus Torvalds1da177e2005-04-16 15:20:36 -070091
92 base = host->base;
93 writel(timeout, base + MMCIDATATIMER);
94 writel(host->size, base + MMCIDATALENGTH);
95
96 datactrl = MCI_DPSM_ENABLE | data->blksz_bits << 4;
97 if (data->flags & MMC_DATA_READ) {
98 datactrl |= MCI_DPSM_DIRECTION;
99 irqmask = MCI_RXFIFOHALFFULLMASK;
100 } else {
101 /*
102 * We don't actually need to include "FIFO empty" here
103 * since its implicit in "FIFO half empty".
104 */
105 irqmask = MCI_TXFIFOHALFEMPTYMASK;
106 }
107
108 writel(datactrl, base + MMCIDATACTRL);
109 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
110 writel(irqmask, base + MMCIMASK1);
111}
112
113static void
114mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
115{
116 void __iomem *base = host->base;
117
118 DBG(host, "op %02x arg %08x flags %08x\n",
119 cmd->opcode, cmd->arg, cmd->flags);
120
121 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
122 writel(0, base + MMCICOMMAND);
123 udelay(1);
124 }
125
126 c |= cmd->opcode | MCI_CPSM_ENABLE;
127 switch (cmd->flags & MMC_RSP_MASK) {
128 case MMC_RSP_NONE:
129 default:
130 break;
131 case MMC_RSP_LONG:
132 c |= MCI_CPSM_LONGRSP;
133 case MMC_RSP_SHORT:
134 c |= MCI_CPSM_RESPONSE;
135 break;
136 }
137 if (/*interrupt*/0)
138 c |= MCI_CPSM_INTERRUPT;
139
140 host->cmd = cmd;
141
142 writel(cmd->arg, base + MMCIARGUMENT);
143 writel(c, base + MMCICOMMAND);
144}
145
146static void
147mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
148 unsigned int status)
149{
150 if (status & MCI_DATABLOCKEND) {
151 host->data_xfered += 1 << data->blksz_bits;
152 }
153 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|MCI_RXOVERRUN)) {
154 if (status & MCI_DATACRCFAIL)
155 data->error = MMC_ERR_BADCRC;
156 else if (status & MCI_DATATIMEOUT)
157 data->error = MMC_ERR_TIMEOUT;
158 else if (status & (MCI_TXUNDERRUN|MCI_RXOVERRUN))
159 data->error = MMC_ERR_FIFO;
160 status |= MCI_DATAEND;
161 }
162 if (status & MCI_DATAEND) {
163 mmci_stop_data(host);
164
165 if (!data->stop) {
166 mmci_request_end(host, data->mrq);
167 } else {
168 mmci_start_command(host, data->stop, 0);
169 }
170 }
171}
172
173static void
174mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
175 unsigned int status)
176{
177 void __iomem *base = host->base;
178
179 host->cmd = NULL;
180
181 cmd->resp[0] = readl(base + MMCIRESPONSE0);
182 cmd->resp[1] = readl(base + MMCIRESPONSE1);
183 cmd->resp[2] = readl(base + MMCIRESPONSE2);
184 cmd->resp[3] = readl(base + MMCIRESPONSE3);
185
186 if (status & MCI_CMDTIMEOUT) {
187 cmd->error = MMC_ERR_TIMEOUT;
188 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
189 cmd->error = MMC_ERR_BADCRC;
190 }
191
192 if (!cmd->data || cmd->error != MMC_ERR_NONE) {
193 mmci_request_end(host, cmd->mrq);
194 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
195 mmci_start_data(host, cmd->data);
196 }
197}
198
199static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
200{
201 void __iomem *base = host->base;
202 char *ptr = buffer;
203 u32 status;
204
205 do {
206 int count = host->size - (readl(base + MMCIFIFOCNT) << 2);
207
208 if (count > remain)
209 count = remain;
210
211 if (count <= 0)
212 break;
213
214 readsl(base + MMCIFIFO, ptr, count >> 2);
215
216 ptr += count;
217 remain -= count;
218
219 if (remain == 0)
220 break;
221
222 status = readl(base + MMCISTATUS);
223 } while (status & MCI_RXDATAAVLBL);
224
225 return ptr - buffer;
226}
227
228static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
229{
230 void __iomem *base = host->base;
231 char *ptr = buffer;
232
233 do {
234 unsigned int count, maxcnt;
235
236 maxcnt = status & MCI_TXFIFOEMPTY ? MCI_FIFOSIZE : MCI_FIFOHALFSIZE;
237 count = min(remain, maxcnt);
238
239 writesl(base + MMCIFIFO, ptr, count >> 2);
240
241 ptr += count;
242 remain -= count;
243
244 if (remain == 0)
245 break;
246
247 status = readl(base + MMCISTATUS);
248 } while (status & MCI_TXFIFOHALFEMPTY);
249
250 return ptr - buffer;
251}
252
253/*
254 * PIO data transfer IRQ handler.
255 */
256static irqreturn_t mmci_pio_irq(int irq, void *dev_id, struct pt_regs *regs)
257{
258 struct mmci_host *host = dev_id;
259 void __iomem *base = host->base;
260 u32 status;
261
262 status = readl(base + MMCISTATUS);
263
264 DBG(host, "irq1 %08x\n", status);
265
266 do {
267 unsigned long flags;
268 unsigned int remain, len;
269 char *buffer;
270
271 /*
272 * For write, we only need to test the half-empty flag
273 * here - if the FIFO is completely empty, then by
274 * definition it is more than half empty.
275 *
276 * For read, check for data available.
277 */
278 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
279 break;
280
281 /*
282 * Map the current scatter buffer.
283 */
284 buffer = mmci_kmap_atomic(host, &flags) + host->sg_off;
285 remain = host->sg_ptr->length - host->sg_off;
286
287 len = 0;
288 if (status & MCI_RXACTIVE)
289 len = mmci_pio_read(host, buffer, remain);
290 if (status & MCI_TXACTIVE)
291 len = mmci_pio_write(host, buffer, remain, status);
292
293 /*
294 * Unmap the buffer.
295 */
296 mmci_kunmap_atomic(host, &flags);
297
298 host->sg_off += len;
299 host->size -= len;
300 remain -= len;
301
302 if (remain)
303 break;
304
305 if (!mmci_next_sg(host))
306 break;
307
308 status = readl(base + MMCISTATUS);
309 } while (1);
310
311 /*
312 * If we're nearing the end of the read, switch to
313 * "any data available" mode.
314 */
315 if (status & MCI_RXACTIVE && host->size < MCI_FIFOSIZE)
316 writel(MCI_RXDATAAVLBLMASK, base + MMCIMASK1);
317
318 /*
319 * If we run out of data, disable the data IRQs; this
320 * prevents a race where the FIFO becomes empty before
321 * the chip itself has disabled the data path, and
322 * stops us racing with our data end IRQ.
323 */
324 if (host->size == 0) {
325 writel(0, base + MMCIMASK1);
326 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
327 }
328
329 return IRQ_HANDLED;
330}
331
332/*
333 * Handle completion of command and data transfers.
334 */
335static irqreturn_t mmci_irq(int irq, void *dev_id, struct pt_regs *regs)
336{
337 struct mmci_host *host = dev_id;
338 u32 status;
339 int ret = 0;
340
341 spin_lock(&host->lock);
342
343 do {
344 struct mmc_command *cmd;
345 struct mmc_data *data;
346
347 status = readl(host->base + MMCISTATUS);
348 status &= readl(host->base + MMCIMASK0);
349 writel(status, host->base + MMCICLEAR);
350
351 DBG(host, "irq0 %08x\n", status);
352
353 data = host->data;
354 if (status & (MCI_DATACRCFAIL|MCI_DATATIMEOUT|MCI_TXUNDERRUN|
355 MCI_RXOVERRUN|MCI_DATAEND|MCI_DATABLOCKEND) && data)
356 mmci_data_irq(host, data, status);
357
358 cmd = host->cmd;
359 if (status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND) && cmd)
360 mmci_cmd_irq(host, cmd, status);
361
362 ret = 1;
363 } while (status);
364
365 spin_unlock(&host->lock);
366
367 return IRQ_RETVAL(ret);
368}
369
370static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
371{
372 struct mmci_host *host = mmc_priv(mmc);
373
374 WARN_ON(host->mrq != NULL);
375
376 spin_lock_irq(&host->lock);
377
378 host->mrq = mrq;
379
380 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
381 mmci_start_data(host, mrq->data);
382
383 mmci_start_command(host, mrq->cmd, 0);
384
385 spin_unlock_irq(&host->lock);
386}
387
388static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
389{
390 struct mmci_host *host = mmc_priv(mmc);
391 u32 clk = 0, pwr = 0;
392
393 DBG(host, "clock %uHz busmode %u powermode %u Vdd %u\n",
394 ios->clock, ios->bus_mode, ios->power_mode, ios->vdd);
395
396 if (ios->clock) {
397 if (ios->clock >= host->mclk) {
398 clk = MCI_CLK_BYPASS;
399 host->cclk = host->mclk;
400 } else {
401 clk = host->mclk / (2 * ios->clock) - 1;
402 if (clk > 256)
403 clk = 255;
404 host->cclk = host->mclk / (2 * (clk + 1));
405 }
406 clk |= MCI_CLK_ENABLE;
407 }
408
409 if (host->plat->translate_vdd)
410 pwr |= host->plat->translate_vdd(mmc_dev(mmc), ios->vdd);
411
412 switch (ios->power_mode) {
413 case MMC_POWER_OFF:
414 break;
415 case MMC_POWER_UP:
416 pwr |= MCI_PWR_UP;
417 break;
418 case MMC_POWER_ON:
419 pwr |= MCI_PWR_ON;
420 break;
421 }
422
423 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
424 pwr |= MCI_ROD;
425
426 writel(clk, host->base + MMCICLOCK);
427
428 if (host->pwr != pwr) {
429 host->pwr = pwr;
430 writel(pwr, host->base + MMCIPOWER);
431 }
432}
433
434static struct mmc_host_ops mmci_ops = {
435 .request = mmci_request,
436 .set_ios = mmci_set_ios,
437};
438
439static void mmci_check_status(unsigned long data)
440{
441 struct mmci_host *host = (struct mmci_host *)data;
442 unsigned int status;
443
444 status = host->plat->status(mmc_dev(host->mmc));
445 if (status ^ host->oldstat)
Richard Purdie8dc00332005-09-08 17:53:01 +0100446 mmc_detect_change(host->mmc, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700447
448 host->oldstat = status;
449 mod_timer(&host->timer, jiffies + HZ);
450}
451
452static int mmci_probe(struct amba_device *dev, void *id)
453{
454 struct mmc_platform_data *plat = dev->dev.platform_data;
455 struct mmci_host *host;
456 struct mmc_host *mmc;
457 int ret;
458
459 /* must have platform data */
460 if (!plat) {
461 ret = -EINVAL;
462 goto out;
463 }
464
465 ret = amba_request_regions(dev, DRIVER_NAME);
466 if (ret)
467 goto out;
468
469 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
470 if (!mmc) {
471 ret = -ENOMEM;
472 goto rel_regions;
473 }
474
475 host = mmc_priv(mmc);
476 host->clk = clk_get(&dev->dev, "MCLK");
477 if (IS_ERR(host->clk)) {
478 ret = PTR_ERR(host->clk);
479 host->clk = NULL;
480 goto host_free;
481 }
482
483 ret = clk_use(host->clk);
484 if (ret)
485 goto clk_free;
486
487 ret = clk_enable(host->clk);
488 if (ret)
489 goto clk_unuse;
490
491 host->plat = plat;
492 host->mclk = clk_get_rate(host->clk);
493 host->mmc = mmc;
494 host->base = ioremap(dev->res.start, SZ_4K);
495 if (!host->base) {
496 ret = -ENOMEM;
497 goto clk_disable;
498 }
499
500 mmc->ops = &mmci_ops;
501 mmc->f_min = (host->mclk + 511) / 512;
502 mmc->f_max = min(host->mclk, fmax);
503 mmc->ocr_avail = plat->ocr_mask;
504
505 /*
506 * We can do SGIO
507 */
508 mmc->max_hw_segs = 16;
509 mmc->max_phys_segs = NR_SG;
510
511 /*
512 * Since we only have a 16-bit data length register, we must
513 * ensure that we don't exceed 2^16-1 bytes in a single request.
514 * Choose 64 (512-byte) sectors as the limit.
515 */
516 mmc->max_sectors = 64;
517
518 /*
519 * Set the maximum segment size. Since we aren't doing DMA
520 * (yet) we are only limited by the data length register.
521 */
522 mmc->max_seg_size = mmc->max_sectors << 9;
523
524 spin_lock_init(&host->lock);
525
526 writel(0, host->base + MMCIMASK0);
527 writel(0, host->base + MMCIMASK1);
528 writel(0xfff, host->base + MMCICLEAR);
529
530 ret = request_irq(dev->irq[0], mmci_irq, SA_SHIRQ, DRIVER_NAME " (cmd)", host);
531 if (ret)
532 goto unmap;
533
534 ret = request_irq(dev->irq[1], mmci_pio_irq, SA_SHIRQ, DRIVER_NAME " (pio)", host);
535 if (ret)
536 goto irq0_free;
537
538 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
539
540 amba_set_drvdata(dev, mmc);
541
542 mmc_add_host(mmc);
543
544 printk(KERN_INFO "%s: MMCI rev %x cfg %02x at 0x%08lx irq %d,%d\n",
Russell Kingd366b642005-08-19 09:40:08 +0100545 mmc_hostname(mmc), amba_rev(dev), amba_config(dev),
Linus Torvalds1da177e2005-04-16 15:20:36 -0700546 dev->res.start, dev->irq[0], dev->irq[1]);
547
548 init_timer(&host->timer);
549 host->timer.data = (unsigned long)host;
550 host->timer.function = mmci_check_status;
551 host->timer.expires = jiffies + HZ;
552 add_timer(&host->timer);
553
554 return 0;
555
556 irq0_free:
557 free_irq(dev->irq[0], host);
558 unmap:
559 iounmap(host->base);
560 clk_disable:
561 clk_disable(host->clk);
562 clk_unuse:
563 clk_unuse(host->clk);
564 clk_free:
565 clk_put(host->clk);
566 host_free:
567 mmc_free_host(mmc);
568 rel_regions:
569 amba_release_regions(dev);
570 out:
571 return ret;
572}
573
574static int mmci_remove(struct amba_device *dev)
575{
576 struct mmc_host *mmc = amba_get_drvdata(dev);
577
578 amba_set_drvdata(dev, NULL);
579
580 if (mmc) {
581 struct mmci_host *host = mmc_priv(mmc);
582
583 del_timer_sync(&host->timer);
584
585 mmc_remove_host(mmc);
586
587 writel(0, host->base + MMCIMASK0);
588 writel(0, host->base + MMCIMASK1);
589
590 writel(0, host->base + MMCICOMMAND);
591 writel(0, host->base + MMCIDATACTRL);
592
593 free_irq(dev->irq[0], host);
594 free_irq(dev->irq[1], host);
595
596 iounmap(host->base);
597 clk_disable(host->clk);
598 clk_unuse(host->clk);
599 clk_put(host->clk);
600
601 mmc_free_host(mmc);
602
603 amba_release_regions(dev);
604 }
605
606 return 0;
607}
608
609#ifdef CONFIG_PM
Pavel Macheke5378ca2005-04-16 15:25:29 -0700610static int mmci_suspend(struct amba_device *dev, pm_message_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700611{
612 struct mmc_host *mmc = amba_get_drvdata(dev);
613 int ret = 0;
614
615 if (mmc) {
616 struct mmci_host *host = mmc_priv(mmc);
617
618 ret = mmc_suspend_host(mmc, state);
619 if (ret == 0)
620 writel(0, host->base + MMCIMASK0);
621 }
622
623 return ret;
624}
625
626static int mmci_resume(struct amba_device *dev)
627{
628 struct mmc_host *mmc = amba_get_drvdata(dev);
629 int ret = 0;
630
631 if (mmc) {
632 struct mmci_host *host = mmc_priv(mmc);
633
634 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
635
636 ret = mmc_resume_host(mmc);
637 }
638
639 return ret;
640}
641#else
642#define mmci_suspend NULL
643#define mmci_resume NULL
644#endif
645
646static struct amba_id mmci_ids[] = {
647 {
648 .id = 0x00041180,
649 .mask = 0x000fffff,
650 },
651 {
652 .id = 0x00041181,
653 .mask = 0x000fffff,
654 },
655 { 0, 0 },
656};
657
658static struct amba_driver mmci_driver = {
659 .drv = {
660 .name = DRIVER_NAME,
661 },
662 .probe = mmci_probe,
663 .remove = mmci_remove,
664 .suspend = mmci_suspend,
665 .resume = mmci_resume,
666 .id_table = mmci_ids,
667};
668
669static int __init mmci_init(void)
670{
671 return amba_driver_register(&mmci_driver);
672}
673
674static void __exit mmci_exit(void)
675{
676 amba_driver_unregister(&mmci_driver);
677}
678
679module_init(mmci_init);
680module_exit(mmci_exit);
681module_param(fmax, uint, 0444);
682
683MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
684MODULE_LICENSE("GPL");