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Mattias Nilssonfea799e2011-08-12 10:28:02 +02001/*
2 * Copyright (C) ST Ericsson SA 2011
3 *
4 * License Terms: GNU General Public License v2
5 *
6 * STE Ux500 PRCMU API
7 */
8#ifndef __MACH_PRCMU_H
9#define __MACH_PRCMU_H
10
11#include <linux/interrupt.h>
12#include <linux/notifier.h>
Mattias Nilsson05089012012-01-13 16:20:20 +010013#include <linux/err.h>
Mattias Nilssonfea799e2011-08-12 10:28:02 +020014
Linus Walleij05ec2602013-02-07 10:17:31 +010015/* Offset for the firmware version within the TCPM */
16#define DB8500_PRCMU_FW_VERSION_OFFSET 0xA4
17#define DBX540_PRCMU_FW_VERSION_OFFSET 0xA8
18
Mattias Nilssonfea799e2011-08-12 10:28:02 +020019/* PRCMU Wakeup defines */
20enum prcmu_wakeup_index {
21 PRCMU_WAKEUP_INDEX_RTC,
22 PRCMU_WAKEUP_INDEX_RTT0,
23 PRCMU_WAKEUP_INDEX_RTT1,
24 PRCMU_WAKEUP_INDEX_HSI0,
25 PRCMU_WAKEUP_INDEX_HSI1,
26 PRCMU_WAKEUP_INDEX_USB,
27 PRCMU_WAKEUP_INDEX_ABB,
28 PRCMU_WAKEUP_INDEX_ABB_FIFO,
29 PRCMU_WAKEUP_INDEX_ARM,
30 PRCMU_WAKEUP_INDEX_CD_IRQ,
31 NUM_PRCMU_WAKEUP_INDICES
32};
33#define PRCMU_WAKEUP(_name) (BIT(PRCMU_WAKEUP_INDEX_##_name))
34
35/* EPOD (power domain) IDs */
36
37/*
38 * DB8500 EPODs
39 * - EPOD_ID_SVAMMDSP: power domain for SVA MMDSP
40 * - EPOD_ID_SVAPIPE: power domain for SVA pipe
41 * - EPOD_ID_SIAMMDSP: power domain for SIA MMDSP
42 * - EPOD_ID_SIAPIPE: power domain for SIA pipe
43 * - EPOD_ID_SGA: power domain for SGA
44 * - EPOD_ID_B2R2_MCDE: power domain for B2R2 and MCDE
45 * - EPOD_ID_ESRAM12: power domain for ESRAM 1 and 2
46 * - EPOD_ID_ESRAM34: power domain for ESRAM 3 and 4
47 * - NUM_EPOD_ID: number of power domains
48 *
49 * TODO: These should be prefixed.
50 */
51#define EPOD_ID_SVAMMDSP 0
52#define EPOD_ID_SVAPIPE 1
53#define EPOD_ID_SIAMMDSP 2
54#define EPOD_ID_SIAPIPE 3
55#define EPOD_ID_SGA 4
56#define EPOD_ID_B2R2_MCDE 5
57#define EPOD_ID_ESRAM12 6
58#define EPOD_ID_ESRAM34 7
59#define NUM_EPOD_ID 8
60
61/*
Mattias Nilssonfea799e2011-08-12 10:28:02 +020062 * state definition for EPOD (power domain)
63 * - EPOD_STATE_NO_CHANGE: The EPOD should remain unchanged
64 * - EPOD_STATE_OFF: The EPOD is switched off
65 * - EPOD_STATE_RAMRET: The EPOD is switched off with its internal RAM in
66 * retention
67 * - EPOD_STATE_ON_CLK_OFF: The EPOD is switched on, clock is still off
68 * - EPOD_STATE_ON: Same as above, but with clock enabled
69 */
70#define EPOD_STATE_NO_CHANGE 0x00
71#define EPOD_STATE_OFF 0x01
72#define EPOD_STATE_RAMRET 0x02
73#define EPOD_STATE_ON_CLK_OFF 0x03
74#define EPOD_STATE_ON 0x04
75
76/*
77 * CLKOUT sources
78 */
79#define PRCMU_CLKSRC_CLK38M 0x00
80#define PRCMU_CLKSRC_ACLK 0x01
81#define PRCMU_CLKSRC_SYSCLK 0x02
82#define PRCMU_CLKSRC_LCDCLK 0x03
83#define PRCMU_CLKSRC_SDMMCCLK 0x04
84#define PRCMU_CLKSRC_TVCLK 0x05
85#define PRCMU_CLKSRC_TIMCLK 0x06
86#define PRCMU_CLKSRC_CLK009 0x07
87/* These are only valid for CLKOUT1: */
88#define PRCMU_CLKSRC_SIAMMDSPCLK 0x40
89#define PRCMU_CLKSRC_I2CCLK 0x41
90#define PRCMU_CLKSRC_MSP02CLK 0x42
91#define PRCMU_CLKSRC_ARMPLL_OBSCLK 0x43
92#define PRCMU_CLKSRC_HSIRXCLK 0x44
93#define PRCMU_CLKSRC_HSITXCLK 0x45
94#define PRCMU_CLKSRC_ARMCLKFIX 0x46
95#define PRCMU_CLKSRC_HDMICLK 0x47
96
97/*
98 * Clock identifiers.
99 */
100enum prcmu_clock {
101 PRCMU_SGACLK,
102 PRCMU_UARTCLK,
103 PRCMU_MSP02CLK,
104 PRCMU_MSP1CLK,
105 PRCMU_I2CCLK,
106 PRCMU_SDMMCCLK,
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100107 PRCMU_SPARE1CLK,
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200108 PRCMU_SLIMCLK,
109 PRCMU_PER1CLK,
110 PRCMU_PER2CLK,
111 PRCMU_PER3CLK,
112 PRCMU_PER5CLK,
113 PRCMU_PER6CLK,
114 PRCMU_PER7CLK,
115 PRCMU_LCDCLK,
116 PRCMU_BMLCLK,
117 PRCMU_HSITXCLK,
118 PRCMU_HSIRXCLK,
119 PRCMU_HDMICLK,
120 PRCMU_APEATCLK,
121 PRCMU_APETRACECLK,
122 PRCMU_MCDECLK,
123 PRCMU_IPI2CCLK,
124 PRCMU_DSIALTCLK,
125 PRCMU_DMACLK,
126 PRCMU_B2R2CLK,
127 PRCMU_TVCLK,
128 PRCMU_SSPCLK,
129 PRCMU_RNGCLK,
130 PRCMU_UICCCLK,
131 PRCMU_PWMCLK,
132 PRCMU_IRDACLK,
133 PRCMU_IRRCCLK,
134 PRCMU_SIACLK,
135 PRCMU_SVACLK,
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100136 PRCMU_ACLK,
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200137 PRCMU_NUM_REG_CLOCKS,
138 PRCMU_SYSCLK = PRCMU_NUM_REG_CLOCKS,
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100139 PRCMU_CDCLK,
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200140 PRCMU_TIMCLK,
141 PRCMU_PLLSOC0,
142 PRCMU_PLLSOC1,
Michel Jaouen20aee5b2012-08-31 14:21:30 +0200143 PRCMU_ARMSS,
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200144 PRCMU_PLLDDR,
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100145 PRCMU_PLLDSI,
146 PRCMU_DSI0CLK,
147 PRCMU_DSI1CLK,
148 PRCMU_DSI0ESCCLK,
149 PRCMU_DSI1ESCCLK,
150 PRCMU_DSI2ESCCLK,
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200151};
152
153/**
154 * enum ape_opp - APE OPP states definition
155 * @APE_OPP_INIT:
156 * @APE_NO_CHANGE: The APE operating point is unchanged
157 * @APE_100_OPP: The new APE operating point is ape100opp
158 * @APE_50_OPP: 50%
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100159 * @APE_50_PARTLY_25_OPP: 50%, except some clocks at 25%.
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200160 */
161enum ape_opp {
162 APE_OPP_INIT = 0x00,
163 APE_NO_CHANGE = 0x01,
164 APE_100_OPP = 0x02,
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100165 APE_50_OPP = 0x03,
166 APE_50_PARTLY_25_OPP = 0xFF,
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200167};
168
169/**
170 * enum arm_opp - ARM OPP states definition
171 * @ARM_OPP_INIT:
172 * @ARM_NO_CHANGE: The ARM operating point is unchanged
173 * @ARM_100_OPP: The new ARM operating point is arm100opp
174 * @ARM_50_OPP: The new ARM operating point is arm50opp
175 * @ARM_MAX_OPP: Operating point is "max" (more than 100)
176 * @ARM_MAX_FREQ100OPP: Set max opp if available, else 100
177 * @ARM_EXTCLK: The new ARM operating point is armExtClk
178 */
179enum arm_opp {
180 ARM_OPP_INIT = 0x00,
181 ARM_NO_CHANGE = 0x01,
182 ARM_100_OPP = 0x02,
183 ARM_50_OPP = 0x03,
184 ARM_MAX_OPP = 0x04,
185 ARM_MAX_FREQ100OPP = 0x05,
186 ARM_EXTCLK = 0x07
187};
188
189/**
190 * enum ddr_opp - DDR OPP states definition
191 * @DDR_100_OPP: The new DDR operating point is ddr100opp
192 * @DDR_50_OPP: The new DDR operating point is ddr50opp
193 * @DDR_25_OPP: The new DDR operating point is ddr25opp
194 */
195enum ddr_opp {
196 DDR_100_OPP = 0x00,
197 DDR_50_OPP = 0x01,
198 DDR_25_OPP = 0x02,
199};
200
201/*
202 * Definitions for controlling ESRAM0 in deep sleep.
203 */
204#define ESRAM0_DEEP_SLEEP_STATE_OFF 1
205#define ESRAM0_DEEP_SLEEP_STATE_RET 2
206
207/**
208 * enum ddr_pwrst - DDR power states definition
209 * @DDR_PWR_STATE_UNCHANGED: SDRAM and DDR controller state is unchanged
210 * @DDR_PWR_STATE_ON:
211 * @DDR_PWR_STATE_OFFLOWLAT:
212 * @DDR_PWR_STATE_OFFHIGHLAT:
213 */
214enum ddr_pwrst {
215 DDR_PWR_STATE_UNCHANGED = 0x00,
216 DDR_PWR_STATE_ON = 0x01,
217 DDR_PWR_STATE_OFFLOWLAT = 0x02,
218 DDR_PWR_STATE_OFFHIGHLAT = 0x03
219};
220
Linus Walleij05ec2602013-02-07 10:17:31 +0100221#define DB8500_PRCMU_LEGACY_OFFSET 0xDD4
222
223struct prcmu_pdata
224{
225 bool enable_set_ddr_opp;
226 bool enable_ape_opp_100_voltage;
227 struct ab8500_platform_data *ab_platdata;
228 u32 version_offset;
229 u32 legacy_offset;
230 u32 adt_offset;
231};
232
233#define PRCMU_FW_PROJECT_U8500 2
234#define PRCMU_FW_PROJECT_U8400 3
235#define PRCMU_FW_PROJECT_U9500 4 /* Customer specific */
236#define PRCMU_FW_PROJECT_U8500_MBB 5
237#define PRCMU_FW_PROJECT_U8500_C1 6
238#define PRCMU_FW_PROJECT_U8500_C2 7
239#define PRCMU_FW_PROJECT_U8500_C3 8
240#define PRCMU_FW_PROJECT_U8500_C4 9
241#define PRCMU_FW_PROJECT_U9500_MBL 10
242#define PRCMU_FW_PROJECT_U8500_MBL 11 /* Customer specific */
243#define PRCMU_FW_PROJECT_U8500_MBL2 12 /* Customer specific */
244#define PRCMU_FW_PROJECT_U8520 13
245#define PRCMU_FW_PROJECT_U8420 14
246#define PRCMU_FW_PROJECT_A9420 20
247/* [32..63] 9540 and derivatives */
248#define PRCMU_FW_PROJECT_U9540 32
249/* [64..95] 8540 and derivatives */
250#define PRCMU_FW_PROJECT_L8540 64
251/* [96..126] 8580 and derivatives */
252#define PRCMU_FW_PROJECT_L8580 96
253
254#define PRCMU_FW_PROJECT_NAME_LEN 20
255struct prcmu_fw_version {
256 u32 project; /* Notice, project shifted with 8 on ux540 */
257 u8 api_version;
258 u8 func_version;
259 u8 errata;
260 char project_name[PRCMU_FW_PROJECT_NAME_LEN];
261};
262
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200263#include <linux/mfd/db8500-prcmu.h>
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200264
Linus Walleijdece3702012-04-13 14:01:39 +0200265#if defined(CONFIG_UX500_SOC_DB8500)
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200266
267static inline void __init prcmu_early_init(void)
268{
Linus Walleijdece3702012-04-13 14:01:39 +0200269 return db8500_prcmu_early_init();
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200270}
271
272static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
273 bool keep_ap_pll)
274{
Linus Walleijdece3702012-04-13 14:01:39 +0200275 return db8500_prcmu_set_power_state(state, keep_ulp_clk,
276 keep_ap_pll);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200277}
278
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100279static inline u8 prcmu_get_power_state_result(void)
280{
Linus Walleijdece3702012-04-13 14:01:39 +0200281 return db8500_prcmu_get_power_state_result();
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100282}
283
Daniel Lezcano485540d2012-02-20 12:30:26 +0100284static inline int prcmu_gic_decouple(void)
285{
Linus Walleijdece3702012-04-13 14:01:39 +0200286 return db8500_prcmu_gic_decouple();
Daniel Lezcano485540d2012-02-20 12:30:26 +0100287}
288
289static inline int prcmu_gic_recouple(void)
290{
Linus Walleijdece3702012-04-13 14:01:39 +0200291 return db8500_prcmu_gic_recouple();
Daniel Lezcano485540d2012-02-20 12:30:26 +0100292}
293
Daniel Lezcanocc9a0f62012-02-28 22:46:06 +0100294static inline bool prcmu_gic_pending_irq(void)
295{
Linus Walleijdece3702012-04-13 14:01:39 +0200296 return db8500_prcmu_gic_pending_irq();
Daniel Lezcanocc9a0f62012-02-28 22:46:06 +0100297}
298
Daniel Lezcano34fe6f12012-02-28 22:46:09 +0100299static inline bool prcmu_is_cpu_in_wfi(int cpu)
300{
Linus Walleijdece3702012-04-13 14:01:39 +0200301 return db8500_prcmu_is_cpu_in_wfi(cpu);
Daniel Lezcano34fe6f12012-02-28 22:46:09 +0100302}
303
Daniel Lezcano9f60d332012-02-28 22:46:07 +0100304static inline int prcmu_copy_gic_settings(void)
305{
Linus Walleijdece3702012-04-13 14:01:39 +0200306 return db8500_prcmu_copy_gic_settings();
Daniel Lezcano9f60d332012-02-28 22:46:07 +0100307}
308
Daniel Lezcano9ab492e2012-02-28 22:46:08 +0100309static inline bool prcmu_pending_irq(void)
310{
Linus Walleijdece3702012-04-13 14:01:39 +0200311 return db8500_prcmu_pending_irq();
Daniel Lezcano9ab492e2012-02-28 22:46:08 +0100312}
313
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200314static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
315{
Linus Walleijdece3702012-04-13 14:01:39 +0200316 return db8500_prcmu_set_epod(epod_id, epod_state);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200317}
318
319static inline void prcmu_enable_wakeups(u32 wakeups)
320{
Linus Walleijdece3702012-04-13 14:01:39 +0200321 db8500_prcmu_enable_wakeups(wakeups);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200322}
323
324static inline void prcmu_disable_wakeups(void)
325{
326 prcmu_enable_wakeups(0);
327}
328
329static inline void prcmu_config_abb_event_readout(u32 abb_events)
330{
Linus Walleijdece3702012-04-13 14:01:39 +0200331 db8500_prcmu_config_abb_event_readout(abb_events);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200332}
333
334static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
335{
Linus Walleijdece3702012-04-13 14:01:39 +0200336 db8500_prcmu_get_abb_event_buffer(buf);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200337}
338
339int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size);
340int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size);
Mattias Nilsson3c3e4892012-03-08 14:02:05 +0100341int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask, u8 size);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200342
343int prcmu_config_clkout(u8 clkout, u8 source, u8 div);
344
345static inline int prcmu_request_clock(u8 clock, bool enable)
346{
Linus Walleijdece3702012-04-13 14:01:39 +0200347 return db8500_prcmu_request_clock(clock, enable);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200348}
349
Mattias Nilsson05089012012-01-13 16:20:20 +0100350unsigned long prcmu_clock_rate(u8 clock);
351long prcmu_round_clock_rate(u8 clock, unsigned long rate);
352int prcmu_set_clock_rate(u8 clock, unsigned long rate);
353
354static inline int prcmu_set_ddr_opp(u8 opp)
355{
Linus Walleijdece3702012-04-13 14:01:39 +0200356 return db8500_prcmu_set_ddr_opp(opp);
Mattias Nilsson05089012012-01-13 16:20:20 +0100357}
358static inline int prcmu_get_ddr_opp(void)
359{
Linus Walleijdece3702012-04-13 14:01:39 +0200360 return db8500_prcmu_get_ddr_opp();
Mattias Nilsson05089012012-01-13 16:20:20 +0100361}
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200362
363static inline int prcmu_set_arm_opp(u8 opp)
364{
Linus Walleijdece3702012-04-13 14:01:39 +0200365 return db8500_prcmu_set_arm_opp(opp);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200366}
367
368static inline int prcmu_get_arm_opp(void)
369{
Linus Walleijdece3702012-04-13 14:01:39 +0200370 return db8500_prcmu_get_arm_opp();
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200371}
372
Mattias Nilsson05089012012-01-13 16:20:20 +0100373static inline int prcmu_set_ape_opp(u8 opp)
374{
Linus Walleijdece3702012-04-13 14:01:39 +0200375 return db8500_prcmu_set_ape_opp(opp);
Mattias Nilsson05089012012-01-13 16:20:20 +0100376}
377
378static inline int prcmu_get_ape_opp(void)
379{
Linus Walleijdece3702012-04-13 14:01:39 +0200380 return db8500_prcmu_get_ape_opp();
Mattias Nilsson05089012012-01-13 16:20:20 +0100381}
382
Ulf Hansson686f8712012-09-24 16:43:17 +0200383static inline int prcmu_request_ape_opp_100_voltage(bool enable)
384{
385 return db8500_prcmu_request_ape_opp_100_voltage(enable);
386}
387
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200388static inline void prcmu_system_reset(u16 reset_code)
389{
Linus Walleijdece3702012-04-13 14:01:39 +0200390 return db8500_prcmu_system_reset(reset_code);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200391}
392
393static inline u16 prcmu_get_reset_code(void)
394{
Linus Walleijdece3702012-04-13 14:01:39 +0200395 return db8500_prcmu_get_reset_code();
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200396}
397
Arun Murthy5261e102012-05-21 14:28:21 +0530398int prcmu_ac_wake_req(void);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200399void prcmu_ac_sleep_req(void);
Mattias Nilsson05089012012-01-13 16:20:20 +0100400static inline void prcmu_modem_reset(void)
401{
Linus Walleijdece3702012-04-13 14:01:39 +0200402 return db8500_prcmu_modem_reset();
Mattias Nilsson05089012012-01-13 16:20:20 +0100403}
404
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200405static inline bool prcmu_is_ac_wake_requested(void)
406{
Linus Walleijdece3702012-04-13 14:01:39 +0200407 return db8500_prcmu_is_ac_wake_requested();
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200408}
409
410static inline int prcmu_set_display_clocks(void)
411{
Linus Walleijdece3702012-04-13 14:01:39 +0200412 return db8500_prcmu_set_display_clocks();
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200413}
414
415static inline int prcmu_disable_dsipll(void)
416{
Linus Walleijdece3702012-04-13 14:01:39 +0200417 return db8500_prcmu_disable_dsipll();
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200418}
419
420static inline int prcmu_enable_dsipll(void)
421{
Linus Walleijdece3702012-04-13 14:01:39 +0200422 return db8500_prcmu_enable_dsipll();
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200423}
424
425static inline int prcmu_config_esram0_deep_sleep(u8 state)
426{
Linus Walleijdece3702012-04-13 14:01:39 +0200427 return db8500_prcmu_config_esram0_deep_sleep(state);
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200428}
Mattias Nilsson05089012012-01-13 16:20:20 +0100429
430static inline int prcmu_config_hotdog(u8 threshold)
431{
Linus Walleijdece3702012-04-13 14:01:39 +0200432 return db8500_prcmu_config_hotdog(threshold);
Mattias Nilsson05089012012-01-13 16:20:20 +0100433}
434
435static inline int prcmu_config_hotmon(u8 low, u8 high)
436{
Linus Walleijdece3702012-04-13 14:01:39 +0200437 return db8500_prcmu_config_hotmon(low, high);
Mattias Nilsson05089012012-01-13 16:20:20 +0100438}
439
440static inline int prcmu_start_temp_sense(u16 cycles32k)
441{
Linus Walleijdece3702012-04-13 14:01:39 +0200442 return db8500_prcmu_start_temp_sense(cycles32k);
Mattias Nilsson05089012012-01-13 16:20:20 +0100443}
444
445static inline int prcmu_stop_temp_sense(void)
446{
Linus Walleijdece3702012-04-13 14:01:39 +0200447 return db8500_prcmu_stop_temp_sense();
Mattias Nilsson05089012012-01-13 16:20:20 +0100448}
449
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100450static inline u32 prcmu_read(unsigned int reg)
451{
Linus Walleijdece3702012-04-13 14:01:39 +0200452 return db8500_prcmu_read(reg);
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100453}
454
455static inline void prcmu_write(unsigned int reg, u32 value)
456{
Linus Walleijdece3702012-04-13 14:01:39 +0200457 db8500_prcmu_write(reg, value);
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100458}
459
460static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value)
461{
Linus Walleijdece3702012-04-13 14:01:39 +0200462 db8500_prcmu_write_masked(reg, mask, value);
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100463}
464
Mattias Nilsson05089012012-01-13 16:20:20 +0100465static inline int prcmu_enable_a9wdog(u8 id)
466{
Linus Walleijdece3702012-04-13 14:01:39 +0200467 return db8500_prcmu_enable_a9wdog(id);
Mattias Nilsson05089012012-01-13 16:20:20 +0100468}
469
470static inline int prcmu_disable_a9wdog(u8 id)
471{
Linus Walleijdece3702012-04-13 14:01:39 +0200472 return db8500_prcmu_disable_a9wdog(id);
Mattias Nilsson05089012012-01-13 16:20:20 +0100473}
474
475static inline int prcmu_kick_a9wdog(u8 id)
476{
Linus Walleijdece3702012-04-13 14:01:39 +0200477 return db8500_prcmu_kick_a9wdog(id);
Mattias Nilsson05089012012-01-13 16:20:20 +0100478}
479
480static inline int prcmu_load_a9wdog(u8 id, u32 timeout)
481{
Linus Walleijdece3702012-04-13 14:01:39 +0200482 return db8500_prcmu_load_a9wdog(id, timeout);
Mattias Nilsson05089012012-01-13 16:20:20 +0100483}
484
485static inline int prcmu_config_a9wdog(u8 num, bool sleep_auto_off)
486{
Linus Walleijdece3702012-04-13 14:01:39 +0200487 return db8500_prcmu_config_a9wdog(num, sleep_auto_off);
Mattias Nilsson05089012012-01-13 16:20:20 +0100488}
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200489#else
490
491static inline void __init prcmu_early_init(void) {}
492
493static inline int prcmu_set_power_state(u8 state, bool keep_ulp_clk,
494 bool keep_ap_pll)
495{
496 return 0;
497}
498
499static inline int prcmu_set_epod(u16 epod_id, u8 epod_state)
500{
501 return 0;
502}
503
504static inline void prcmu_enable_wakeups(u32 wakeups) {}
505
506static inline void prcmu_disable_wakeups(void) {}
507
508static inline int prcmu_abb_read(u8 slave, u8 reg, u8 *value, u8 size)
509{
510 return -ENOSYS;
511}
512
513static inline int prcmu_abb_write(u8 slave, u8 reg, u8 *value, u8 size)
514{
515 return -ENOSYS;
516}
517
Mattias Nilsson3c3e4892012-03-08 14:02:05 +0100518static inline int prcmu_abb_write_masked(u8 slave, u8 reg, u8 *value, u8 *mask,
519 u8 size)
520{
521 return -ENOSYS;
522}
523
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200524static inline int prcmu_config_clkout(u8 clkout, u8 source, u8 div)
525{
526 return 0;
527}
528
529static inline int prcmu_request_clock(u8 clock, bool enable)
530{
531 return 0;
532}
533
Mattias Nilsson6b6fae22012-01-13 16:20:28 +0100534static inline long prcmu_round_clock_rate(u8 clock, unsigned long rate)
535{
536 return 0;
537}
538
539static inline int prcmu_set_clock_rate(u8 clock, unsigned long rate)
540{
541 return 0;
542}
543
544static inline unsigned long prcmu_clock_rate(u8 clock)
545{
546 return 0;
547}
548
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200549static inline int prcmu_set_ape_opp(u8 opp)
550{
551 return 0;
552}
553
554static inline int prcmu_get_ape_opp(void)
555{
556 return APE_100_OPP;
557}
558
Ulf Hansson686f8712012-09-24 16:43:17 +0200559static inline int prcmu_request_ape_opp_100_voltage(bool enable)
560{
561 return 0;
562}
563
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200564static inline int prcmu_set_arm_opp(u8 opp)
565{
566 return 0;
567}
568
569static inline int prcmu_get_arm_opp(void)
570{
571 return ARM_100_OPP;
572}
573
574static inline int prcmu_set_ddr_opp(u8 opp)
575{
576 return 0;
577}
578
579static inline int prcmu_get_ddr_opp(void)
580{
581 return DDR_100_OPP;
582}
583
584static inline void prcmu_system_reset(u16 reset_code) {}
585
586static inline u16 prcmu_get_reset_code(void)
587{
588 return 0;
589}
590
Arun Murthy5261e102012-05-21 14:28:21 +0530591static inline int prcmu_ac_wake_req(void)
592{
593 return 0;
594}
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200595
596static inline void prcmu_ac_sleep_req(void) {}
597
598static inline void prcmu_modem_reset(void) {}
599
600static inline bool prcmu_is_ac_wake_requested(void)
601{
602 return false;
603}
604
605static inline int prcmu_set_display_clocks(void)
606{
607 return 0;
608}
609
610static inline int prcmu_disable_dsipll(void)
611{
612 return 0;
613}
614
615static inline int prcmu_enable_dsipll(void)
616{
617 return 0;
618}
619
620static inline int prcmu_config_esram0_deep_sleep(u8 state)
621{
622 return 0;
623}
624
625static inline void prcmu_config_abb_event_readout(u32 abb_events) {}
626
627static inline void prcmu_get_abb_event_buffer(void __iomem **buf)
628{
629 *buf = NULL;
630}
631
Mattias Nilsson05089012012-01-13 16:20:20 +0100632static inline int prcmu_config_hotdog(u8 threshold)
633{
634 return 0;
635}
636
637static inline int prcmu_config_hotmon(u8 low, u8 high)
638{
639 return 0;
640}
641
642static inline int prcmu_start_temp_sense(u16 cycles32k)
643{
644 return 0;
645}
646
647static inline int prcmu_stop_temp_sense(void)
648{
649 return 0;
650}
651
Mattias Nilssonb4a6dbd2012-01-13 16:21:00 +0100652static inline u32 prcmu_read(unsigned int reg)
653{
654 return 0;
655}
656
657static inline void prcmu_write(unsigned int reg, u32 value) {}
658
659static inline void prcmu_write_masked(unsigned int reg, u32 mask, u32 value) {}
660
661#endif
662
663static inline void prcmu_set(unsigned int reg, u32 bits)
664{
665 prcmu_write_masked(reg, bits, bits);
666}
667
668static inline void prcmu_clear(unsigned int reg, u32 bits)
669{
670 prcmu_write_masked(reg, bits, 0);
671}
672
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200673/* PRCMU QoS APE OPP class */
674#define PRCMU_QOS_APE_OPP 1
675#define PRCMU_QOS_DDR_OPP 2
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100676#define PRCMU_QOS_ARM_OPP 3
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200677#define PRCMU_QOS_DEFAULT_VALUE -1
678
Mattias Nilsson4d64d2e2012-01-13 16:20:43 +0100679#ifdef CONFIG_DBX500_PRCMU_QOS_POWER
Mattias Nilssonfea799e2011-08-12 10:28:02 +0200680
681unsigned long prcmu_qos_get_cpufreq_opp_delay(void);
682void prcmu_qos_set_cpufreq_opp_delay(unsigned long);
683void prcmu_qos_force_opp(int, s32);
684int prcmu_qos_requirement(int pm_qos_class);
685int prcmu_qos_add_requirement(int pm_qos_class, char *name, s32 value);
686int prcmu_qos_update_requirement(int pm_qos_class, char *name, s32 new_value);
687void prcmu_qos_remove_requirement(int pm_qos_class, char *name);
688int prcmu_qos_add_notifier(int prcmu_qos_class,
689 struct notifier_block *notifier);
690int prcmu_qos_remove_notifier(int prcmu_qos_class,
691 struct notifier_block *notifier);
692
693#else
694
695static inline unsigned long prcmu_qos_get_cpufreq_opp_delay(void)
696{
697 return 0;
698}
699
700static inline void prcmu_qos_set_cpufreq_opp_delay(unsigned long n) {}
701
702static inline void prcmu_qos_force_opp(int prcmu_qos_class, s32 i) {}
703
704static inline int prcmu_qos_requirement(int prcmu_qos_class)
705{
706 return 0;
707}
708
709static inline int prcmu_qos_add_requirement(int prcmu_qos_class,
710 char *name, s32 value)
711{
712 return 0;
713}
714
715static inline int prcmu_qos_update_requirement(int prcmu_qos_class,
716 char *name, s32 new_value)
717{
718 return 0;
719}
720
721static inline void prcmu_qos_remove_requirement(int prcmu_qos_class, char *name)
722{
723}
724
725static inline int prcmu_qos_add_notifier(int prcmu_qos_class,
726 struct notifier_block *notifier)
727{
728 return 0;
729}
730static inline int prcmu_qos_remove_notifier(int prcmu_qos_class,
731 struct notifier_block *notifier)
732{
733 return 0;
734}
735
736#endif
737
738#endif /* __MACH_PRCMU_H */