Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 Texas Instruments |
| 3 | * Author: Rob Clark <robdclark@gmail.com> |
| 4 | * |
| 5 | * This program is free software; you can redistribute it and/or modify it |
| 6 | * under the terms of the GNU General Public License version 2 as published by |
| 7 | * the Free Software Foundation. |
| 8 | * |
| 9 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 10 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 11 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 12 | * more details. |
| 13 | * |
| 14 | * You should have received a copy of the GNU General Public License along with |
| 15 | * this program. If not, see <http://www.gnu.org/licenses/>. |
| 16 | */ |
| 17 | |
| 18 | |
| 19 | |
| 20 | #include <linux/module.h> |
| 21 | |
| 22 | #include <drm/drmP.h> |
| 23 | #include <drm/drm_crtc_helper.h> |
| 24 | #include <drm/drm_encoder_slave.h> |
| 25 | #include <drm/drm_edid.h> |
| 26 | |
| 27 | |
| 28 | #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) |
| 29 | |
| 30 | struct tda998x_priv { |
| 31 | struct i2c_client *cec; |
| 32 | uint16_t rev; |
| 33 | uint8_t current_page; |
| 34 | int dpms; |
| 35 | }; |
| 36 | |
| 37 | #define to_tda998x_priv(x) ((struct tda998x_priv *)to_encoder_slave(x)->slave_priv) |
| 38 | |
| 39 | /* The TDA9988 series of devices use a paged register scheme.. to simplify |
| 40 | * things we encode the page # in upper bits of the register #. To read/ |
| 41 | * write a given register, we need to make sure CURPAGE register is set |
| 42 | * appropriately. Which implies reads/writes are not atomic. Fun! |
| 43 | */ |
| 44 | |
| 45 | #define REG(page, addr) (((page) << 8) | (addr)) |
| 46 | #define REG2ADDR(reg) ((reg) & 0xff) |
| 47 | #define REG2PAGE(reg) (((reg) >> 8) & 0xff) |
| 48 | |
| 49 | #define REG_CURPAGE 0xff /* write */ |
| 50 | |
| 51 | |
| 52 | /* Page 00h: General Control */ |
| 53 | #define REG_VERSION_LSB REG(0x00, 0x00) /* read */ |
| 54 | #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ |
| 55 | # define MAIN_CNTRL0_SR (1 << 0) |
| 56 | # define MAIN_CNTRL0_DECS (1 << 1) |
| 57 | # define MAIN_CNTRL0_DEHS (1 << 2) |
| 58 | # define MAIN_CNTRL0_CECS (1 << 3) |
| 59 | # define MAIN_CNTRL0_CEHS (1 << 4) |
| 60 | # define MAIN_CNTRL0_SCALER (1 << 7) |
| 61 | #define REG_VERSION_MSB REG(0x00, 0x02) /* read */ |
| 62 | #define REG_SOFTRESET REG(0x00, 0x0a) /* write */ |
| 63 | # define SOFTRESET_AUDIO (1 << 0) |
| 64 | # define SOFTRESET_I2C_MASTER (1 << 1) |
| 65 | #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ |
| 66 | #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ |
| 67 | #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ |
| 68 | # define I2C_MASTER_DIS_MM (1 << 0) |
| 69 | # define I2C_MASTER_DIS_FILT (1 << 1) |
| 70 | # define I2C_MASTER_APP_STRT_LAT (1 << 2) |
| 71 | #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ |
| 72 | #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ |
| 73 | #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ |
| 74 | # define INT_FLAGS_2_EDID_BLK_RD (1 << 1) |
| 75 | #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ |
| 76 | #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ |
| 77 | #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ |
| 78 | #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ |
| 79 | #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ |
| 80 | # define VIP_CNTRL_0_MIRR_A (1 << 7) |
| 81 | # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) |
| 82 | # define VIP_CNTRL_0_MIRR_B (1 << 3) |
| 83 | # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) |
| 84 | #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ |
| 85 | # define VIP_CNTRL_1_MIRR_C (1 << 7) |
| 86 | # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) |
| 87 | # define VIP_CNTRL_1_MIRR_D (1 << 3) |
| 88 | # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) |
| 89 | #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ |
| 90 | # define VIP_CNTRL_2_MIRR_E (1 << 7) |
| 91 | # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) |
| 92 | # define VIP_CNTRL_2_MIRR_F (1 << 3) |
| 93 | # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) |
| 94 | #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ |
| 95 | # define VIP_CNTRL_3_X_TGL (1 << 0) |
| 96 | # define VIP_CNTRL_3_H_TGL (1 << 1) |
| 97 | # define VIP_CNTRL_3_V_TGL (1 << 2) |
| 98 | # define VIP_CNTRL_3_EMB (1 << 3) |
| 99 | # define VIP_CNTRL_3_SYNC_DE (1 << 4) |
| 100 | # define VIP_CNTRL_3_SYNC_HS (1 << 5) |
| 101 | # define VIP_CNTRL_3_DE_INT (1 << 6) |
| 102 | # define VIP_CNTRL_3_EDGE (1 << 7) |
| 103 | #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ |
| 104 | # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) |
| 105 | # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) |
| 106 | # define VIP_CNTRL_4_CCIR656 (1 << 4) |
| 107 | # define VIP_CNTRL_4_656_ALT (1 << 5) |
| 108 | # define VIP_CNTRL_4_TST_656 (1 << 6) |
| 109 | # define VIP_CNTRL_4_TST_PAT (1 << 7) |
| 110 | #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ |
| 111 | # define VIP_CNTRL_5_CKCASE (1 << 0) |
| 112 | # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) |
| 113 | #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ |
| 114 | # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) |
| 115 | # define MAT_CONTRL_MAT_BP (1 << 2) |
| 116 | #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ |
| 117 | #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ |
| 118 | #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ |
| 119 | #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ |
| 120 | #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ |
| 121 | #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ |
| 122 | #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ |
| 123 | #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ |
| 124 | #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ |
| 125 | #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ |
| 126 | #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ |
| 127 | #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ |
| 128 | #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ |
| 129 | #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ |
| 130 | #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ |
| 131 | #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ |
| 132 | #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ |
| 133 | #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ |
| 134 | #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ |
| 135 | #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ |
| 136 | #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ |
| 137 | #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ |
| 138 | #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ |
| 139 | #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ |
| 140 | #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ |
| 141 | #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ |
| 142 | #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ |
| 143 | #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ |
| 144 | #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ |
| 145 | #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ |
| 146 | #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ |
| 147 | #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ |
| 148 | #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ |
| 149 | #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ |
| 150 | # define TBG_CNTRL_0_FRAME_DIS (1 << 5) |
| 151 | # define TBG_CNTRL_0_SYNC_MTHD (1 << 6) |
| 152 | # define TBG_CNTRL_0_SYNC_ONCE (1 << 7) |
| 153 | #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ |
| 154 | # define TBG_CNTRL_1_VH_TGL_0 (1 << 0) |
| 155 | # define TBG_CNTRL_1_VH_TGL_1 (1 << 1) |
| 156 | # define TBG_CNTRL_1_VH_TGL_2 (1 << 2) |
| 157 | # define TBG_CNTRL_1_VHX_EXT_DE (1 << 3) |
| 158 | # define TBG_CNTRL_1_VHX_EXT_HS (1 << 4) |
| 159 | # define TBG_CNTRL_1_VHX_EXT_VS (1 << 5) |
| 160 | # define TBG_CNTRL_1_DWIN_DIS (1 << 6) |
| 161 | #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ |
| 162 | #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ |
| 163 | # define HVF_CNTRL_0_SM (1 << 7) |
| 164 | # define HVF_CNTRL_0_RWB (1 << 6) |
| 165 | # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) |
| 166 | # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) |
| 167 | #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ |
| 168 | # define HVF_CNTRL_1_FOR (1 << 0) |
| 169 | # define HVF_CNTRL_1_YUVBLK (1 << 1) |
| 170 | # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) |
| 171 | # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) |
| 172 | # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) |
| 173 | #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ |
| 174 | |
| 175 | |
| 176 | /* Page 02h: PLL settings */ |
| 177 | #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ |
| 178 | # define PLL_SERIAL_1_SRL_FDN (1 << 0) |
| 179 | # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) |
| 180 | # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) |
| 181 | #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ |
| 182 | # define PLL_SERIAL_2_SRL_NOSC(x) (((x) & 3) << 0) |
| 183 | # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) |
| 184 | #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ |
| 185 | # define PLL_SERIAL_3_SRL_CCIR (1 << 0) |
| 186 | # define PLL_SERIAL_3_SRL_DE (1 << 2) |
| 187 | # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) |
| 188 | #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ |
| 189 | #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ |
| 190 | #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ |
| 191 | #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ |
| 192 | #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ |
| 193 | #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ |
| 194 | #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ |
| 195 | #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ |
| 196 | #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ |
| 197 | #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ |
| 198 | # define SEL_CLK_SEL_CLK1 (1 << 0) |
| 199 | # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) |
| 200 | # define SEL_CLK_ENA_SC_CLK (1 << 3) |
| 201 | #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ |
| 202 | |
| 203 | |
| 204 | /* Page 09h: EDID Control */ |
| 205 | #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ |
| 206 | /* next 127 successive registers are the EDID block */ |
| 207 | #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ |
| 208 | #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ |
| 209 | #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ |
| 210 | #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ |
| 211 | #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ |
| 212 | |
| 213 | |
| 214 | /* Page 10h: information frames and packets */ |
| 215 | |
| 216 | |
| 217 | /* Page 11h: audio settings and content info packets */ |
| 218 | #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ |
| 219 | # define AIP_CNTRL_0_RST_FIFO (1 << 0) |
| 220 | # define AIP_CNTRL_0_SWAP (1 << 1) |
| 221 | # define AIP_CNTRL_0_LAYOUT (1 << 2) |
| 222 | # define AIP_CNTRL_0_ACR_MAN (1 << 5) |
| 223 | # define AIP_CNTRL_0_RST_CTS (1 << 6) |
| 224 | #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ |
| 225 | # define ENC_CNTRL_RST_ENC (1 << 0) |
| 226 | # define ENC_CNTRL_RST_SEL (1 << 1) |
| 227 | # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) |
| 228 | |
| 229 | |
| 230 | /* Page 12h: HDCP and OTP */ |
| 231 | #define REG_TX3 REG(0x12, 0x9a) /* read/write */ |
Russell King | 063b472 | 2013-08-14 21:43:26 +0200 | [diff] [blame^] | 232 | #define REG_TX4 REG(0x12, 0x9b) /* read/write */ |
| 233 | # define TX4_PD_RAM (1 << 1) |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 234 | #define REG_TX33 REG(0x12, 0xb8) /* read/write */ |
| 235 | # define TX33_HDMI (1 << 1) |
| 236 | |
| 237 | |
| 238 | /* Page 13h: Gamut related metadata packets */ |
| 239 | |
| 240 | |
| 241 | |
| 242 | /* CEC registers: (not paged) |
| 243 | */ |
| 244 | #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ |
| 245 | # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) |
| 246 | # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) |
| 247 | # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) |
| 248 | # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) |
| 249 | #define REG_CEC_RXSHPDLEV 0xfe /* read */ |
| 250 | # define CEC_RXSHPDLEV_RXSENS (1 << 0) |
| 251 | # define CEC_RXSHPDLEV_HPD (1 << 1) |
| 252 | |
| 253 | #define REG_CEC_ENAMODS 0xff /* read/write */ |
| 254 | # define CEC_ENAMODS_DIS_FRO (1 << 6) |
| 255 | # define CEC_ENAMODS_DIS_CCLK (1 << 5) |
| 256 | # define CEC_ENAMODS_EN_RXSENS (1 << 2) |
| 257 | # define CEC_ENAMODS_EN_HDMI (1 << 1) |
| 258 | # define CEC_ENAMODS_EN_CEC (1 << 0) |
| 259 | |
| 260 | |
| 261 | /* Device versions: */ |
| 262 | #define TDA9989N2 0x0101 |
| 263 | #define TDA19989 0x0201 |
| 264 | #define TDA19989N2 0x0202 |
| 265 | #define TDA19988 0x0301 |
| 266 | |
| 267 | static void |
| 268 | cec_write(struct drm_encoder *encoder, uint16_t addr, uint8_t val) |
| 269 | { |
| 270 | struct i2c_client *client = to_tda998x_priv(encoder)->cec; |
| 271 | uint8_t buf[] = {addr, val}; |
| 272 | int ret; |
| 273 | |
| 274 | ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); |
| 275 | if (ret < 0) |
| 276 | dev_err(&client->dev, "Error %d writing to cec:0x%x\n", ret, addr); |
| 277 | } |
| 278 | |
| 279 | static uint8_t |
| 280 | cec_read(struct drm_encoder *encoder, uint8_t addr) |
| 281 | { |
| 282 | struct i2c_client *client = to_tda998x_priv(encoder)->cec; |
| 283 | uint8_t val; |
| 284 | int ret; |
| 285 | |
| 286 | ret = i2c_master_send(client, &addr, sizeof(addr)); |
| 287 | if (ret < 0) |
| 288 | goto fail; |
| 289 | |
| 290 | ret = i2c_master_recv(client, &val, sizeof(val)); |
| 291 | if (ret < 0) |
| 292 | goto fail; |
| 293 | |
| 294 | return val; |
| 295 | |
| 296 | fail: |
| 297 | dev_err(&client->dev, "Error %d reading from cec:0x%x\n", ret, addr); |
| 298 | return 0; |
| 299 | } |
| 300 | |
| 301 | static void |
| 302 | set_page(struct drm_encoder *encoder, uint16_t reg) |
| 303 | { |
| 304 | struct tda998x_priv *priv = to_tda998x_priv(encoder); |
| 305 | |
| 306 | if (REG2PAGE(reg) != priv->current_page) { |
| 307 | struct i2c_client *client = drm_i2c_encoder_get_client(encoder); |
| 308 | uint8_t buf[] = { |
| 309 | REG_CURPAGE, REG2PAGE(reg) |
| 310 | }; |
| 311 | int ret = i2c_master_send(client, buf, sizeof(buf)); |
| 312 | if (ret < 0) |
| 313 | dev_err(&client->dev, "Error %d writing to REG_CURPAGE\n", ret); |
| 314 | |
| 315 | priv->current_page = REG2PAGE(reg); |
| 316 | } |
| 317 | } |
| 318 | |
| 319 | static int |
| 320 | reg_read_range(struct drm_encoder *encoder, uint16_t reg, char *buf, int cnt) |
| 321 | { |
| 322 | struct i2c_client *client = drm_i2c_encoder_get_client(encoder); |
| 323 | uint8_t addr = REG2ADDR(reg); |
| 324 | int ret; |
| 325 | |
| 326 | set_page(encoder, reg); |
| 327 | |
| 328 | ret = i2c_master_send(client, &addr, sizeof(addr)); |
| 329 | if (ret < 0) |
| 330 | goto fail; |
| 331 | |
| 332 | ret = i2c_master_recv(client, buf, cnt); |
| 333 | if (ret < 0) |
| 334 | goto fail; |
| 335 | |
| 336 | return ret; |
| 337 | |
| 338 | fail: |
| 339 | dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); |
| 340 | return ret; |
| 341 | } |
| 342 | |
| 343 | static uint8_t |
| 344 | reg_read(struct drm_encoder *encoder, uint16_t reg) |
| 345 | { |
| 346 | uint8_t val = 0; |
| 347 | reg_read_range(encoder, reg, &val, sizeof(val)); |
| 348 | return val; |
| 349 | } |
| 350 | |
| 351 | static void |
| 352 | reg_write(struct drm_encoder *encoder, uint16_t reg, uint8_t val) |
| 353 | { |
| 354 | struct i2c_client *client = drm_i2c_encoder_get_client(encoder); |
| 355 | uint8_t buf[] = {REG2ADDR(reg), val}; |
| 356 | int ret; |
| 357 | |
| 358 | set_page(encoder, reg); |
| 359 | |
| 360 | ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); |
| 361 | if (ret < 0) |
| 362 | dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); |
| 363 | } |
| 364 | |
| 365 | static void |
| 366 | reg_write16(struct drm_encoder *encoder, uint16_t reg, uint16_t val) |
| 367 | { |
| 368 | struct i2c_client *client = drm_i2c_encoder_get_client(encoder); |
| 369 | uint8_t buf[] = {REG2ADDR(reg), val >> 8, val}; |
| 370 | int ret; |
| 371 | |
| 372 | set_page(encoder, reg); |
| 373 | |
| 374 | ret = i2c_master_send(client, buf, ARRAY_SIZE(buf)); |
| 375 | if (ret < 0) |
| 376 | dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); |
| 377 | } |
| 378 | |
| 379 | static void |
| 380 | reg_set(struct drm_encoder *encoder, uint16_t reg, uint8_t val) |
| 381 | { |
| 382 | reg_write(encoder, reg, reg_read(encoder, reg) | val); |
| 383 | } |
| 384 | |
| 385 | static void |
| 386 | reg_clear(struct drm_encoder *encoder, uint16_t reg, uint8_t val) |
| 387 | { |
| 388 | reg_write(encoder, reg, reg_read(encoder, reg) & ~val); |
| 389 | } |
| 390 | |
| 391 | static void |
| 392 | tda998x_reset(struct drm_encoder *encoder) |
| 393 | { |
| 394 | /* reset audio and i2c master: */ |
| 395 | reg_set(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); |
| 396 | msleep(50); |
| 397 | reg_clear(encoder, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); |
| 398 | msleep(50); |
| 399 | |
| 400 | /* reset transmitter: */ |
| 401 | reg_set(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); |
| 402 | reg_clear(encoder, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); |
| 403 | |
| 404 | /* PLL registers common configuration */ |
| 405 | reg_write(encoder, REG_PLL_SERIAL_1, 0x00); |
| 406 | reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); |
| 407 | reg_write(encoder, REG_PLL_SERIAL_3, 0x00); |
| 408 | reg_write(encoder, REG_SERIALIZER, 0x00); |
| 409 | reg_write(encoder, REG_BUFFER_OUT, 0x00); |
| 410 | reg_write(encoder, REG_PLL_SCG1, 0x00); |
| 411 | reg_write(encoder, REG_AUDIO_DIV, 0x03); |
| 412 | reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); |
| 413 | reg_write(encoder, REG_PLL_SCGN1, 0xfa); |
| 414 | reg_write(encoder, REG_PLL_SCGN2, 0x00); |
| 415 | reg_write(encoder, REG_PLL_SCGR1, 0x5b); |
| 416 | reg_write(encoder, REG_PLL_SCGR2, 0x00); |
| 417 | reg_write(encoder, REG_PLL_SCG2, 0x10); |
| 418 | } |
| 419 | |
| 420 | /* DRM encoder functions */ |
| 421 | |
| 422 | static void |
| 423 | tda998x_encoder_set_config(struct drm_encoder *encoder, void *params) |
| 424 | { |
| 425 | } |
| 426 | |
| 427 | static void |
| 428 | tda998x_encoder_dpms(struct drm_encoder *encoder, int mode) |
| 429 | { |
| 430 | struct tda998x_priv *priv = to_tda998x_priv(encoder); |
| 431 | |
| 432 | /* we only care about on or off: */ |
| 433 | if (mode != DRM_MODE_DPMS_ON) |
| 434 | mode = DRM_MODE_DPMS_OFF; |
| 435 | |
| 436 | if (mode == priv->dpms) |
| 437 | return; |
| 438 | |
| 439 | switch (mode) { |
| 440 | case DRM_MODE_DPMS_ON: |
| 441 | /* enable audio and video ports */ |
| 442 | reg_write(encoder, REG_ENA_AP, 0xff); |
| 443 | reg_write(encoder, REG_ENA_VP_0, 0xff); |
| 444 | reg_write(encoder, REG_ENA_VP_1, 0xff); |
| 445 | reg_write(encoder, REG_ENA_VP_2, 0xff); |
| 446 | /* set muxing after enabling ports: */ |
| 447 | reg_write(encoder, REG_VIP_CNTRL_0, |
| 448 | VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3)); |
| 449 | reg_write(encoder, REG_VIP_CNTRL_1, |
| 450 | VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1)); |
| 451 | reg_write(encoder, REG_VIP_CNTRL_2, |
| 452 | VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5)); |
| 453 | break; |
| 454 | case DRM_MODE_DPMS_OFF: |
| 455 | /* disable audio and video ports */ |
| 456 | reg_write(encoder, REG_ENA_AP, 0x00); |
| 457 | reg_write(encoder, REG_ENA_VP_0, 0x00); |
| 458 | reg_write(encoder, REG_ENA_VP_1, 0x00); |
| 459 | reg_write(encoder, REG_ENA_VP_2, 0x00); |
| 460 | break; |
| 461 | } |
| 462 | |
| 463 | priv->dpms = mode; |
| 464 | } |
| 465 | |
| 466 | static void |
| 467 | tda998x_encoder_save(struct drm_encoder *encoder) |
| 468 | { |
| 469 | DBG(""); |
| 470 | } |
| 471 | |
| 472 | static void |
| 473 | tda998x_encoder_restore(struct drm_encoder *encoder) |
| 474 | { |
| 475 | DBG(""); |
| 476 | } |
| 477 | |
| 478 | static bool |
| 479 | tda998x_encoder_mode_fixup(struct drm_encoder *encoder, |
| 480 | const struct drm_display_mode *mode, |
| 481 | struct drm_display_mode *adjusted_mode) |
| 482 | { |
| 483 | return true; |
| 484 | } |
| 485 | |
| 486 | static int |
| 487 | tda998x_encoder_mode_valid(struct drm_encoder *encoder, |
| 488 | struct drm_display_mode *mode) |
| 489 | { |
| 490 | return MODE_OK; |
| 491 | } |
| 492 | |
| 493 | static void |
| 494 | tda998x_encoder_mode_set(struct drm_encoder *encoder, |
| 495 | struct drm_display_mode *mode, |
| 496 | struct drm_display_mode *adjusted_mode) |
| 497 | { |
| 498 | struct tda998x_priv *priv = to_tda998x_priv(encoder); |
| 499 | uint16_t hs_start, hs_end, line_start, line_end; |
| 500 | uint16_t vwin_start, vwin_end, de_start, de_end; |
| 501 | uint16_t ref_pix, ref_line, pix_start2; |
| 502 | uint8_t reg, div, rep; |
| 503 | |
| 504 | hs_start = mode->hsync_start - mode->hdisplay; |
| 505 | hs_end = mode->hsync_end - mode->hdisplay; |
| 506 | line_start = 1; |
| 507 | line_end = 1 + mode->vsync_end - mode->vsync_start; |
| 508 | vwin_start = mode->vtotal - mode->vsync_start; |
| 509 | vwin_end = vwin_start + mode->vdisplay; |
| 510 | de_start = mode->htotal - mode->hdisplay; |
| 511 | de_end = mode->htotal; |
| 512 | |
| 513 | pix_start2 = 0; |
| 514 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) |
| 515 | pix_start2 = (mode->htotal / 2) + hs_start; |
| 516 | |
| 517 | /* TODO how is this value calculated? It is 2 for all common |
| 518 | * formats in the tables in out of tree nxp driver (assuming |
| 519 | * I've properly deciphered their byzantine table system) |
| 520 | */ |
| 521 | ref_line = 2; |
| 522 | |
| 523 | /* this might changes for other color formats from the CRTC: */ |
| 524 | ref_pix = 3 + hs_start; |
| 525 | |
| 526 | div = 148500 / mode->clock; |
| 527 | |
| 528 | DBG("clock=%d, div=%u", mode->clock, div); |
| 529 | DBG("hs_start=%u, hs_end=%u, line_start=%u, line_end=%u", |
| 530 | hs_start, hs_end, line_start, line_end); |
| 531 | DBG("vwin_start=%u, vwin_end=%u, de_start=%u, de_end=%u", |
| 532 | vwin_start, vwin_end, de_start, de_end); |
| 533 | DBG("ref_line=%u, ref_pix=%u, pix_start2=%u", |
| 534 | ref_line, ref_pix, pix_start2); |
| 535 | |
| 536 | /* mute the audio FIFO: */ |
| 537 | reg_set(encoder, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); |
| 538 | |
| 539 | /* set HDMI HDCP mode off: */ |
| 540 | reg_set(encoder, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); |
| 541 | reg_clear(encoder, REG_TX33, TX33_HDMI); |
| 542 | |
| 543 | reg_write(encoder, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); |
| 544 | /* no pre-filter or interpolator: */ |
| 545 | reg_write(encoder, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | |
| 546 | HVF_CNTRL_0_INTPOL(0)); |
| 547 | reg_write(encoder, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); |
| 548 | reg_write(encoder, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | |
| 549 | VIP_CNTRL_4_BLC(0)); |
| 550 | reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR); |
| 551 | |
| 552 | reg_clear(encoder, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); |
| 553 | reg_clear(encoder, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_DE); |
| 554 | reg_write(encoder, REG_SERIALIZER, 0); |
| 555 | reg_write(encoder, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); |
| 556 | |
| 557 | /* TODO enable pixel repeat for pixel rates less than 25Msamp/s */ |
| 558 | rep = 0; |
| 559 | reg_write(encoder, REG_RPT_CNTRL, 0); |
| 560 | reg_write(encoder, REG_SEL_CLK, SEL_CLK_SEL_VRF_CLK(0) | |
| 561 | SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); |
| 562 | |
| 563 | reg_write(encoder, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | |
| 564 | PLL_SERIAL_2_SRL_PR(rep)); |
| 565 | |
| 566 | reg_write16(encoder, REG_VS_PIX_STRT_2_MSB, pix_start2); |
| 567 | reg_write16(encoder, REG_VS_PIX_END_2_MSB, pix_start2); |
| 568 | |
| 569 | /* set color matrix bypass flag: */ |
| 570 | reg_set(encoder, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP); |
| 571 | |
| 572 | /* set BIAS tmds value: */ |
| 573 | reg_write(encoder, REG_ANA_GENERAL, 0x09); |
| 574 | |
| 575 | reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_MTHD); |
| 576 | |
| 577 | reg_write(encoder, REG_VIP_CNTRL_3, 0); |
| 578 | reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_SYNC_HS); |
| 579 | if (mode->flags & DRM_MODE_FLAG_NVSYNC) |
| 580 | reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_V_TGL); |
| 581 | |
| 582 | if (mode->flags & DRM_MODE_FLAG_NHSYNC) |
| 583 | reg_set(encoder, REG_VIP_CNTRL_3, VIP_CNTRL_3_H_TGL); |
| 584 | |
| 585 | reg_write(encoder, REG_VIDFORMAT, 0x00); |
| 586 | reg_write16(encoder, REG_NPIX_MSB, mode->hdisplay - 1); |
| 587 | reg_write16(encoder, REG_NLINE_MSB, mode->vdisplay - 1); |
| 588 | reg_write16(encoder, REG_VS_LINE_STRT_1_MSB, line_start); |
| 589 | reg_write16(encoder, REG_VS_LINE_END_1_MSB, line_end); |
| 590 | reg_write16(encoder, REG_VS_PIX_STRT_1_MSB, hs_start); |
| 591 | reg_write16(encoder, REG_VS_PIX_END_1_MSB, hs_start); |
| 592 | reg_write16(encoder, REG_HS_PIX_START_MSB, hs_start); |
| 593 | reg_write16(encoder, REG_HS_PIX_STOP_MSB, hs_end); |
| 594 | reg_write16(encoder, REG_VWIN_START_1_MSB, vwin_start); |
| 595 | reg_write16(encoder, REG_VWIN_END_1_MSB, vwin_end); |
| 596 | reg_write16(encoder, REG_DE_START_MSB, de_start); |
| 597 | reg_write16(encoder, REG_DE_STOP_MSB, de_end); |
| 598 | |
| 599 | if (priv->rev == TDA19988) { |
| 600 | /* let incoming pixels fill the active space (if any) */ |
| 601 | reg_write(encoder, REG_ENABLE_SPACE, 0x01); |
| 602 | } |
| 603 | |
| 604 | reg_write16(encoder, REG_REFPIX_MSB, ref_pix); |
| 605 | reg_write16(encoder, REG_REFLINE_MSB, ref_line); |
| 606 | |
| 607 | reg = TBG_CNTRL_1_VHX_EXT_DE | |
| 608 | TBG_CNTRL_1_VHX_EXT_HS | |
| 609 | TBG_CNTRL_1_VHX_EXT_VS | |
| 610 | TBG_CNTRL_1_DWIN_DIS | /* HDCP off */ |
| 611 | TBG_CNTRL_1_VH_TGL_2; |
| 612 | if (mode->flags & (DRM_MODE_FLAG_NVSYNC | DRM_MODE_FLAG_NHSYNC)) |
| 613 | reg |= TBG_CNTRL_1_VH_TGL_0; |
| 614 | reg_set(encoder, REG_TBG_CNTRL_1, reg); |
| 615 | |
| 616 | /* must be last register set: */ |
| 617 | reg_clear(encoder, REG_TBG_CNTRL_0, TBG_CNTRL_0_SYNC_ONCE); |
| 618 | } |
| 619 | |
| 620 | static enum drm_connector_status |
| 621 | tda998x_encoder_detect(struct drm_encoder *encoder, |
| 622 | struct drm_connector *connector) |
| 623 | { |
| 624 | uint8_t val = cec_read(encoder, REG_CEC_RXSHPDLEV); |
| 625 | return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : |
| 626 | connector_status_disconnected; |
| 627 | } |
| 628 | |
| 629 | static int |
| 630 | read_edid_block(struct drm_encoder *encoder, uint8_t *buf, int blk) |
| 631 | { |
| 632 | uint8_t offset, segptr; |
| 633 | int ret, i; |
| 634 | |
| 635 | /* enable EDID read irq: */ |
| 636 | reg_set(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); |
| 637 | |
| 638 | offset = (blk & 1) ? 128 : 0; |
| 639 | segptr = blk / 2; |
| 640 | |
| 641 | reg_write(encoder, REG_DDC_ADDR, 0xa0); |
| 642 | reg_write(encoder, REG_DDC_OFFS, offset); |
| 643 | reg_write(encoder, REG_DDC_SEGM_ADDR, 0x60); |
| 644 | reg_write(encoder, REG_DDC_SEGM, segptr); |
| 645 | |
| 646 | /* enable reading EDID: */ |
| 647 | reg_write(encoder, REG_EDID_CTRL, 0x1); |
| 648 | |
| 649 | /* flag must be cleared by sw: */ |
| 650 | reg_write(encoder, REG_EDID_CTRL, 0x0); |
| 651 | |
| 652 | /* wait for block read to complete: */ |
| 653 | for (i = 100; i > 0; i--) { |
| 654 | uint8_t val = reg_read(encoder, REG_INT_FLAGS_2); |
| 655 | if (val & INT_FLAGS_2_EDID_BLK_RD) |
| 656 | break; |
| 657 | msleep(1); |
| 658 | } |
| 659 | |
| 660 | if (i == 0) |
| 661 | return -ETIMEDOUT; |
| 662 | |
| 663 | ret = reg_read_range(encoder, REG_EDID_DATA_0, buf, EDID_LENGTH); |
| 664 | if (ret != EDID_LENGTH) { |
| 665 | dev_err(encoder->dev->dev, "failed to read edid block %d: %d", |
| 666 | blk, ret); |
| 667 | return ret; |
| 668 | } |
| 669 | |
| 670 | reg_clear(encoder, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); |
| 671 | |
| 672 | return 0; |
| 673 | } |
| 674 | |
| 675 | static uint8_t * |
| 676 | do_get_edid(struct drm_encoder *encoder) |
| 677 | { |
Russell King | 063b472 | 2013-08-14 21:43:26 +0200 | [diff] [blame^] | 678 | struct tda998x_priv *priv = to_tda998x_priv(encoder); |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 679 | int j = 0, valid_extensions = 0; |
| 680 | uint8_t *block, *new; |
| 681 | bool print_bad_edid = drm_debug & DRM_UT_KMS; |
| 682 | |
| 683 | if ((block = kmalloc(EDID_LENGTH, GFP_KERNEL)) == NULL) |
| 684 | return NULL; |
| 685 | |
Russell King | 063b472 | 2013-08-14 21:43:26 +0200 | [diff] [blame^] | 686 | if (priv->rev == TDA19988) |
| 687 | reg_clear(encoder, REG_TX4, TX4_PD_RAM); |
| 688 | |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 689 | /* base block fetch */ |
| 690 | if (read_edid_block(encoder, block, 0)) |
| 691 | goto fail; |
| 692 | |
| 693 | if (!drm_edid_block_valid(block, 0, print_bad_edid)) |
| 694 | goto fail; |
| 695 | |
| 696 | /* if there's no extensions, we're done */ |
| 697 | if (block[0x7e] == 0) |
Russell King | 063b472 | 2013-08-14 21:43:26 +0200 | [diff] [blame^] | 698 | goto done; |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 699 | |
| 700 | new = krealloc(block, (block[0x7e] + 1) * EDID_LENGTH, GFP_KERNEL); |
| 701 | if (!new) |
| 702 | goto fail; |
| 703 | block = new; |
| 704 | |
| 705 | for (j = 1; j <= block[0x7e]; j++) { |
| 706 | uint8_t *ext_block = block + (valid_extensions + 1) * EDID_LENGTH; |
| 707 | if (read_edid_block(encoder, ext_block, j)) |
| 708 | goto fail; |
| 709 | |
| 710 | if (!drm_edid_block_valid(ext_block, j, print_bad_edid)) |
| 711 | goto fail; |
| 712 | |
| 713 | valid_extensions++; |
| 714 | } |
| 715 | |
| 716 | if (valid_extensions != block[0x7e]) { |
| 717 | block[EDID_LENGTH-1] += block[0x7e] - valid_extensions; |
| 718 | block[0x7e] = valid_extensions; |
| 719 | new = krealloc(block, (valid_extensions + 1) * EDID_LENGTH, GFP_KERNEL); |
| 720 | if (!new) |
| 721 | goto fail; |
| 722 | block = new; |
| 723 | } |
| 724 | |
Russell King | 063b472 | 2013-08-14 21:43:26 +0200 | [diff] [blame^] | 725 | done: |
| 726 | if (priv->rev == TDA19988) |
| 727 | reg_set(encoder, REG_TX4, TX4_PD_RAM); |
| 728 | |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 729 | return block; |
| 730 | |
| 731 | fail: |
Russell King | 063b472 | 2013-08-14 21:43:26 +0200 | [diff] [blame^] | 732 | if (priv->rev == TDA19988) |
| 733 | reg_set(encoder, REG_TX4, TX4_PD_RAM); |
Rob Clark | e7792ce | 2013-01-08 19:21:02 -0600 | [diff] [blame] | 734 | dev_warn(encoder->dev->dev, "failed to read EDID\n"); |
| 735 | kfree(block); |
| 736 | return NULL; |
| 737 | } |
| 738 | |
| 739 | static int |
| 740 | tda998x_encoder_get_modes(struct drm_encoder *encoder, |
| 741 | struct drm_connector *connector) |
| 742 | { |
| 743 | struct edid *edid = (struct edid *)do_get_edid(encoder); |
| 744 | int n = 0; |
| 745 | |
| 746 | if (edid) { |
| 747 | drm_mode_connector_update_edid_property(connector, edid); |
| 748 | n = drm_add_edid_modes(connector, edid); |
| 749 | kfree(edid); |
| 750 | } |
| 751 | |
| 752 | return n; |
| 753 | } |
| 754 | |
| 755 | static int |
| 756 | tda998x_encoder_create_resources(struct drm_encoder *encoder, |
| 757 | struct drm_connector *connector) |
| 758 | { |
| 759 | DBG(""); |
| 760 | return 0; |
| 761 | } |
| 762 | |
| 763 | static int |
| 764 | tda998x_encoder_set_property(struct drm_encoder *encoder, |
| 765 | struct drm_connector *connector, |
| 766 | struct drm_property *property, |
| 767 | uint64_t val) |
| 768 | { |
| 769 | DBG(""); |
| 770 | return 0; |
| 771 | } |
| 772 | |
| 773 | static void |
| 774 | tda998x_encoder_destroy(struct drm_encoder *encoder) |
| 775 | { |
| 776 | struct tda998x_priv *priv = to_tda998x_priv(encoder); |
| 777 | drm_i2c_encoder_destroy(encoder); |
| 778 | kfree(priv); |
| 779 | } |
| 780 | |
| 781 | static struct drm_encoder_slave_funcs tda998x_encoder_funcs = { |
| 782 | .set_config = tda998x_encoder_set_config, |
| 783 | .destroy = tda998x_encoder_destroy, |
| 784 | .dpms = tda998x_encoder_dpms, |
| 785 | .save = tda998x_encoder_save, |
| 786 | .restore = tda998x_encoder_restore, |
| 787 | .mode_fixup = tda998x_encoder_mode_fixup, |
| 788 | .mode_valid = tda998x_encoder_mode_valid, |
| 789 | .mode_set = tda998x_encoder_mode_set, |
| 790 | .detect = tda998x_encoder_detect, |
| 791 | .get_modes = tda998x_encoder_get_modes, |
| 792 | .create_resources = tda998x_encoder_create_resources, |
| 793 | .set_property = tda998x_encoder_set_property, |
| 794 | }; |
| 795 | |
| 796 | /* I2C driver functions */ |
| 797 | |
| 798 | static int |
| 799 | tda998x_probe(struct i2c_client *client, const struct i2c_device_id *id) |
| 800 | { |
| 801 | return 0; |
| 802 | } |
| 803 | |
| 804 | static int |
| 805 | tda998x_remove(struct i2c_client *client) |
| 806 | { |
| 807 | return 0; |
| 808 | } |
| 809 | |
| 810 | static int |
| 811 | tda998x_encoder_init(struct i2c_client *client, |
| 812 | struct drm_device *dev, |
| 813 | struct drm_encoder_slave *encoder_slave) |
| 814 | { |
| 815 | struct drm_encoder *encoder = &encoder_slave->base; |
| 816 | struct tda998x_priv *priv; |
| 817 | |
| 818 | priv = kzalloc(sizeof(*priv), GFP_KERNEL); |
| 819 | if (!priv) |
| 820 | return -ENOMEM; |
| 821 | |
| 822 | priv->current_page = 0; |
| 823 | priv->cec = i2c_new_dummy(client->adapter, 0x34); |
| 824 | priv->dpms = DRM_MODE_DPMS_OFF; |
| 825 | |
| 826 | encoder_slave->slave_priv = priv; |
| 827 | encoder_slave->slave_funcs = &tda998x_encoder_funcs; |
| 828 | |
| 829 | /* wake up the device: */ |
| 830 | cec_write(encoder, REG_CEC_ENAMODS, |
| 831 | CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); |
| 832 | |
| 833 | tda998x_reset(encoder); |
| 834 | |
| 835 | /* read version: */ |
| 836 | priv->rev = reg_read(encoder, REG_VERSION_LSB) | |
| 837 | reg_read(encoder, REG_VERSION_MSB) << 8; |
| 838 | |
| 839 | /* mask off feature bits: */ |
| 840 | priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ |
| 841 | |
| 842 | switch (priv->rev) { |
| 843 | case TDA9989N2: dev_info(dev->dev, "found TDA9989 n2"); break; |
| 844 | case TDA19989: dev_info(dev->dev, "found TDA19989"); break; |
| 845 | case TDA19989N2: dev_info(dev->dev, "found TDA19989 n2"); break; |
| 846 | case TDA19988: dev_info(dev->dev, "found TDA19988"); break; |
| 847 | default: |
| 848 | DBG("found unsupported device: %04x", priv->rev); |
| 849 | goto fail; |
| 850 | } |
| 851 | |
| 852 | /* after reset, enable DDC: */ |
| 853 | reg_write(encoder, REG_DDC_DISABLE, 0x00); |
| 854 | |
| 855 | /* set clock on DDC channel: */ |
| 856 | reg_write(encoder, REG_TX3, 39); |
| 857 | |
| 858 | /* if necessary, disable multi-master: */ |
| 859 | if (priv->rev == TDA19989) |
| 860 | reg_set(encoder, REG_I2C_MASTER, I2C_MASTER_DIS_MM); |
| 861 | |
| 862 | cec_write(encoder, REG_CEC_FRO_IM_CLK_CTRL, |
| 863 | CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); |
| 864 | |
| 865 | return 0; |
| 866 | |
| 867 | fail: |
| 868 | /* if encoder_init fails, the encoder slave is never registered, |
| 869 | * so cleanup here: |
| 870 | */ |
| 871 | if (priv->cec) |
| 872 | i2c_unregister_device(priv->cec); |
| 873 | kfree(priv); |
| 874 | encoder_slave->slave_priv = NULL; |
| 875 | encoder_slave->slave_funcs = NULL; |
| 876 | return -ENXIO; |
| 877 | } |
| 878 | |
| 879 | static struct i2c_device_id tda998x_ids[] = { |
| 880 | { "tda998x", 0 }, |
| 881 | { } |
| 882 | }; |
| 883 | MODULE_DEVICE_TABLE(i2c, tda998x_ids); |
| 884 | |
| 885 | static struct drm_i2c_encoder_driver tda998x_driver = { |
| 886 | .i2c_driver = { |
| 887 | .probe = tda998x_probe, |
| 888 | .remove = tda998x_remove, |
| 889 | .driver = { |
| 890 | .name = "tda998x", |
| 891 | }, |
| 892 | .id_table = tda998x_ids, |
| 893 | }, |
| 894 | .encoder_init = tda998x_encoder_init, |
| 895 | }; |
| 896 | |
| 897 | /* Module initialization */ |
| 898 | |
| 899 | static int __init |
| 900 | tda998x_init(void) |
| 901 | { |
| 902 | DBG(""); |
| 903 | return drm_i2c_encoder_register(THIS_MODULE, &tda998x_driver); |
| 904 | } |
| 905 | |
| 906 | static void __exit |
| 907 | tda998x_exit(void) |
| 908 | { |
| 909 | DBG(""); |
| 910 | drm_i2c_encoder_unregister(&tda998x_driver); |
| 911 | } |
| 912 | |
| 913 | MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); |
| 914 | MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); |
| 915 | MODULE_LICENSE("GPL"); |
| 916 | |
| 917 | module_init(tda998x_init); |
| 918 | module_exit(tda998x_exit); |