Mukesh Kumar Savaliya | 065ca48 | 2017-06-06 14:44:45 +0530 | [diff] [blame^] | 1 | /* Copyright (c) 2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #include <dt-bindings/msm/msm-bus-ids.h> |
| 14 | |
| 15 | &soc { |
| 16 | /* QUPv3 South instances */ |
| 17 | qupv3_0: qcom,qupv3_0_geni_se@8c0000 { |
| 18 | compatible = "qcom,qupv3-geni-se"; |
| 19 | reg = <0x8c0000 0x6000>; |
| 20 | qcom,bus-mas-id = <MSM_BUS_MASTER_BLSP_1>; |
| 21 | qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>; |
| 22 | qcom,iommu-s1-bypass; |
| 23 | |
| 24 | iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb { |
| 25 | compatible = "qcom,qupv3-geni-se-cb"; |
| 26 | iommus = <&apps_smmu 0x003 0x0>; |
| 27 | }; |
| 28 | }; |
| 29 | |
| 30 | /* |
| 31 | * HS UART instances. HS UART usecases can be supported on these |
| 32 | * instances only. |
| 33 | */ |
| 34 | qupv3_se6_4uart: qcom,qup_uart@0x898000 { |
| 35 | compatible = "qcom,msm-geni-serial-hs", "qcom,msm-geni-uart"; |
| 36 | reg = <0x898000 0x4000>; |
| 37 | reg-names = "se_phys"; |
| 38 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 39 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, |
| 40 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 41 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 42 | pinctrl-names = "default", "sleep"; |
| 43 | pinctrl-0 = <&qupv3_se6_4uart_active>; |
| 44 | pinctrl-1 = <&qupv3_se6_4uart_sleep>; |
| 45 | interrupts-extended = <&intc GIC_SPI 607 0>, |
| 46 | <&tlmm 48 0>; |
| 47 | status = "disabled"; |
| 48 | qcom,wakeup-byte = <0xFD>; |
| 49 | qcom,wrapper-core = <&qupv3_0>; |
| 50 | }; |
| 51 | |
| 52 | qupv3_se7_4uart: qcom,qup_uart@0x89c000 { |
| 53 | compatible = "qcom,msm-geni-serial-hs", "qcom,msm-geni-uart"; |
| 54 | reg = <0x89c000 0x4000>; |
| 55 | reg-names = "se_phys"; |
| 56 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 57 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, |
| 58 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 59 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 60 | pinctrl-names = "default", "sleep"; |
| 61 | pinctrl-0 = <&qupv3_se7_4uart_active>; |
| 62 | pinctrl-1 = <&qupv3_se7_4uart_sleep>; |
| 63 | interrupts-extended = <&intc GIC_SPI 608 0>, |
| 64 | <&tlmm 96 0>; |
| 65 | status = "disabled"; |
| 66 | qcom,wakeup-byte = <0xFD>; |
| 67 | qcom,wrapper-core = <&qupv3_0>; |
| 68 | }; |
| 69 | |
| 70 | /* I2C */ |
| 71 | qupv3_se0_i2c: i2c@880000 { |
| 72 | compatible = "qcom,i2c-geni"; |
| 73 | reg = <0x880000 0x4000>; |
| 74 | interrupts = <GIC_SPI 601 0>; |
| 75 | #address-cells = <1>; |
| 76 | #size-cells = <0>; |
| 77 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 78 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, |
| 79 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 80 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 81 | pinctrl-names = "default", "sleep"; |
| 82 | pinctrl-0 = <&qupv3_se0_i2c_active>; |
| 83 | pinctrl-1 = <&qupv3_se0_i2c_sleep>; |
| 84 | qcom,wrapper-core = <&qupv3_0>; |
| 85 | status = "disabled"; |
| 86 | }; |
| 87 | |
| 88 | qupv3_se1_i2c: i2c@884000 { |
| 89 | compatible = "qcom,i2c-geni"; |
| 90 | reg = <0x884000 0x4000>; |
| 91 | interrupts = <GIC_SPI 602 0>; |
| 92 | #address-cells = <1>; |
| 93 | #size-cells = <0>; |
| 94 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 95 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, |
| 96 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 97 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 98 | pinctrl-names = "default", "sleep"; |
| 99 | pinctrl-0 = <&qupv3_se1_i2c_active>; |
| 100 | pinctrl-1 = <&qupv3_se1_i2c_sleep>; |
| 101 | qcom,wrapper-core = <&qupv3_0>; |
| 102 | status = "disabled"; |
| 103 | }; |
| 104 | |
| 105 | qupv3_se2_i2c: i2c@888000 { |
| 106 | compatible = "qcom,i2c-geni"; |
| 107 | reg = <0x888000 0x4000>; |
| 108 | interrupts = <GIC_SPI 603 0>; |
| 109 | #address-cells = <1>; |
| 110 | #size-cells = <0>; |
| 111 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 112 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, |
| 113 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 114 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 115 | pinctrl-names = "default", "sleep"; |
| 116 | pinctrl-0 = <&qupv3_se2_i2c_active>; |
| 117 | pinctrl-1 = <&qupv3_se2_i2c_sleep>; |
| 118 | qcom,wrapper-core = <&qupv3_0>; |
| 119 | status = "disabled"; |
| 120 | }; |
| 121 | |
| 122 | qupv3_se3_i2c: i2c@88c000 { |
| 123 | compatible = "qcom,i2c-geni"; |
| 124 | reg = <0x88c000 0x4000>; |
| 125 | interrupts = <GIC_SPI 604 0>; |
| 126 | #address-cells = <1>; |
| 127 | #size-cells = <0>; |
| 128 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 129 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, |
| 130 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 131 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 132 | pinctrl-names = "default", "sleep"; |
| 133 | pinctrl-0 = <&qupv3_se3_i2c_active>; |
| 134 | pinctrl-1 = <&qupv3_se3_i2c_sleep>; |
| 135 | qcom,wrapper-core = <&qupv3_0>; |
| 136 | status = "disabled"; |
| 137 | }; |
| 138 | |
| 139 | qupv3_se4_i2c: i2c@890000 { |
| 140 | compatible = "qcom,i2c-geni"; |
| 141 | reg = <0x890000 0x4000>; |
| 142 | interrupts = <GIC_SPI 605 0>; |
| 143 | #address-cells = <1>; |
| 144 | #size-cells = <0>; |
| 145 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 146 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, |
| 147 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 148 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 149 | pinctrl-names = "default", "sleep"; |
| 150 | pinctrl-0 = <&qupv3_se4_i2c_active>; |
| 151 | pinctrl-1 = <&qupv3_se4_i2c_sleep>; |
| 152 | qcom,wrapper-core = <&qupv3_0>; |
| 153 | status = "disabled"; |
| 154 | }; |
| 155 | |
| 156 | qupv3_se5_i2c: i2c@894000 { |
| 157 | compatible = "qcom,i2c-geni"; |
| 158 | reg = <0x894000 0x4000>; |
| 159 | interrupts = <GIC_SPI 606 0>; |
| 160 | #address-cells = <1>; |
| 161 | #size-cells = <0>; |
| 162 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 163 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, |
| 164 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 165 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 166 | pinctrl-names = "default", "sleep"; |
| 167 | pinctrl-0 = <&qupv3_se5_i2c_active>; |
| 168 | pinctrl-1 = <&qupv3_se5_i2c_sleep>; |
| 169 | qcom,wrapper-core = <&qupv3_0>; |
| 170 | status = "disabled"; |
| 171 | }; |
| 172 | |
| 173 | qupv3_se6_i2c: i2c@898000 { |
| 174 | compatible = "qcom,i2c-geni"; |
| 175 | reg = <0x898000 0x4000>; |
| 176 | interrupts = <GIC_SPI 607 0>; |
| 177 | #address-cells = <1>; |
| 178 | #size-cells = <0>; |
| 179 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 180 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, |
| 181 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 182 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 183 | pinctrl-names = "default", "sleep"; |
| 184 | pinctrl-0 = <&qupv3_se6_i2c_active>; |
| 185 | pinctrl-1 = <&qupv3_se6_i2c_sleep>; |
| 186 | qcom,wrapper-core = <&qupv3_0>; |
| 187 | status = "disabled"; |
| 188 | }; |
| 189 | |
| 190 | qupv3_se7_i2c: i2c@89c000 { |
| 191 | compatible = "qcom,i2c-geni"; |
| 192 | reg = <0x89c000 0x4000>; |
| 193 | interrupts = <GIC_SPI 608 0>; |
| 194 | #address-cells = <1>; |
| 195 | #size-cells = <0>; |
| 196 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 197 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, |
| 198 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 199 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 200 | pinctrl-names = "default", "sleep"; |
| 201 | pinctrl-0 = <&qupv3_se7_i2c_active>; |
| 202 | pinctrl-1 = <&qupv3_se7_i2c_sleep>; |
| 203 | qcom,wrapper-core = <&qupv3_0>; |
| 204 | status = "disabled"; |
| 205 | }; |
| 206 | |
| 207 | /* SPI */ |
| 208 | qupv3_se0_spi: spi@880000 { |
| 209 | compatible = "qcom,spi-geni"; |
| 210 | #address-cells = <1>; |
| 211 | #size-cells = <0>; |
| 212 | reg = <0x880000 0x4000>; |
| 213 | reg-names = "se_phys"; |
| 214 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 215 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, |
| 216 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 217 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 218 | pinctrl-names = "default", "sleep"; |
| 219 | pinctrl-0 = <&qupv3_se0_spi_active>; |
| 220 | pinctrl-1 = <&qupv3_se0_spi_sleep>; |
| 221 | interrupts = <GIC_SPI 601 0>; |
| 222 | spi-max-frequency = <50000000>; |
| 223 | qcom,wrapper-core = <&qupv3_0>; |
| 224 | status = "disabled"; |
| 225 | }; |
| 226 | |
| 227 | qupv3_se1_spi: spi@884000 { |
| 228 | compatible = "qcom,spi-geni"; |
| 229 | #address-cells = <1>; |
| 230 | #size-cells = <0>; |
| 231 | reg = <0x884000 0x4000>; |
| 232 | reg-names = "se_phys"; |
| 233 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 234 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, |
| 235 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 236 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 237 | pinctrl-names = "default", "sleep"; |
| 238 | pinctrl-0 = <&qupv3_se1_spi_active>; |
| 239 | pinctrl-1 = <&qupv3_se1_spi_sleep>; |
| 240 | interrupts = <GIC_SPI 602 0>; |
| 241 | spi-max-frequency = <50000000>; |
| 242 | qcom,wrapper-core = <&qupv3_0>; |
| 243 | status = "disabled"; |
| 244 | }; |
| 245 | |
| 246 | qupv3_se2_spi: spi@888000 { |
| 247 | compatible = "qcom,spi-geni"; |
| 248 | #address-cells = <1>; |
| 249 | #size-cells = <0>; |
| 250 | reg = <0x888000 0x4000>; |
| 251 | reg-names = "se_phys"; |
| 252 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 253 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, |
| 254 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 255 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 256 | pinctrl-names = "default", "sleep"; |
| 257 | pinctrl-0 = <&qupv3_se2_spi_active>; |
| 258 | pinctrl-1 = <&qupv3_se2_spi_sleep>; |
| 259 | interrupts = <GIC_SPI 603 0>; |
| 260 | spi-max-frequency = <50000000>; |
| 261 | qcom,wrapper-core = <&qupv3_0>; |
| 262 | status = "disabled"; |
| 263 | }; |
| 264 | |
| 265 | qupv3_se3_spi: spi@88c000 { |
| 266 | compatible = "qcom,spi-geni"; |
| 267 | #address-cells = <1>; |
| 268 | #size-cells = <0>; |
| 269 | reg = <0x88c000 0x4000>; |
| 270 | reg-names = "se_phys"; |
| 271 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 272 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, |
| 273 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 274 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 275 | pinctrl-names = "default", "sleep"; |
| 276 | pinctrl-0 = <&qupv3_se3_spi_active>; |
| 277 | pinctrl-1 = <&qupv3_se3_spi_sleep>; |
| 278 | interrupts = <GIC_SPI 604 0>; |
| 279 | spi-max-frequency = <50000000>; |
| 280 | qcom,wrapper-core = <&qupv3_0>; |
| 281 | status = "disabled"; |
| 282 | }; |
| 283 | |
| 284 | qupv3_se4_spi: spi@890000 { |
| 285 | compatible = "qcom,spi-geni"; |
| 286 | #address-cells = <1>; |
| 287 | #size-cells = <0>; |
| 288 | reg = <0x890000 0x4000>; |
| 289 | reg-names = "se_phys"; |
| 290 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 291 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, |
| 292 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 293 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 294 | pinctrl-names = "default", "sleep"; |
| 295 | pinctrl-0 = <&qupv3_se4_spi_active>; |
| 296 | pinctrl-1 = <&qupv3_se4_spi_sleep>; |
| 297 | interrupts = <GIC_SPI 605 0>; |
| 298 | spi-max-frequency = <50000000>; |
| 299 | qcom,wrapper-core = <&qupv3_0>; |
| 300 | status = "disabled"; |
| 301 | }; |
| 302 | |
| 303 | qupv3_se5_spi: spi@894000 { |
| 304 | compatible = "qcom,spi-geni"; |
| 305 | #address-cells = <1>; |
| 306 | #size-cells = <0>; |
| 307 | reg = <0x894000 0x4000>; |
| 308 | reg-names = "se_phys"; |
| 309 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 310 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, |
| 311 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 312 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 313 | pinctrl-names = "default", "sleep"; |
| 314 | pinctrl-0 = <&qupv3_se5_spi_active>; |
| 315 | pinctrl-1 = <&qupv3_se5_spi_sleep>; |
| 316 | interrupts = <GIC_SPI 606 0>; |
| 317 | spi-max-frequency = <50000000>; |
| 318 | qcom,wrapper-core = <&qupv3_0>; |
| 319 | status = "disabled"; |
| 320 | }; |
| 321 | |
| 322 | qupv3_se6_spi: spi@898000 { |
| 323 | compatible = "qcom,spi-geni"; |
| 324 | #address-cells = <1>; |
| 325 | #size-cells = <0>; |
| 326 | reg = <0x898000 0x4000>; |
| 327 | reg-names = "se_phys"; |
| 328 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 329 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, |
| 330 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 331 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 332 | pinctrl-names = "default", "sleep"; |
| 333 | pinctrl-0 = <&qupv3_se6_spi_active>; |
| 334 | pinctrl-1 = <&qupv3_se6_spi_sleep>; |
| 335 | interrupts = <GIC_SPI 607 0>; |
| 336 | spi-max-frequency = <50000000>; |
| 337 | qcom,wrapper-core = <&qupv3_0>; |
| 338 | status = "disabled"; |
| 339 | }; |
| 340 | |
| 341 | qupv3_se7_spi: spi@89c000 { |
| 342 | compatible = "qcom,spi-geni"; |
| 343 | #address-cells = <1>; |
| 344 | #size-cells = <0>; |
| 345 | reg = <0x89c000 0x4000>; |
| 346 | reg-names = "se_phys"; |
| 347 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 348 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, |
| 349 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 350 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 351 | pinctrl-names = "default", "sleep"; |
| 352 | pinctrl-0 = <&qupv3_se7_spi_active>; |
| 353 | pinctrl-1 = <&qupv3_se7_spi_sleep>; |
| 354 | interrupts = <GIC_SPI 608 0>; |
| 355 | spi-max-frequency = <50000000>; |
| 356 | qcom,wrapper-core = <&qupv3_0>; |
| 357 | status = "disabled"; |
| 358 | }; |
| 359 | |
| 360 | /* QUPv3 North Instances */ |
| 361 | qupv3_1: qcom,qupv3_1_geni_se@ac0000 { |
| 362 | compatible = "qcom,qupv3-geni-se"; |
| 363 | reg = <0xac0000 0x6000>; |
| 364 | qcom,bus-mas-id = <MSM_BUS_MASTER_BLSP_2>; |
| 365 | qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>; |
| 366 | qcom,iommu-s1-bypass; |
| 367 | |
| 368 | iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb { |
| 369 | compatible = "qcom,qupv3-geni-se-cb"; |
| 370 | iommus = <&apps_smmu 0x6c3 0x0>; |
| 371 | }; |
| 372 | }; |
| 373 | |
| 374 | /* 2-wire UART */ |
| 375 | |
| 376 | /* Debug UART Instance for CDP/MTP platform */ |
| 377 | qupv3_se9_2uart: qcom,qup_uart@0xa84000 { |
| 378 | compatible = "qcom,msm-geni-console", "qcom,msm-geni-uart"; |
| 379 | reg = <0xa84000 0x4000>; |
| 380 | reg-names = "se_phys"; |
| 381 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 382 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, |
| 383 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 384 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 385 | pinctrl-names = "default", "sleep"; |
| 386 | pinctrl-0 = <&qupv3_se9_2uart_active>; |
| 387 | pinctrl-1 = <&qupv3_se9_2uart_sleep>; |
| 388 | interrupts = <GIC_SPI 354 0>; |
| 389 | qcom,wrapper-core = <&qupv3_1>; |
| 390 | status = "disabled"; |
| 391 | }; |
| 392 | |
| 393 | /* Debug UART Instance for RUMI platform */ |
| 394 | qupv3_se10_2uart: qcom,qup_uart@0xa88000 { |
| 395 | compatible = "qcom,msm-geni-console", "qcom,msm-geni-uart"; |
| 396 | reg = <0xa88000 0x4000>; |
| 397 | reg-names = "se_phys"; |
| 398 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 399 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, |
| 400 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 401 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 402 | pinctrl-names = "default", "sleep"; |
| 403 | pinctrl-0 = <&qupv3_se10_2uart_active>; |
| 404 | pinctrl-1 = <&qupv3_se10_2uart_sleep>; |
| 405 | interrupts = <GIC_SPI 355 0>; |
| 406 | qcom,wrapper-core = <&qupv3_1>; |
| 407 | status = "disabled"; |
| 408 | }; |
| 409 | |
| 410 | /* I2C */ |
| 411 | qupv3_se8_i2c: i2c@a80000 { |
| 412 | compatible = "qcom,i2c-geni"; |
| 413 | reg = <0xa80000 0x4000>; |
| 414 | interrupts = <GIC_SPI 353 0>; |
| 415 | #address-cells = <1>; |
| 416 | #size-cells = <0>; |
| 417 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 418 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, |
| 419 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 420 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 421 | pinctrl-names = "default", "sleep"; |
| 422 | pinctrl-0 = <&qupv3_se8_i2c_active>; |
| 423 | pinctrl-1 = <&qupv3_se8_i2c_sleep>; |
| 424 | qcom,wrapper-core = <&qupv3_1>; |
| 425 | status = "disabled"; |
| 426 | }; |
| 427 | |
| 428 | qupv3_se9_i2c: i2c@a84000 { |
| 429 | compatible = "qcom,i2c-geni"; |
| 430 | reg = <0xa84000 0x4000>; |
| 431 | interrupts = <GIC_SPI 354 0>; |
| 432 | #address-cells = <1>; |
| 433 | #size-cells = <0>; |
| 434 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 435 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, |
| 436 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 437 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 438 | pinctrl-names = "default", "sleep"; |
| 439 | pinctrl-0 = <&qupv3_se9_i2c_active>; |
| 440 | pinctrl-1 = <&qupv3_se9_i2c_sleep>; |
| 441 | qcom,wrapper-core = <&qupv3_1>; |
| 442 | status = "disabled"; |
| 443 | }; |
| 444 | |
| 445 | qupv3_se10_i2c: i2c@a88000 { |
| 446 | compatible = "qcom,i2c-geni"; |
| 447 | reg = <0xa88000 0x4000>; |
| 448 | interrupts = <GIC_SPI 355 0>; |
| 449 | #address-cells = <1>; |
| 450 | #size-cells = <0>; |
| 451 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 452 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, |
| 453 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 454 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 455 | pinctrl-names = "default", "sleep"; |
| 456 | pinctrl-0 = <&qupv3_se10_i2c_active>; |
| 457 | pinctrl-1 = <&qupv3_se10_i2c_sleep>; |
| 458 | qcom,wrapper-core = <&qupv3_1>; |
| 459 | status = "disabled"; |
| 460 | }; |
| 461 | |
| 462 | qupv3_se11_i2c: i2c@a8c000 { |
| 463 | compatible = "qcom,i2c-geni"; |
| 464 | reg = <0xa8c000 0x4000>; |
| 465 | interrupts = <GIC_SPI 356 0>; |
| 466 | #address-cells = <1>; |
| 467 | #size-cells = <0>; |
| 468 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 469 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, |
| 470 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 471 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 472 | pinctrl-names = "default", "sleep"; |
| 473 | pinctrl-0 = <&qupv3_se11_i2c_active>; |
| 474 | pinctrl-1 = <&qupv3_se11_i2c_sleep>; |
| 475 | qcom,wrapper-core = <&qupv3_1>; |
| 476 | status = "disabled"; |
| 477 | }; |
| 478 | |
| 479 | qupv3_se12_i2c: i2c@a90000 { |
| 480 | compatible = "qcom,i2c-geni"; |
| 481 | reg = <0xa90000 0x4000>; |
| 482 | interrupts = <GIC_SPI 357 0>; |
| 483 | #address-cells = <1>; |
| 484 | #size-cells = <0>; |
| 485 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 486 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, |
| 487 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 488 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 489 | pinctrl-names = "default", "sleep"; |
| 490 | pinctrl-0 = <&qupv3_se12_i2c_active>; |
| 491 | pinctrl-1 = <&qupv3_se12_i2c_sleep>; |
| 492 | qcom,wrapper-core = <&qupv3_1>; |
| 493 | status = "disabled"; |
| 494 | }; |
| 495 | |
| 496 | qupv3_se13_i2c: i2c@a94000 { |
| 497 | compatible = "qcom,i2c-geni"; |
| 498 | reg = <0xa94000 0x4000>; |
| 499 | interrupts = <GIC_SPI 358 0>; |
| 500 | #address-cells = <1>; |
| 501 | #size-cells = <0>; |
| 502 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 503 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, |
| 504 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 505 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 506 | pinctrl-names = "default", "sleep"; |
| 507 | pinctrl-0 = <&qupv3_se13_i2c_active>; |
| 508 | pinctrl-1 = <&qupv3_se13_i2c_sleep>; |
| 509 | qcom,wrapper-core = <&qupv3_1>; |
| 510 | status = "disabled"; |
| 511 | }; |
| 512 | |
| 513 | qupv3_se14_i2c: i2c@a98000 { |
| 514 | compatible = "qcom,i2c-geni"; |
| 515 | reg = <0xa98000 0x4000>; |
| 516 | interrupts = <GIC_SPI 359 0>; |
| 517 | #address-cells = <1>; |
| 518 | #size-cells = <0>; |
| 519 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 520 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S6_CLK>, |
| 521 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 522 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 523 | pinctrl-names = "default", "sleep"; |
| 524 | pinctrl-0 = <&qupv3_se14_i2c_active>; |
| 525 | pinctrl-1 = <&qupv3_se14_i2c_sleep>; |
| 526 | qcom,wrapper-core = <&qupv3_1>; |
| 527 | status = "disabled"; |
| 528 | }; |
| 529 | |
| 530 | qupv3_se15_i2c: i2c@a9c000 { |
| 531 | compatible = "qcom,i2c-geni"; |
| 532 | reg = <0xa9c000 0x4000>; |
| 533 | interrupts = <GIC_SPI 360 0>; |
| 534 | #address-cells = <1>; |
| 535 | #size-cells = <0>; |
| 536 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 537 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S7_CLK>, |
| 538 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 539 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 540 | pinctrl-names = "default", "sleep"; |
| 541 | pinctrl-0 = <&qupv3_se15_i2c_active>; |
| 542 | pinctrl-1 = <&qupv3_se15_i2c_sleep>; |
| 543 | qcom,wrapper-core = <&qupv3_1>; |
| 544 | status = "disabled"; |
| 545 | }; |
| 546 | |
| 547 | /* SPI */ |
| 548 | qupv3_se8_spi: spi@a80000 { |
| 549 | compatible = "qcom,spi-geni"; |
| 550 | #address-cells = <1>; |
| 551 | #size-cells = <0>; |
| 552 | reg = <0xa80000 0x4000>; |
| 553 | reg-names = "se_phys"; |
| 554 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 555 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, |
| 556 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 557 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 558 | pinctrl-names = "default", "sleep"; |
| 559 | pinctrl-0 = <&qupv3_se8_spi_active>; |
| 560 | pinctrl-1 = <&qupv3_se8_spi_sleep>; |
| 561 | interrupts = <GIC_SPI 353 0>; |
| 562 | spi-max-frequency = <50000000>; |
| 563 | qcom,wrapper-core = <&qupv3_1>; |
| 564 | status = "disabled"; |
| 565 | }; |
| 566 | |
| 567 | qupv3_se9_spi: spi@a84000 { |
| 568 | compatible = "qcom,spi-geni"; |
| 569 | #address-cells = <1>; |
| 570 | #size-cells = <0>; |
| 571 | reg = <0xa84000 0x4000>; |
| 572 | reg-names = "se_phys"; |
| 573 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 574 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, |
| 575 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 576 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 577 | pinctrl-names = "default", "sleep"; |
| 578 | pinctrl-0 = <&qupv3_se9_spi_active>; |
| 579 | pinctrl-1 = <&qupv3_se9_spi_sleep>; |
| 580 | interrupts = <GIC_SPI 354 0>; |
| 581 | spi-max-frequency = <50000000>; |
| 582 | qcom,wrapper-core = <&qupv3_1>; |
| 583 | status = "disabled"; |
| 584 | }; |
| 585 | |
| 586 | qupv3_se10_spi: spi@a88000 { |
| 587 | compatible = "qcom,spi-geni"; |
| 588 | #address-cells = <1>; |
| 589 | #size-cells = <0>; |
| 590 | reg = <0xa88000 0x4000>; |
| 591 | reg-names = "se_phys"; |
| 592 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 593 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, |
| 594 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 595 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 596 | pinctrl-names = "default", "sleep"; |
| 597 | pinctrl-0 = <&qupv3_se10_spi_active>; |
| 598 | pinctrl-1 = <&qupv3_se10_spi_sleep>; |
| 599 | interrupts = <GIC_SPI 355 0>; |
| 600 | spi-max-frequency = <50000000>; |
| 601 | qcom,wrapper-core = <&qupv3_1>; |
| 602 | status = "disabled"; |
| 603 | }; |
| 604 | |
| 605 | qupv3_se11_spi: spi@a8c000 { |
| 606 | compatible = "qcom,spi-geni"; |
| 607 | #address-cells = <1>; |
| 608 | #size-cells = <0>; |
| 609 | reg = <0xa8c000 0x4000>; |
| 610 | reg-names = "se_phys"; |
| 611 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 612 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, |
| 613 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 614 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 615 | pinctrl-names = "default", "sleep"; |
| 616 | pinctrl-0 = <&qupv3_se11_spi_active>; |
| 617 | pinctrl-1 = <&qupv3_se11_spi_sleep>; |
| 618 | interrupts = <GIC_SPI 356 0>; |
| 619 | spi-max-frequency = <50000000>; |
| 620 | qcom,wrapper-core = <&qupv3_1>; |
| 621 | status = "disabled"; |
| 622 | }; |
| 623 | |
| 624 | qupv3_se12_spi: spi@a90000 { |
| 625 | compatible = "qcom,spi-geni"; |
| 626 | #address-cells = <1>; |
| 627 | #size-cells = <0>; |
| 628 | reg = <0xa90000 0x4000>; |
| 629 | reg-names = "se_phys"; |
| 630 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 631 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, |
| 632 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 633 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 634 | pinctrl-names = "default", "sleep"; |
| 635 | pinctrl-0 = <&qupv3_se12_spi_active>; |
| 636 | pinctrl-1 = <&qupv3_se12_spi_sleep>; |
| 637 | interrupts = <GIC_SPI 357 0>; |
| 638 | spi-max-frequency = <50000000>; |
| 639 | qcom,wrapper-core = <&qupv3_1>; |
| 640 | status = "disabled"; |
| 641 | }; |
| 642 | |
| 643 | qupv3_se13_spi: spi@a94000 { |
| 644 | compatible = "qcom,spi-geni"; |
| 645 | #address-cells = <1>; |
| 646 | #size-cells = <0>; |
| 647 | reg = <0xa94000 0x4000>; |
| 648 | reg-names = "se_phys"; |
| 649 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 650 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, |
| 651 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 652 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 653 | pinctrl-names = "default", "sleep"; |
| 654 | pinctrl-0 = <&qupv3_se13_spi_active>; |
| 655 | pinctrl-1 = <&qupv3_se13_spi_sleep>; |
| 656 | interrupts = <GIC_SPI 358 0>; |
| 657 | spi-max-frequency = <50000000>; |
| 658 | qcom,wrapper-core = <&qupv3_1>; |
| 659 | status = "disabled"; |
| 660 | }; |
| 661 | |
| 662 | qupv3_se14_spi: spi@a98000 { |
| 663 | compatible = "qcom,spi-geni"; |
| 664 | #address-cells = <1>; |
| 665 | #size-cells = <0>; |
| 666 | reg = <0xa98000 0x4000>; |
| 667 | reg-names = "se_phys"; |
| 668 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 669 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S6_CLK>, |
| 670 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 671 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 672 | pinctrl-names = "default", "sleep"; |
| 673 | pinctrl-0 = <&qupv3_se14_spi_active>; |
| 674 | pinctrl-1 = <&qupv3_se14_spi_sleep>; |
| 675 | interrupts = <GIC_SPI 359 0>; |
| 676 | spi-max-frequency = <50000000>; |
| 677 | qcom,wrapper-core = <&qupv3_1>; |
| 678 | status = "disabled"; |
| 679 | }; |
| 680 | |
| 681 | qupv3_se15_spi: spi@a9c000 { |
| 682 | compatible = "qcom,spi-geni"; |
| 683 | #address-cells = <1>; |
| 684 | #size-cells = <0>; |
| 685 | reg = <0xa9c000 0x4000>; |
| 686 | reg-names = "se_phys"; |
| 687 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 688 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S7_CLK>, |
| 689 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 690 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 691 | pinctrl-names = "default", "sleep"; |
| 692 | pinctrl-0 = <&qupv3_se15_spi_active>; |
| 693 | pinctrl-1 = <&qupv3_se15_spi_sleep>; |
| 694 | interrupts = <GIC_SPI 360 0>; |
| 695 | spi-max-frequency = <50000000>; |
| 696 | qcom,wrapper-core = <&qupv3_1>; |
| 697 | status = "disabled"; |
| 698 | }; |
| 699 | }; |