| Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2013 NVIDIA Corporation |
| 3 | * |
| Thierry Reding | 9a2ac2d | 2014-02-11 15:52:01 +0100 | [diff] [blame] | 4 | * This program is free software; you can redistribute it and/or modify |
| 5 | * it under the terms of the GNU General Public License version 2 as |
| 6 | * published by the Free Software Foundation. |
| Thierry Reding | dec7273 | 2013-09-03 08:45:46 +0200 | [diff] [blame] | 7 | */ |
| 8 | |
| 9 | #ifndef DRM_TEGRA_DSI_H |
| 10 | #define DRM_TEGRA_DSI_H |
| 11 | |
| 12 | #define DSI_INCR_SYNCPT 0x00 |
| 13 | #define DSI_INCR_SYNCPT_CONTROL 0x01 |
| 14 | #define DSI_INCR_SYNCPT_ERROR 0x02 |
| 15 | #define DSI_CTXSW 0x08 |
| 16 | #define DSI_RD_DATA 0x09 |
| 17 | #define DSI_WR_DATA 0x0a |
| 18 | #define DSI_POWER_CONTROL 0x0b |
| 19 | #define DSI_POWER_CONTROL_ENABLE (1 << 0) |
| 20 | #define DSI_INT_ENABLE 0x0c |
| 21 | #define DSI_INT_STATUS 0x0d |
| 22 | #define DSI_INT_MASK 0x0e |
| 23 | #define DSI_HOST_CONTROL 0x0f |
| 24 | #define DSI_HOST_CONTROL_RAW (1 << 6) |
| 25 | #define DSI_HOST_CONTROL_HS (1 << 5) |
| 26 | #define DSI_HOST_CONTROL_BTA (1 << 2) |
| 27 | #define DSI_HOST_CONTROL_CS (1 << 1) |
| 28 | #define DSI_HOST_CONTROL_ECC (1 << 0) |
| 29 | #define DSI_CONTROL 0x10 |
| 30 | #define DSI_CONTROL_HS_CLK_CTRL (1 << 20) |
| 31 | #define DSI_CONTROL_CHANNEL(c) (((c) & 0x3) << 16) |
| 32 | #define DSI_CONTROL_FORMAT(f) (((f) & 0x3) << 12) |
| 33 | #define DSI_CONTROL_TX_TRIG(x) (((x) & 0x3) << 8) |
| 34 | #define DSI_CONTROL_LANES(n) (((n) & 0x3) << 4) |
| 35 | #define DSI_CONTROL_DCS_ENABLE (1 << 3) |
| 36 | #define DSI_CONTROL_SOURCE(s) (((s) & 0x1) << 2) |
| 37 | #define DSI_CONTROL_VIDEO_ENABLE (1 << 1) |
| 38 | #define DSI_CONTROL_HOST_ENABLE (1 << 0) |
| 39 | #define DSI_SOL_DELAY 0x11 |
| 40 | #define DSI_MAX_THRESHOLD 0x12 |
| 41 | #define DSI_TRIGGER 0x13 |
| 42 | #define DSI_TX_CRC 0x14 |
| 43 | #define DSI_STATUS 0x15 |
| 44 | #define DSI_STATUS_IDLE (1 << 10) |
| 45 | #define DSI_INIT_SEQ_CONTROL 0x1a |
| 46 | #define DSI_INIT_SEQ_DATA_0 0x1b |
| 47 | #define DSI_INIT_SEQ_DATA_1 0x1c |
| 48 | #define DSI_INIT_SEQ_DATA_2 0x1d |
| 49 | #define DSI_INIT_SEQ_DATA_3 0x1e |
| 50 | #define DSI_INIT_SEQ_DATA_4 0x1f |
| 51 | #define DSI_INIT_SEQ_DATA_5 0x20 |
| 52 | #define DSI_INIT_SEQ_DATA_6 0x21 |
| 53 | #define DSI_INIT_SEQ_DATA_7 0x22 |
| 54 | #define DSI_PKT_SEQ_0_LO 0x23 |
| 55 | #define DSI_PKT_SEQ_0_HI 0x24 |
| 56 | #define DSI_PKT_SEQ_1_LO 0x25 |
| 57 | #define DSI_PKT_SEQ_1_HI 0x26 |
| 58 | #define DSI_PKT_SEQ_2_LO 0x27 |
| 59 | #define DSI_PKT_SEQ_2_HI 0x28 |
| 60 | #define DSI_PKT_SEQ_3_LO 0x29 |
| 61 | #define DSI_PKT_SEQ_3_HI 0x2a |
| 62 | #define DSI_PKT_SEQ_4_LO 0x2b |
| 63 | #define DSI_PKT_SEQ_4_HI 0x2c |
| 64 | #define DSI_PKT_SEQ_5_LO 0x2d |
| 65 | #define DSI_PKT_SEQ_5_HI 0x2e |
| 66 | #define DSI_DCS_CMDS 0x33 |
| 67 | #define DSI_PKT_LEN_0_1 0x34 |
| 68 | #define DSI_PKT_LEN_2_3 0x35 |
| 69 | #define DSI_PKT_LEN_4_5 0x36 |
| 70 | #define DSI_PKT_LEN_6_7 0x37 |
| 71 | #define DSI_PHY_TIMING_0 0x3c |
| 72 | #define DSI_PHY_TIMING_1 0x3d |
| 73 | #define DSI_PHY_TIMING_2 0x3e |
| 74 | #define DSI_BTA_TIMING 0x3f |
| 75 | |
| 76 | #define DSI_TIMING_FIELD(value, period, hwinc) \ |
| 77 | ((DIV_ROUND_CLOSEST(value, period) - (hwinc)) & 0xff) |
| 78 | |
| 79 | #define DSI_TIMEOUT_0 0x44 |
| 80 | #define DSI_TIMEOUT_LRX(x) (((x) & 0xffff) << 16) |
| 81 | #define DSI_TIMEOUT_HTX(x) (((x) & 0xffff) << 0) |
| 82 | #define DSI_TIMEOUT_1 0x45 |
| 83 | #define DSI_TIMEOUT_PR(x) (((x) & 0xffff) << 16) |
| 84 | #define DSI_TIMEOUT_TA(x) (((x) & 0xffff) << 0) |
| 85 | #define DSI_TO_TALLY 0x46 |
| 86 | #define DSI_TALLY_TA(x) (((x) & 0xff) << 16) |
| 87 | #define DSI_TALLY_LRX(x) (((x) & 0xff) << 8) |
| 88 | #define DSI_TALLY_HTX(x) (((x) & 0xff) << 0) |
| 89 | #define DSI_PAD_CONTROL_0 0x4b |
| 90 | #define DSI_PAD_CONTROL_VS1_PDIO(x) (((x) & 0xf) << 0) |
| 91 | #define DSI_PAD_CONTROL_VS1_PDIO_CLK (1 << 8) |
| 92 | #define DSI_PAD_CONTROL_VS1_PULLDN(x) (((x) & 0xf) << 16) |
| 93 | #define DSI_PAD_CONTROL_VS1_PULLDN_CLK (1 << 24) |
| 94 | #define DSI_PAD_CONTROL_CD 0x4c |
| 95 | #define DSI_PAD_CD_STATUS 0x4d |
| 96 | #define DSI_VIDEO_MODE_CONTROL 0x4e |
| 97 | #define DSI_PAD_CONTROL_1 0x4f |
| 98 | #define DSI_PAD_CONTROL_2 0x50 |
| 99 | #define DSI_PAD_OUT_CLK(x) (((x) & 0x7) << 0) |
| 100 | #define DSI_PAD_LP_DN(x) (((x) & 0x7) << 4) |
| 101 | #define DSI_PAD_LP_UP(x) (((x) & 0x7) << 8) |
| 102 | #define DSI_PAD_SLEW_DN(x) (((x) & 0x7) << 12) |
| 103 | #define DSI_PAD_SLEW_UP(x) (((x) & 0x7) << 16) |
| 104 | #define DSI_PAD_CONTROL_3 0x51 |
| 105 | #define DSI_PAD_CONTROL_4 0x52 |
| 106 | #define DSI_GANGED_MODE_CONTROL 0x53 |
| 107 | #define DSI_GANGED_MODE_START 0x54 |
| 108 | #define DSI_GANGED_MODE_SIZE 0x55 |
| 109 | #define DSI_RAW_DATA_BYTE_COUNT 0x56 |
| 110 | #define DSI_ULTRA_LOW_POWER_CONTROL 0x57 |
| 111 | #define DSI_INIT_SEQ_DATA_8 0x58 |
| 112 | #define DSI_INIT_SEQ_DATA_9 0x59 |
| 113 | #define DSI_INIT_SEQ_DATA_10 0x5a |
| 114 | #define DSI_INIT_SEQ_DATA_11 0x5b |
| 115 | #define DSI_INIT_SEQ_DATA_12 0x5c |
| 116 | #define DSI_INIT_SEQ_DATA_13 0x5d |
| 117 | #define DSI_INIT_SEQ_DATA_14 0x5e |
| 118 | #define DSI_INIT_SEQ_DATA_15 0x5f |
| 119 | |
| 120 | #endif |