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gerrit-public.fairphone.software / kernel / msm-4.9 / 070ea8e1f5c7003aa463fdc511b9f898544a2a39 / . / arch / arm / boot / dts / qcom / sdxpoorwills-coresight.dtsi
blob: f8baa04ecee152ba1c96ffab2174b114d70b2b8f [file] [log] [blame]
Mao Jinlong9c7f4182018-01-11 20:48:58 +0800[diff] [blame]1/* Copyright (c) 2018, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13&soc {
14 csr: csr@6001000 {
15 compatible = "qcom,coresight-csr";
16 reg = <0x6001000 0x1000>;
17 reg-names = "csr-base";
18
19 coresight-name = "coresight-csr";
20
21 qcom,blk-size = <1>;
22 };
23
24 tmc_etr: tmc@6048000 {
25 compatible = "arm,primecell";
26 arm,primecell-periphid = <0x0003b961>;
27
28 reg = <0x6048000 0x1000>,
29 <0x6064000 0x15000>;
30 reg-names = "tmc-base", "bam-base";
31
32 arm,buffer-size = <0x400000>;
33 arm,sg-enable;
34
35 coresight-name = "coresight-tmc-etr";
36 coresight-ctis = <&cti0 &cti8>;
37
38 clocks = <&clock_aop QDSS_CLK>;
39 clock-names = "apb_pclk";
40
41 interrupts = <GIC_SPI 251 IRQ_TYPE_EDGE_RISING>;
42 interrupt-names = "byte-cntr-irq";
43
44 port {
45 tmc_etr_in_replicator: endpoint {
46 slave-mode;
47 remote-endpoint = <&replicator_out_tmc_etr>;
48 };
49 };
50 };
51
52 replicator_qdss: replicator@6046000 {
53 compatible = "arm,primecell";
54 arm,primecell-periphid = <0x0003b909>;
55
56 reg = <0x6046000 0x1000>;
57 reg-names = "replicator-base";
58
59 coresight-name = "coresight-replicator";
60
61 clocks = <&clock_aop QDSS_CLK>;
62 clock-names = "apb_pclk";
63
64 ports {
65 #address-cells = <1>;
66 #size-cells = <0>;
67
68 port@0 {
69 reg = <0>;
70 replicator_out_tmc_etr: endpoint {
71 remote-endpoint=
72 <&tmc_etr_in_replicator>;
73 };
74 };
75
76 port@1 {
77 reg = <0>;
78 replicator_in_tmc_etf: endpoint {
79 slave-mode;
80 remote-endpoint=
81 <&tmc_etf_out_replicator>;
82 };
83 };
84 };
85 };
86
87 tmc_etf: tmc@6047000 {
88 compatible = "arm,primecell";
89 arm,primecell-periphid = <0x0003b961>;
90
91 reg = <0x6047000 0x1000>;
92 reg-names = "tmc-base";
93
94 coresight-name = "coresight-tmc-etf";
95 coresight-ctis = <&cti0 &cti8>;
96 arm,default-sink;
97
98 clocks = <&clock_aop QDSS_CLK>;
99 clock-names = "apb_pclk";
100
101 ports {
102 #address-cells = <1>;
103 #size-cells = <0>;
104
105 port@0 {
106 reg = <0>;
107 tmc_etf_out_replicator: endpoint {
108 remote-endpoint =
109 <&replicator_in_tmc_etf>;
110 };
111 };
112
113 port@1 {
114 reg = <0>;
115 tmc_etf_in_funnel_merg: endpoint {
116 slave-mode;
117 remote-endpoint =
118 <&funnel_merg_out_tmc_etf>;
119 };
120 };
121 };
122 };
123
124 funnel_merg: funnel@6045000 {
125 compatible = "arm,primecell";
126 arm,primecell-periphid = <0x0003b908>;
127
128 reg = <0x6045000 0x1000>;
129 reg-names = "funnel-base";
130
131 coresight-name = "coresight-funnel-merg";
132
133 clocks = <&clock_aop QDSS_CLK>;
134 clock-names = "apb_pclk";
135
136 ports {
137 #address-cells = <1>;
138 #size-cells = <0>;
139
140 port@0 {
141 reg = <0>;
142 funnel_merg_out_tmc_etf: endpoint {
143 remote-endpoint =
144 <&tmc_etf_in_funnel_merg>;
145 };
146 };
147
148 port@1 {
149 reg = <0>;
150 funnel_merg_in_funnel_in0: endpoint {
151 slave-mode;
152 remote-endpoint =
153 <&funnel_in0_out_funnel_merg>;
154 };
155 };
156
157 port@2 {
158 reg = <1>;
159 funnel_merg_in_funnel_in1: endpoint {
160 slave-mode;
161 remote-endpoint =
162 <&funnel_in1_out_funnel_merg>;
163 };
164 };
165 };
166 };
167
168 funnel_in0: funnel@6041000 {
169 compatible = "arm,primecell";
170 arm,primecell-periphid = <0x0003b908>;
171
172 reg = <0x6041000 0x1000>;
173 reg-names = "funnel-base";
174
175 coresight-name = "coresight-funnel-in0";
176
177 clocks = <&clock_aop QDSS_CLK>;
178 clock-names = "apb_pclk";
179
180 ports {
181 #address-cells = <1>;
182 #size-cells = <0>;
183
184 port@0 {
185 reg = <0>;
186 funnel_in0_out_funnel_merg: endpoint {
187 remote-endpoint =
188 <&funnel_merg_in_funnel_in0>;
189 };
190 };
191
192 port@1 {
193 reg = <6>;
194 funnel_in0_in_funnel_qatb: endpoint {
195 slave-mode;
196 remote-endpoint =
197 <&funnel_qatb_out_funnel_in0>;
198 };
199 };
200
201 port@2 {
202 reg = <7>;
203 funnel_in0_in_stm: endpoint {
204 slave-mode;
205 remote-endpoint = <&stm_out_funnel_in0>;
206 };
207 };
208 };
209 };
210
211 stm: stm@6002000 {
212 compatible = "arm,primecell";
213 arm,primecell-periphid = <0x0003b962>;
214
215 reg = <0x6002000 0x1000>,
216 <0x16280000 0x180000>;
217 reg-names = "stm-base", "stm-stimulus-base";
218
219 coresight-name = "coresight-stm";
220
221 clocks = <&clock_aop QDSS_CLK>;
222 clock-names = "apb_pclk";
223
224 port {
225 stm_out_funnel_in0: endpoint {
226 remote-endpoint = <&funnel_in0_in_stm>;
227 };
228 };
229
230 };
231
232 funnel_qatb: funnel@6005000 {
233 compatible = "arm,primecell";
234 arm,primecell-periphid = <0x0003b908>;
235
236 reg = <0x6005000 0x1000>;
237 reg-names = "funnel-base";
238
239 coresight-name = "coresight-funnel-qatb";
240
241 clocks = <&clock_aop QDSS_CLK>;
242 clock-names = "apb_pclk";
243
244 ports {
245 #address-cells = <1>;
246 #size-cells = <0>;
247
248 port@0 {
249 reg = <0>;
250 funnel_qatb_out_funnel_in0: endpoint {
251 remote-endpoint =
252 <&funnel_in0_in_funnel_qatb>;
253 };
254 };
255
256 port@1 {
257 reg = <0>;
258 funnel_qatb_in_tpda: endpoint {
259 slave-mode;
260 remote-endpoint =
261 <&tpda_out_funnel_qatb>;
262 };
263 };
264 };
265 };
266
267 tpda: tpda@6004000 {
268 compatible = "arm,primecell";
269 arm,primecell-periphid = <0x0003b969>;
270 reg = <0x6004000 0x1000>;
271 reg-names = "tpda-base";
272
273 coresight-name = "coresight-tpda";
274
275 qcom,tpda-atid = <65>;
276 qcom,bc-elem-size = <10 32>,
277 <13 32>;
278 qcom,tc-elem-size = <13 32>;
279 qcom,dsb-elem-size = <0 32>,
280 <2 32>,
281 <3 32>,
282 <5 32>,
283 <6 32>,
284 <10 32>,
285 <11 32>,
286 <13 32>;
287 qcom,cmb-elem-size = <3 64>,
288 <7 64>,
289 <9 64>,
290 <13 64>;
291
292 clocks = <&clock_aop QDSS_CLK>;
293 clock-names = "apb_pclk";
294
295 ports {
296 #address-cells = <1>;
297 #size-cells = <0>;
298 port@0 {
299 reg = <0>;
300 tpda_out_funnel_qatb: endpoint {
301 remote-endpoint =
302 <&funnel_qatb_in_tpda>;
303 };
304
305 };
306
307 port@1 {
308 reg = <0>;
309 tpda_in_funnel_ddr_0: endpoint {
310 slave-mode;
311 remote-endpoint =
312 <&funnel_ddr_0_out_tpda>;
313 };
314 };
315
316 port@2 {
317 reg = <1>;
318 tpda_in_tpdm_vsense: endpoint {
319 slave-mode;
320 remote-endpoint =
321 <&tpdm_vsense_out_tpda>;
322 };
323 };
324
325 port@3 {
326 reg = <2>;
327 tpda_in_tpdm_dcc: endpoint {
328 slave-mode;
329 remote-endpoint =
330 <&tpdm_dcc_out_tpda>;
331 };
332 };
333
334 port@4 {
335 reg = <5>;
336 tpda_in_tpdm_center: endpoint {
337 slave-mode;
338 remote-endpoint =
339 <&tpdm_center_out_tpda>;
340 };
341 };
342 };
343 };
344
345 funnel_ddr_0: funnel@69e2000 {
346 compatible = "arm,primecell";
347 arm,primecell-periphid = <0x0003b908>;
348
349 reg = <0x69e2000 0x1000>;
350 reg-names = "funnel-base";
351
352 coresight-name = "coresight-funnel-ddr-0";
353
354 clocks = <&clock_aop QDSS_CLK>;
355 clock-names = "apb_pclk";
356
357 ports {
358 #address-cells = <1>;
359 #size-cells = <0>;
360
361 port@0 {
362 reg = <0>;
363 funnel_ddr_0_out_tpda: endpoint {
364 remote-endpoint =
365 <&tpda_in_funnel_ddr_0>;
366 };
367 };
368
369 port@1 {
370 reg = <0>;
371 funnel_ddr_0_in_tpdm_ddr: endpoint {
372 slave-mode;
373 remote-endpoint =
374 <&tpdm_ddr_out_funnel_ddr_0>;
375 };
376 };
377 };
378 };
379
380 tpdm_dcc: tpdm@6870280 {
381 compatible = "arm,primecell";
382 arm,primecell-periphid = <0x0003b968>;
383 reg = <0x6870280 0x1000>;
384 reg-names = "tpdm-base";
385
386 coresight-name = "coresight-tpdm-dcc";
387
388 clocks = <&clock_aop QDSS_CLK>;
389 clock-names = "apb_pclk";
390
391 port{
392 tpdm_dcc_out_tpda: endpoint {
393 remote-endpoint = <&tpda_in_tpdm_dcc>;
394 };
395 };
396 };
397
398 tpdm_vsense: tpdm@6840000 {
399 compatible = "arm,primecell";
400 arm,primecell-periphid = <0x0003b968>;
401 reg = <0x6840000 0x1000>;
402 reg-names = "tpdm-base";
403
404 coresight-name = "coresight-tpdm-vsense";
405
406 clocks = <&clock_aop QDSS_CLK>;
407 clock-names = "apb_pclk";
408
409 port{
410 tpdm_vsense_out_tpda: endpoint {
411 remote-endpoint = <&tpda_in_tpdm_vsense>;
412 };
413 };
414 };
415
416 tpdm_center: tpdm@6c28000 {
417 compatible = "arm,primecell";
418 arm,primecell-periphid = <0x0003b968>;
419 reg = <0x6c28000 0x1000>;
420 reg-names = "tpdm-base";
421
422 coresight-name = "coresight-tpdm-center";
423
424 clocks = <&clock_aop QDSS_CLK>;
425 clock-names = "apb_pclk";
426
427 port{
428 tpdm_center_out_tpda: endpoint {
429 remote-endpoint = <&tpda_in_tpdm_center>;
430 };
431 };
432 };
433
434 tpdm_ddr: tpdm@69e0000 {
435 compatible = "arm,primecell";
436 arm,primecell-periphid = <0x0003b968>;
437 reg = <0x69e0000 0x1000>;
438 reg-names = "tpdm-base";
439
440 coresight-name = "coresight-tpdm-ddr";
441
442 clocks = <&clock_aop QDSS_CLK>;
443 clock-names = "apb_pclk";
444
445 qcom,msr-fix-req;
446
447 port {
448 tpdm_ddr_out_funnel_ddr_0: endpoint {
449 remote-endpoint = <&funnel_ddr_0_in_tpdm_ddr>;
450 };
451 };
452 };
453
454 funnel_in1: funnel@6042000 {
455 compatible = "arm,primecell";
456 arm,primecell-periphid = <0x0003b908>;
457
458 reg = <0x6042000 0x1000>;
459 reg-names = "funnel-base";
460
461 coresight-name = "coresight-funnel-in1";
462
463 clocks = <&clock_aop QDSS_CLK>;
464 clock-names = "apb_pclk";
465
466 ports {
467 #address-cells = <1>;
468 #size-cells = <0>;
469
470 port@0 {
471 reg = <0>;
472 funnel_in1_out_funnel_merg: endpoint {
473 remote-endpoint =
474 <&funnel_merg_in_funnel_in1>;
475 };
476 };
477
478 port@1 {
479 reg = <2>;
480 funnel_in1_in_funnel_swao: endpoint {
481 slave-mode;
482 remote-endpoint =
483 <&funnel_swao_out_funnel_in1>;
484 };
485 };
486
487 port@2 {
488 reg = <3>;
489 funnel_in1_in_modem_etm0: endpoint {
490 slave-mode;
491 remote-endpoint =
492 <&modem_etm0_out_funnel_in1>;
493 };
494 };
495
496 port@3 {
497 reg = <7>;
498 funnel_in1_in_tpda_modem: endpoint {
499 slave-mode;
500 remote-endpoint =
501 <&tpda_modem_out_funnel_in1>;
502 };
503 };
504 };
505 };
506
507 modem_etm0 {
508 compatible = "qcom,coresight-remote-etm";
509
510 coresight-name = "coresight-modem-etm0";
511 qcom,inst-id = <2>;
512
513 port {
514 modem_etm0_out_funnel_in1: endpoint {
515 remote-endpoint =
516 <&funnel_in1_in_modem_etm0>;
517 };
518 };
519 };
520
521 funnel_swao:funnel@6b08000 {
522 compatible = "arm,primecell";
523 arm,primecell-periphid = <0x0003b908>;
524
525 reg = <0x6b08000 0x1000>;
526 reg-names = "funnel-base";
527
528 coresight-name = "coresight-funnel-swao";
529
530 clocks = <&clock_aop QDSS_CLK>;
531 clock-names = "apb_pclk";
532
533 ports {
534 #address-cells = <1>;
535 #size-cells = <0>;
536
537 port@0 {
538 reg = <0>;
539 funnel_swao_out_funnel_in1: endpoint {
540 remote-endpoint =
541 <&funnel_in1_in_funnel_swao>;
542 };
543 };
544
545 port@1 {
546 reg = <7>;
547 funnel_swao_in_tpda_swao: endpoint {
548 slave-mode;
549 remote-endpoint=
550 <&tpda_swao_out_funnel_swao>;
551 };
552 };
553 };
554 };
555
556 tpda_modem: tpda@6832000 {
557 compatible = "arm,primecell";
558 arm,primecell-periphid = <0x0003b969>;
559 reg = <0x6832000 0x1000>;
560 reg-names = "tpda-base";
561
562 coresight-name = "coresight-tpda-modem";
563
564 qcom,tpda-atid = <67>;
565 qcom,dsb-elem-size = <0 32>;
566 qcom,cmb-elem-size = <0 64>;
567
568 clocks = <&clock_aop QDSS_CLK>;
569 clock-names = "apb_pclk";
570
571 ports {
572 #address-cells = <1>;
573 #size-cells = <0>;
574 port@0 {
575 reg = <0>;
576 tpda_modem_out_funnel_in1: endpoint {
577 remote-endpoint =
578 <&funnel_in1_in_tpda_modem>;
579 };
580 };
581
582 port@1 {
583 reg = <0>;
584 tpda_modem_in_tpdm_modem: endpoint {
585 slave-mode;
586 remote-endpoint =
587 <&tpdm_modem_out_tpda_modem>;
588 };
589 };
590 };
591 };
592
593 tpdm_modem: tpdm@6830000 {
594 compatible = "arm,primecell";
595 arm,primecell-periphid = <0x0003b968>;
596 reg = <0x6830000 0x1000>;
597 reg-names = "tpdm-base";
598
599 coresight-name = "coresight-tpdm-modem";
600
601 clocks = <&clock_aop QDSS_CLK>;
602 clock-names = "apb_pclk";
603
604 port {
605 tpdm_modem_out_tpda_modem: endpoint {
606 remote-endpoint = <&tpda_modem_in_tpdm_modem>;
607 };
608 };
609 };
610
611 tpda_swao: tpda@6b01000 {
612 compatible = "arm,primecell";
613 arm,primecell-periphid = <0x0003b969>;
614 reg = <0x6b01000 0x1000>;
615 reg-names = "tpda-base";
616
617 coresight-name = "coresight-tpda-swao";
618
619 qcom,tpda-atid = <71>;
620 qcom,dsb-elem-size = <1 32>;
621 qcom,cmb-elem-size = <0 64>;
622
623 clocks = <&clock_aop QDSS_CLK>;
624 clock-names = "apb_pclk";
625
626 ports {
627 #address-cells = <1>;
628 #size-cells = <0>;
629
630 port@0 {
631 reg = <0>;
632 tpda_swao_out_funnel_swao: endpoint {
633 remote-endpoint =
634 <&funnel_swao_in_tpda_swao>;
635 };
636
637 };
638
639 port@1 {
640 reg = <0>;
641 tpda_swao_in_tpdm_swao0: endpoint {
642 slave-mode;
643 remote-endpoint =
644 <&tpdm_swao0_out_tpda_swao>;
645 };
646 };
647
648 port@2 {
649 reg = <1>;
650 tpda_swao_in_tpdm_swao1: endpoint {
651 slave-mode;
652 remote-endpoint =
653 <&tpdm_swao1_out_tpda_swao>;
654 };
655
656 };
657 };
658 };
659
660 tpdm_swao0: tpdm@6b02000 {
661 compatible = "arm,primecell";
662 arm,primecell-periphid = <0x0003b968>;
663
664 reg = <0x6b02000 0x1000>;
665 reg-names = "tpdm-base";
666
667 coresight-name = "coresight-tpdm-swao-0";
668
669 clocks = <&clock_aop QDSS_CLK>;
670 clock-names = "apb_pclk";
671
672 port {
673 tpdm_swao0_out_tpda_swao: endpoint {
674 remote-endpoint = <&tpda_swao_in_tpdm_swao0>;
675 };
676 };
677 };
678
679 tpdm_swao1: tpdm@6b03000 {
680 compatible = "arm,primecell";
681 arm,primecell-periphid = <0x0003b968>;
682 reg = <0x6b03000 0x1000>;
683 reg-names = "tpdm-base";
684
685 coresight-name="coresight-tpdm-swao-1";
686
687 clocks = <&clock_aop QDSS_CLK>;
688 clock-names = "apb_pclk";
689
690 qcom,msr-fix-req;
691
692 port {
693 tpdm_swao1_out_tpda_swao: endpoint {
694 remote-endpoint = <&tpda_swao_in_tpdm_swao1>;
695 };
696 };
697 };
698
699 ipcb_tgu: tgu@6b0c000 {
700 compatible = "arm,primecell";
701 arm,primecell-periphid = <0x0003b999>;
702 reg = <0x6b0c000 0x1000>;
703 reg-names = "tgu-base";
704 tgu-steps = <3>;
705 tgu-conditions = <4>;
706 tgu-regs = <4>;
707 tgu-timer-counters = <8>;
708
709 coresight-name = "coresight-tgu-ipcb";
710
711 clocks = <&clock_aop QDSS_CLK>;
712 clock-names = "apb_pclk";
713 };
714
715 cti0: cti@6010000 {
716 compatible = "arm,primecell";
717 arm,primecell-periphid = <0x0003b966>;
718 reg = <0x6010000 0x1000>;
719 reg-names = "cti-base";
720
721 coresight-name = "coresight-cti0";
722
723 clocks = <&clock_aop QDSS_CLK>;
724 clock-names = "apb_pclk";
725
726 };
727
728 cti1: cti@6011000 {
729 compatible = "arm,primecell";
730 arm,primecell-periphid = <0x0003b966>;
731 reg = <0x6011000 0x1000>;
732 reg-names = "cti-base";
733
734 coresight-name = "coresight-cti1";
735
736 clocks = <&clock_aop QDSS_CLK>;
737 clock-names = "apb_pclk";
738
739 };
740
741 cti2: cti@6012000 {
742 compatible = "arm,primecell";
743 arm,primecell-periphid = <0x0003b966>;
744 reg = <0x6012000 0x1000>;
745 reg-names = "cti-base";
746
747 coresight-name = "coresight-cti2";
748
749 clocks = <&clock_aop QDSS_CLK>;
750 clock-names = "apb_pclk";
751 };
752
753 cti3: cti@6013000 {
754 compatible = "arm,primecell";
755 arm,primecell-periphid = <0x0003b966>;
756 reg = <0x6013000 0x1000>;
757 reg-names = "cti-base";
758
759 coresight-name = "coresight-cti3";
760
761 clocks = <&clock_aop QDSS_CLK>;
762 clock-names = "apb_pclk";
763
764 };
765
766 cti4: cti@6014000 {
767 compatible = "arm,primecell";
768 arm,primecell-periphid = <0x0003b966>;
769 reg = <0x6014000 0x1000>;
770 reg-names = "cti-base";
771
772 coresight-name = "coresight-cti4";
773
774 clocks = <&clock_aop QDSS_CLK>;
775 clock-names = "apb_pclk";
776
777 };
778
779 cti5: cti@6015000 {
780 compatible = "arm,primecell";
781 arm,primecell-periphid = <0x0003b966>;
782 reg = <0x6015000 0x1000>;
783 reg-names = "cti-base";
784
785 coresight-name = "coresight-cti5";
786
787 clocks = <&clock_aop QDSS_CLK>;
788 clock-names = "apb_pclk";
789
790 };
791
792 cti6: cti@6016000 {
793 compatible = "arm,primecell";
794 arm,primecell-periphid = <0x0003b966>;
795 reg = <0x6016000 0x1000>;
796 reg-names = "cti-base";
797
798 coresight-name = "coresight-cti6";
799
800 clocks = <&clock_aop QDSS_CLK>;
801 clock-names = "apb_pclk";
802
803 };
804
805 cti7: cti@6017000 {
806 compatible = "arm,primecell";
807 arm,primecell-periphid = <0x0003b966>;
808 reg = <0x6017000 0x1000>;
809 reg-names = "cti-base";
810
811 coresight-name = "coresight-cti7";
812
813 clocks = <&clock_aop QDSS_CLK>;
814 clock-names = "apb_pclk";
815
816 };
817
818 cti8: cti@6018000 {
819 compatible = "arm,primecell";
820 arm,primecell-periphid = <0x0003b966>;
821 reg = <0x6018000 0x1000>;
822 reg-names = "cti-base";
823
824 coresight-name = "coresight-cti8";
825
826 clocks = <&clock_aop QDSS_CLK>;
827 clock-names = "apb_pclk";
828
829 };
830
831 cti9: cti@6019000 {
832 compatible = "arm,primecell";
833 arm,primecell-periphid = <0x0003b966>;
834 reg = <0x6019000 0x1000>;
835 reg-names = "cti-base";
836
837 coresight-name = "coresight-cti9";
838
839 clocks = <&clock_aop QDSS_CLK>;
840 clock-names = "apb_pclk";
841
842 };
843
844 cti10: cti@601a000 {
845 compatible = "arm,primecell";
846 arm,primecell-periphid = <0x0003b966>;
847 reg = <0x601a000 0x1000>;
848 reg-names = "cti-base";
849
850 coresight-name = "coresight-cti10";
851
852 clocks = <&clock_aop QDSS_CLK>;
853 clock-names = "apb_pclk";
854
855 };
856
857 cti11: cti@601b000 {
858 compatible = "arm,primecell";
859 arm,primecell-periphid = <0x0003b966>;
860 reg = <0x601b000 0x1000>;
861 reg-names = "cti-base";
862
863 coresight-name = "coresight-cti11";
864
865 clocks = <&clock_aop QDSS_CLK>;
866 clock-names = "apb_pclk";
867
868 };
869
870 cti12: cti@601c000 {
871 compatible = "arm,primecell";
872 arm,primecell-periphid = <0x0003b966>;
873 reg = <0x601c000 0x1000>;
874 reg-names = "cti-base";
875
876 coresight-name = "coresight-cti12";
877
878 clocks = <&clock_aop QDSS_CLK>;
879 clock-names = "apb_pclk";
880
881 };
882
883 cti13: cti@601d000 {
884 compatible = "arm,primecell";
885 arm,primecell-periphid = <0x0003b966>;
886 reg = <0x601d000 0x1000>;
887 reg-names = "cti-base";
888
889 coresight-name = "coresight-cti13";
890
891 clocks = <&clock_aop QDSS_CLK>;
892 clock-names = "apb_pclk";
893
894 };
895
896 cti14: cti@601e000 {
897 compatible = "arm,primecell";
898 arm,primecell-periphid = <0x0003b966>;
899 reg = <0x601e000 0x1000>;
900 reg-names = "cti-base";
901
902 coresight-name = "coresight-cti14";
903
904 clocks = <&clock_aop QDSS_CLK>;
905 clock-names = "apb_pclk";
906
907 };
908
909 cti15: cti@601f000 {
910 compatible = "arm,primecell";
911 arm,primecell-periphid = <0x0003b966>;
912 reg = <0x601f000 0x1000>;
913 reg-names = "cti-base";
914
915 coresight-name = "coresight-cti15";
916
917 clocks = <&clock_aop QDSS_CLK>;
918 clock-names = "apb_pclk";
919
920 };
921
922 cti_cpu0: cti@7003000 {
923 compatible = "arm,primecell";
924 arm,primecell-periphid = <0x0003b966>;
925 reg = <0x7003000 0x1000>;
926 reg-names = "cti-base";
927
928 coresight-name = "coresight-cti-cpu0";
929 cpu = <&CPU0>;
930
931 clocks = <&clock_aop QDSS_CLK>;
932 clock-names = "apb_pclk";
933
934 };
935
936 cti_modem_cpu0:cti@6837000 {
937 compatible = "arm,primecell";
938 arm,primecell-periphid = <0x0003b966>;
939 reg = <0x6837000 0x1000>;
940 reg-names = "cti-base";
941
942 coresight-name = "coresight-cti-modem-cpu0";
943
944 clocks = <&clock_aop QDSS_CLK>;
945 clock-names = "apb_pclk";
946 };
947
948 cti_modem_cpu1:cti@683b000 {
949 compatible = "arm,primecell";
950 arm,primecell-periphid = <0x0003b966>;
951 reg = <0x683b000 0x1000>;
952 reg-names = "cti-base";
953
954 coresight-name = "coresight-cti-modem-cpu1";
955
956 clocks = <&clock_aop QDSS_CLK>;
957 clock-names = "apb_pclk";
958 };
959
960 cti0_swao:cti@6b04000 {
961 compatible = "arm,primecell";
962 arm,primecell-periphid = <0x0003b966>;
963 reg = <0x6b04000 0x1000>;
964 reg-names = "cti-base";
965
966 coresight-name = "coresight-cti-swao_cti0";
967
968 clocks = <&clock_aop QDSS_CLK>;
969 clock-names = "apb_pclk";
970 };
971
972 cti1_swao:cti@6b05000 {
973 compatible = "arm,primecell";
974 arm,primecell-periphid = <0x0003b966>;
975 reg = <0x6b05000 0x1000>;
976 reg-names = "cti-base";
977
978 coresight-name = "coresight-cti-swao_cti1";
979
980 clocks = <&clock_aop QDSS_CLK>;
981 clock-names = "apb_pclk";
982 };
983
984 cti2_swao:cti@6b06000 {
985 compatible = "arm,primecell";
986 arm,primecell-periphid = <0x0003b966>;
987 reg = <0x6b06000 0x1000>;
988 reg-names = "cti-base";
989
990 coresight-name = "coresight-cti-swao_cti2";
991
992 clocks = <&clock_aop QDSS_CLK>;
993 clock-names = "apb_pclk";
994 };
995
996 cti3_swao:cti@6b07000 {
997 compatible = "arm,primecell";
998 arm,primecell-periphid = <0x0003b966>;
999 reg = <0x6b07000 0x1000>;
1000 reg-names = "cti-base";
1001
1002 coresight-name = "coresight-cti-swao_cti3";
1003
1004 clocks = <&clock_aop QDSS_CLK>;
1005 clock-names = "apb_pclk";
1006 };
1007
1008 cti0_ddr0: cti@69e1000 {
1009 compatible = "arm,primecell";
1010 arm,primecell-periphid = <0x0003b966>;
1011 reg = <0x69e1000 0x1000>;
1012 reg-names = "cti-base";
1013
1014 coresight-name = "coresight-cti-ddr_dl_0_cti";
1015
1016 clocks = <&clock_aop QDSS_CLK>;
1017 clock-names = "apb_pclk";
1018 };
1019
1020 cti0_ddr1: cti@69e4000 {
1021 compatible = "arm,primecell";
1022 arm,primecell-periphid = <0x0003b966>;
1023 reg = <0x69e4000 0x1000>;
1024 reg-names = "cti-base";
1025
1026 coresight-name = "coresight-cti-ddr_dl_1_cti0";
1027
1028 clocks = <&clock_aop QDSS_CLK>;
1029 clock-names = "apb_pclk";
1030 };
1031
1032 cti1_ddr1: cti@69e5000 {
1033 compatible = "arm,primecell";
1034 arm,primecell-periphid = <0x0003b966>;
1035 reg = <0x69e5000 0x1000>;
1036 reg-names = "cti-base";
1037
1038 coresight-name = "coresight-cti-ddr_dl_1_cti1";
1039
1040 clocks = <&clock_aop QDSS_CLK>;
1041 clock-names = "apb_pclk";
1042 };
1043
1044 cti2_ddr1: cti@69e6000 {
1045 compatible = "arm,primecell";
1046 arm,primecell-periphid = <0x0003b966>;
1047 reg = <0x69e6000 0x1000>;
1048 reg-names = "cti-base";
1049
1050 coresight-name = "coresight-cti-ddr_dl_1_cti2";
1051
1052 clocks = <&clock_aop QDSS_CLK>;
1053 clock-names = "apb_pclk";
1054 };
1055
1056 hwevent: hwevent@0x014066f0 {
1057 compatible = "qcom,coresight-hwevent";
1058 reg = <0x14066f0 0x4>,
1059 <0x14166f0 0x4>,
1060 <0x1406038 0x4>,
1061 <0x1416038 0x4>;
1062 reg-names = "ddr-ch0-cfg", "ddr-ch23-cfg", "ddr-ch0-ctrl",
1063 "ddr-ch23-ctrl";
1064
1065 coresight-name = "coresight-hwevent";
1066
1067 clocks = <&clock_aop QDSS_CLK>;
1068 clock-names = "apb_pclk";
1069 };
1070};