Mukesh Kumar Savaliya | d08d4b2 | 2018-01-08 17:13:33 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
Girish Mahadevan | 57e4771 | 2017-04-19 16:55:10 -0600 | [diff] [blame] | 13 | #include <dt-bindings/msm/msm-bus-ids.h> |
| 14 | |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 15 | &soc { |
| 16 | /* QUPv3 South instances */ |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 17 | qupv3_0: qcom,qupv3_0_geni_se@8c0000 { |
| 18 | compatible = "qcom,qupv3-geni-se"; |
| 19 | reg = <0x8c0000 0x6000>; |
| 20 | qcom,bus-mas-id = <MSM_BUS_MASTER_BLSP_1>; |
| 21 | qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>; |
| 22 | qcom,iommu-s1-bypass; |
| 23 | |
| 24 | iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb { |
| 25 | compatible = "qcom,qupv3-geni-se-cb"; |
| 26 | iommus = <&apps_smmu 0x003 0x0>; |
| 27 | }; |
| 28 | }; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 29 | |
| 30 | /* |
| 31 | * HS UART instances. HS UART usecases can be supported on these |
| 32 | * instances only. |
| 33 | */ |
| 34 | qupv3_se6_4uart: qcom,qup_uart@0x898000 { |
Mukesh Kumar Savaliya | d08d4b2 | 2018-01-08 17:13:33 +0530 | [diff] [blame] | 35 | compatible = "qcom,msm-geni-serial-hs"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 36 | reg = <0x898000 0x4000>; |
| 37 | reg-names = "se_phys"; |
| 38 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 39 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, |
| 40 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 41 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 42 | pinctrl-names = "default", "sleep"; |
| 43 | pinctrl-0 = <&qupv3_se6_4uart_active>; |
| 44 | pinctrl-1 = <&qupv3_se6_4uart_sleep>; |
Archana Sathyakumar | 00a36ab | 2017-03-03 14:38:26 -0700 | [diff] [blame] | 45 | interrupts-extended = <&pdc GIC_SPI 607 0>, |
Girish Mahadevan | 1d38bd3 | 2017-04-11 17:59:47 -0600 | [diff] [blame] | 46 | <&tlmm 48 0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 47 | status = "disabled"; |
Girish Mahadevan | 1d38bd3 | 2017-04-11 17:59:47 -0600 | [diff] [blame] | 48 | qcom,wakeup-byte = <0xFD>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 49 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 50 | }; |
| 51 | |
| 52 | qupv3_se7_4uart: qcom,qup_uart@0x89c000 { |
Mukesh Kumar Savaliya | d08d4b2 | 2018-01-08 17:13:33 +0530 | [diff] [blame] | 53 | compatible = "qcom,msm-geni-serial-hs"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 54 | reg = <0x89c000 0x4000>; |
| 55 | reg-names = "se_phys"; |
| 56 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 57 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, |
| 58 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 59 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 60 | pinctrl-names = "default", "sleep"; |
| 61 | pinctrl-0 = <&qupv3_se7_4uart_active>; |
| 62 | pinctrl-1 = <&qupv3_se7_4uart_sleep>; |
Archana Sathyakumar | 00a36ab | 2017-03-03 14:38:26 -0700 | [diff] [blame] | 63 | interrupts-extended = <&pdc GIC_SPI 608 0>, |
Girish Mahadevan | 1d38bd3 | 2017-04-11 17:59:47 -0600 | [diff] [blame] | 64 | <&tlmm 96 0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 65 | status = "disabled"; |
Girish Mahadevan | 1d38bd3 | 2017-04-11 17:59:47 -0600 | [diff] [blame] | 66 | qcom,wakeup-byte = <0xFD>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 67 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 68 | }; |
| 69 | |
| 70 | /* I2C */ |
| 71 | qupv3_se0_i2c: i2c@880000 { |
| 72 | compatible = "qcom,i2c-geni"; |
| 73 | reg = <0x880000 0x4000>; |
| 74 | interrupts = <GIC_SPI 601 0>; |
| 75 | #address-cells = <1>; |
| 76 | #size-cells = <0>; |
| 77 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 78 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, |
| 79 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 80 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
Sagar Dharia | 82bf858 | 2017-04-15 13:17:49 -0600 | [diff] [blame] | 81 | dmas = <&gpi_dma0 0 0 3 64 0>, |
| 82 | <&gpi_dma0 1 0 3 64 0>; |
| 83 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 84 | pinctrl-names = "default", "sleep"; |
| 85 | pinctrl-0 = <&qupv3_se0_i2c_active>; |
| 86 | pinctrl-1 = <&qupv3_se0_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 87 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 88 | status = "disabled"; |
| 89 | }; |
| 90 | |
| 91 | qupv3_se1_i2c: i2c@884000 { |
| 92 | compatible = "qcom,i2c-geni"; |
| 93 | reg = <0x884000 0x4000>; |
| 94 | interrupts = <GIC_SPI 602 0>; |
| 95 | #address-cells = <1>; |
| 96 | #size-cells = <0>; |
| 97 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 98 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, |
| 99 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 100 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
Sagar Dharia | 82bf858 | 2017-04-15 13:17:49 -0600 | [diff] [blame] | 101 | dmas = <&gpi_dma0 0 1 3 64 0>, |
| 102 | <&gpi_dma0 1 1 3 64 0>; |
| 103 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 104 | pinctrl-names = "default", "sleep"; |
| 105 | pinctrl-0 = <&qupv3_se1_i2c_active>; |
| 106 | pinctrl-1 = <&qupv3_se1_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 107 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 108 | status = "disabled"; |
| 109 | }; |
| 110 | |
| 111 | qupv3_se2_i2c: i2c@888000 { |
| 112 | compatible = "qcom,i2c-geni"; |
| 113 | reg = <0x888000 0x4000>; |
| 114 | interrupts = <GIC_SPI 603 0>; |
| 115 | #address-cells = <1>; |
| 116 | #size-cells = <0>; |
| 117 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 118 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, |
| 119 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 120 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
Sagar Dharia | 82bf858 | 2017-04-15 13:17:49 -0600 | [diff] [blame] | 121 | dmas = <&gpi_dma0 0 2 3 64 0>, |
| 122 | <&gpi_dma0 1 2 3 64 0>; |
| 123 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 124 | pinctrl-names = "default", "sleep"; |
| 125 | pinctrl-0 = <&qupv3_se2_i2c_active>; |
| 126 | pinctrl-1 = <&qupv3_se2_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 127 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 128 | status = "disabled"; |
| 129 | }; |
| 130 | |
| 131 | qupv3_se3_i2c: i2c@88c000 { |
| 132 | compatible = "qcom,i2c-geni"; |
| 133 | reg = <0x88c000 0x4000>; |
| 134 | interrupts = <GIC_SPI 604 0>; |
| 135 | #address-cells = <1>; |
| 136 | #size-cells = <0>; |
| 137 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 138 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, |
| 139 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 140 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
Sagar Dharia | 82bf858 | 2017-04-15 13:17:49 -0600 | [diff] [blame] | 141 | dmas = <&gpi_dma0 0 3 3 64 0>, |
| 142 | <&gpi_dma0 1 3 3 64 0>; |
| 143 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 144 | pinctrl-names = "default", "sleep"; |
| 145 | pinctrl-0 = <&qupv3_se3_i2c_active>; |
| 146 | pinctrl-1 = <&qupv3_se3_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 147 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 148 | status = "disabled"; |
| 149 | }; |
| 150 | |
| 151 | qupv3_se4_i2c: i2c@890000 { |
| 152 | compatible = "qcom,i2c-geni"; |
| 153 | reg = <0x890000 0x4000>; |
| 154 | interrupts = <GIC_SPI 605 0>; |
| 155 | #address-cells = <1>; |
| 156 | #size-cells = <0>; |
| 157 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 158 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, |
| 159 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 160 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
Sagar Dharia | 82bf858 | 2017-04-15 13:17:49 -0600 | [diff] [blame] | 161 | dmas = <&gpi_dma0 0 4 3 64 0>, |
| 162 | <&gpi_dma0 1 4 3 64 0>; |
| 163 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 164 | pinctrl-names = "default", "sleep"; |
| 165 | pinctrl-0 = <&qupv3_se4_i2c_active>; |
| 166 | pinctrl-1 = <&qupv3_se4_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 167 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 168 | status = "disabled"; |
| 169 | }; |
| 170 | |
| 171 | qupv3_se5_i2c: i2c@894000 { |
| 172 | compatible = "qcom,i2c-geni"; |
| 173 | reg = <0x894000 0x4000>; |
| 174 | interrupts = <GIC_SPI 606 0>; |
| 175 | #address-cells = <1>; |
| 176 | #size-cells = <0>; |
| 177 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 178 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, |
| 179 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 180 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
Sagar Dharia | 82bf858 | 2017-04-15 13:17:49 -0600 | [diff] [blame] | 181 | dmas = <&gpi_dma0 0 5 3 64 0>, |
| 182 | <&gpi_dma0 1 5 3 64 0>; |
| 183 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 184 | pinctrl-names = "default", "sleep"; |
| 185 | pinctrl-0 = <&qupv3_se5_i2c_active>; |
| 186 | pinctrl-1 = <&qupv3_se5_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 187 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 188 | status = "disabled"; |
| 189 | }; |
| 190 | |
| 191 | qupv3_se6_i2c: i2c@898000 { |
| 192 | compatible = "qcom,i2c-geni"; |
| 193 | reg = <0x898000 0x4000>; |
| 194 | interrupts = <GIC_SPI 607 0>; |
| 195 | #address-cells = <1>; |
| 196 | #size-cells = <0>; |
| 197 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 198 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, |
| 199 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 200 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
Sagar Dharia | 82bf858 | 2017-04-15 13:17:49 -0600 | [diff] [blame] | 201 | dmas = <&gpi_dma0 0 6 3 64 0>, |
| 202 | <&gpi_dma0 1 6 3 64 0>; |
| 203 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 204 | pinctrl-names = "default", "sleep"; |
| 205 | pinctrl-0 = <&qupv3_se6_i2c_active>; |
| 206 | pinctrl-1 = <&qupv3_se6_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 207 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 208 | status = "disabled"; |
| 209 | }; |
| 210 | |
| 211 | qupv3_se7_i2c: i2c@89c000 { |
| 212 | compatible = "qcom,i2c-geni"; |
| 213 | reg = <0x89c000 0x4000>; |
| 214 | interrupts = <GIC_SPI 608 0>; |
| 215 | #address-cells = <1>; |
| 216 | #size-cells = <0>; |
| 217 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 218 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, |
| 219 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 220 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
Sagar Dharia | 82bf858 | 2017-04-15 13:17:49 -0600 | [diff] [blame] | 221 | dmas = <&gpi_dma0 0 7 3 64 0>, |
| 222 | <&gpi_dma0 1 7 3 64 0>; |
| 223 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 224 | pinctrl-names = "default", "sleep"; |
| 225 | pinctrl-0 = <&qupv3_se7_i2c_active>; |
| 226 | pinctrl-1 = <&qupv3_se7_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 227 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 228 | status = "disabled"; |
| 229 | }; |
| 230 | |
| 231 | /* SPI */ |
| 232 | qupv3_se0_spi: spi@880000 { |
| 233 | compatible = "qcom,spi-geni"; |
| 234 | #address-cells = <1>; |
| 235 | #size-cells = <0>; |
| 236 | reg = <0x880000 0x4000>; |
| 237 | reg-names = "se_phys"; |
| 238 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 239 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S0_CLK>, |
| 240 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 241 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 242 | pinctrl-names = "default", "sleep"; |
| 243 | pinctrl-0 = <&qupv3_se0_spi_active>; |
| 244 | pinctrl-1 = <&qupv3_se0_spi_sleep>; |
| 245 | interrupts = <GIC_SPI 601 0>; |
| 246 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 247 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 248 | dmas = <&gpi_dma0 0 0 1 64 0>, |
| 249 | <&gpi_dma0 1 0 1 64 0>; |
| 250 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 251 | status = "disabled"; |
| 252 | }; |
| 253 | |
| 254 | qupv3_se1_spi: spi@884000 { |
| 255 | compatible = "qcom,spi-geni"; |
| 256 | #address-cells = <1>; |
| 257 | #size-cells = <0>; |
| 258 | reg = <0x884000 0x4000>; |
| 259 | reg-names = "se_phys"; |
| 260 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 261 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>, |
| 262 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 263 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 264 | pinctrl-names = "default", "sleep"; |
| 265 | pinctrl-0 = <&qupv3_se1_spi_active>; |
| 266 | pinctrl-1 = <&qupv3_se1_spi_sleep>; |
| 267 | interrupts = <GIC_SPI 602 0>; |
| 268 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 269 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 270 | dmas = <&gpi_dma0 0 1 1 64 0>, |
| 271 | <&gpi_dma0 1 1 1 64 0>; |
| 272 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 273 | status = "disabled"; |
| 274 | }; |
| 275 | |
| 276 | qupv3_se2_spi: spi@888000 { |
| 277 | compatible = "qcom,spi-geni"; |
| 278 | #address-cells = <1>; |
| 279 | #size-cells = <0>; |
| 280 | reg = <0x888000 0x4000>; |
| 281 | reg-names = "se_phys"; |
| 282 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 283 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>, |
| 284 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 285 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 286 | pinctrl-names = "default", "sleep"; |
| 287 | pinctrl-0 = <&qupv3_se2_spi_active>; |
| 288 | pinctrl-1 = <&qupv3_se2_spi_sleep>; |
| 289 | interrupts = <GIC_SPI 603 0>; |
| 290 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 291 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 292 | dmas = <&gpi_dma0 0 2 1 64 0>, |
| 293 | <&gpi_dma0 1 2 1 64 0>; |
| 294 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 295 | status = "disabled"; |
| 296 | }; |
| 297 | |
| 298 | qupv3_se3_spi: spi@88c000 { |
| 299 | compatible = "qcom,spi-geni"; |
| 300 | #address-cells = <1>; |
| 301 | #size-cells = <0>; |
| 302 | reg = <0x88c000 0x4000>; |
| 303 | reg-names = "se_phys"; |
| 304 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 305 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>, |
| 306 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 307 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 308 | pinctrl-names = "default", "sleep"; |
| 309 | pinctrl-0 = <&qupv3_se3_spi_active>; |
| 310 | pinctrl-1 = <&qupv3_se3_spi_sleep>; |
| 311 | interrupts = <GIC_SPI 604 0>; |
| 312 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 313 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 314 | dmas = <&gpi_dma0 0 3 1 64 0>, |
| 315 | <&gpi_dma0 1 3 1 64 0>; |
| 316 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 317 | status = "disabled"; |
| 318 | }; |
| 319 | |
| 320 | qupv3_se4_spi: spi@890000 { |
| 321 | compatible = "qcom,spi-geni"; |
| 322 | #address-cells = <1>; |
| 323 | #size-cells = <0>; |
| 324 | reg = <0x890000 0x4000>; |
| 325 | reg-names = "se_phys"; |
| 326 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 327 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S4_CLK>, |
| 328 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 329 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 330 | pinctrl-names = "default", "sleep"; |
| 331 | pinctrl-0 = <&qupv3_se4_spi_active>; |
| 332 | pinctrl-1 = <&qupv3_se4_spi_sleep>; |
| 333 | interrupts = <GIC_SPI 605 0>; |
| 334 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 335 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 336 | dmas = <&gpi_dma0 0 4 1 64 0>, |
| 337 | <&gpi_dma0 1 4 1 64 0>; |
| 338 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 339 | status = "disabled"; |
| 340 | }; |
| 341 | |
| 342 | qupv3_se5_spi: spi@894000 { |
| 343 | compatible = "qcom,spi-geni"; |
| 344 | #address-cells = <1>; |
| 345 | #size-cells = <0>; |
| 346 | reg = <0x894000 0x4000>; |
| 347 | reg-names = "se_phys"; |
| 348 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 349 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S5_CLK>, |
| 350 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 351 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 352 | pinctrl-names = "default", "sleep"; |
| 353 | pinctrl-0 = <&qupv3_se5_spi_active>; |
| 354 | pinctrl-1 = <&qupv3_se5_spi_sleep>; |
| 355 | interrupts = <GIC_SPI 606 0>; |
| 356 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 357 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 358 | dmas = <&gpi_dma0 0 5 1 64 0>, |
| 359 | <&gpi_dma0 1 5 1 64 0>; |
| 360 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 361 | status = "disabled"; |
| 362 | }; |
| 363 | |
| 364 | qupv3_se6_spi: spi@898000 { |
| 365 | compatible = "qcom,spi-geni"; |
| 366 | #address-cells = <1>; |
| 367 | #size-cells = <0>; |
| 368 | reg = <0x898000 0x4000>; |
| 369 | reg-names = "se_phys"; |
| 370 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 371 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S6_CLK>, |
| 372 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 373 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 374 | pinctrl-names = "default", "sleep"; |
| 375 | pinctrl-0 = <&qupv3_se6_spi_active>; |
| 376 | pinctrl-1 = <&qupv3_se6_spi_sleep>; |
| 377 | interrupts = <GIC_SPI 607 0>; |
| 378 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 379 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 380 | dmas = <&gpi_dma0 0 6 1 64 0>, |
| 381 | <&gpi_dma0 1 6 1 64 0>; |
| 382 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 383 | status = "disabled"; |
| 384 | }; |
| 385 | |
| 386 | qupv3_se7_spi: spi@89c000 { |
| 387 | compatible = "qcom,spi-geni"; |
| 388 | #address-cells = <1>; |
| 389 | #size-cells = <0>; |
| 390 | reg = <0x89c000 0x4000>; |
| 391 | reg-names = "se_phys"; |
| 392 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 393 | clocks = <&clock_gcc GCC_QUPV3_WRAP0_S7_CLK>, |
| 394 | <&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, |
| 395 | <&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; |
| 396 | pinctrl-names = "default", "sleep"; |
| 397 | pinctrl-0 = <&qupv3_se7_spi_active>; |
| 398 | pinctrl-1 = <&qupv3_se7_spi_sleep>; |
| 399 | interrupts = <GIC_SPI 608 0>; |
| 400 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 401 | qcom,wrapper-core = <&qupv3_0>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 402 | dmas = <&gpi_dma0 0 7 1 64 0>, |
| 403 | <&gpi_dma0 1 7 1 64 0>; |
| 404 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 405 | status = "disabled"; |
| 406 | }; |
| 407 | |
| 408 | /* QUPv3 North Instances */ |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 409 | qupv3_1: qcom,qupv3_1_geni_se@ac0000 { |
| 410 | compatible = "qcom,qupv3-geni-se"; |
| 411 | reg = <0xac0000 0x6000>; |
| 412 | qcom,bus-mas-id = <MSM_BUS_MASTER_BLSP_2>; |
| 413 | qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>; |
| 414 | qcom,iommu-s1-bypass; |
| 415 | |
| 416 | iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb { |
| 417 | compatible = "qcom,qupv3-geni-se-cb"; |
| 418 | iommus = <&apps_smmu 0x6c3 0x0>; |
| 419 | }; |
| 420 | }; |
| 421 | |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 422 | /* 2-wire UART */ |
| 423 | |
| 424 | /* Debug UART Instance for CDP/MTP platform */ |
| 425 | qupv3_se9_2uart: qcom,qup_uart@0xa84000 { |
Mukesh Kumar Savaliya | d08d4b2 | 2018-01-08 17:13:33 +0530 | [diff] [blame] | 426 | compatible = "qcom,msm-geni-console"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 427 | reg = <0xa84000 0x4000>; |
| 428 | reg-names = "se_phys"; |
| 429 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 430 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, |
| 431 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 432 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 433 | pinctrl-names = "default", "sleep"; |
| 434 | pinctrl-0 = <&qupv3_se9_2uart_active>; |
| 435 | pinctrl-1 = <&qupv3_se9_2uart_sleep>; |
| 436 | interrupts = <GIC_SPI 354 0>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 437 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 438 | status = "disabled"; |
| 439 | }; |
| 440 | |
| 441 | /* Debug UART Instance for RUMI platform */ |
| 442 | qupv3_se10_2uart: qcom,qup_uart@0xa88000 { |
Mukesh Kumar Savaliya | d08d4b2 | 2018-01-08 17:13:33 +0530 | [diff] [blame] | 443 | compatible = "qcom,msm-geni-console"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 444 | reg = <0xa88000 0x4000>; |
| 445 | reg-names = "se_phys"; |
| 446 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 447 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, |
| 448 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 449 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 450 | pinctrl-names = "default", "sleep"; |
| 451 | pinctrl-0 = <&qupv3_se10_2uart_active>; |
| 452 | pinctrl-1 = <&qupv3_se10_2uart_sleep>; |
| 453 | interrupts = <GIC_SPI 355 0>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 454 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 455 | status = "disabled"; |
| 456 | }; |
| 457 | |
| 458 | /* I2C */ |
| 459 | qupv3_se8_i2c: i2c@a80000 { |
| 460 | compatible = "qcom,i2c-geni"; |
| 461 | reg = <0xa80000 0x4000>; |
| 462 | interrupts = <GIC_SPI 353 0>; |
| 463 | #address-cells = <1>; |
| 464 | #size-cells = <0>; |
| 465 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 466 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, |
| 467 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 468 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
Sagar Dharia | 82bf858 | 2017-04-15 13:17:49 -0600 | [diff] [blame] | 469 | dmas = <&gpi_dma1 0 0 3 64 0>, |
| 470 | <&gpi_dma1 1 0 3 64 0>; |
| 471 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 472 | pinctrl-names = "default", "sleep"; |
| 473 | pinctrl-0 = <&qupv3_se8_i2c_active>; |
| 474 | pinctrl-1 = <&qupv3_se8_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 475 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 476 | status = "disabled"; |
| 477 | }; |
| 478 | |
| 479 | qupv3_se9_i2c: i2c@a84000 { |
| 480 | compatible = "qcom,i2c-geni"; |
| 481 | reg = <0xa84000 0x4000>; |
| 482 | interrupts = <GIC_SPI 354 0>; |
| 483 | #address-cells = <1>; |
| 484 | #size-cells = <0>; |
| 485 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 486 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, |
| 487 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 488 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
Sagar Dharia | 82bf858 | 2017-04-15 13:17:49 -0600 | [diff] [blame] | 489 | dmas = <&gpi_dma1 0 1 3 64 0>, |
| 490 | <&gpi_dma1 1 1 3 64 0>; |
| 491 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 492 | pinctrl-names = "default", "sleep"; |
| 493 | pinctrl-0 = <&qupv3_se9_i2c_active>; |
| 494 | pinctrl-1 = <&qupv3_se9_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 495 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 496 | status = "disabled"; |
| 497 | }; |
| 498 | |
| 499 | qupv3_se10_i2c: i2c@a88000 { |
| 500 | compatible = "qcom,i2c-geni"; |
| 501 | reg = <0xa88000 0x4000>; |
| 502 | interrupts = <GIC_SPI 355 0>; |
| 503 | #address-cells = <1>; |
| 504 | #size-cells = <0>; |
| 505 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 506 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, |
| 507 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 508 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
Sagar Dharia | 82bf858 | 2017-04-15 13:17:49 -0600 | [diff] [blame] | 509 | dmas = <&gpi_dma1 0 2 3 64 0>, |
| 510 | <&gpi_dma1 1 2 3 64 0>; |
| 511 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 512 | pinctrl-names = "default", "sleep"; |
| 513 | pinctrl-0 = <&qupv3_se10_i2c_active>; |
| 514 | pinctrl-1 = <&qupv3_se10_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 515 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 516 | status = "disabled"; |
| 517 | }; |
| 518 | |
| 519 | qupv3_se11_i2c: i2c@a8c000 { |
| 520 | compatible = "qcom,i2c-geni"; |
| 521 | reg = <0xa8c000 0x4000>; |
| 522 | interrupts = <GIC_SPI 356 0>; |
| 523 | #address-cells = <1>; |
| 524 | #size-cells = <0>; |
| 525 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 526 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, |
| 527 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 528 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
Sagar Dharia | 82bf858 | 2017-04-15 13:17:49 -0600 | [diff] [blame] | 529 | dmas = <&gpi_dma1 0 3 3 64 0>, |
| 530 | <&gpi_dma1 1 3 3 64 0>; |
| 531 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 532 | pinctrl-names = "default", "sleep"; |
| 533 | pinctrl-0 = <&qupv3_se11_i2c_active>; |
| 534 | pinctrl-1 = <&qupv3_se11_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 535 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 536 | status = "disabled"; |
| 537 | }; |
| 538 | |
| 539 | qupv3_se12_i2c: i2c@a90000 { |
| 540 | compatible = "qcom,i2c-geni"; |
| 541 | reg = <0xa90000 0x4000>; |
| 542 | interrupts = <GIC_SPI 357 0>; |
| 543 | #address-cells = <1>; |
| 544 | #size-cells = <0>; |
| 545 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 546 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, |
| 547 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 548 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
Sagar Dharia | 82bf858 | 2017-04-15 13:17:49 -0600 | [diff] [blame] | 549 | dmas = <&gpi_dma1 0 4 3 64 0>, |
| 550 | <&gpi_dma1 1 4 3 64 0>; |
| 551 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 552 | pinctrl-names = "default", "sleep"; |
| 553 | pinctrl-0 = <&qupv3_se12_i2c_active>; |
| 554 | pinctrl-1 = <&qupv3_se12_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 555 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 556 | status = "disabled"; |
| 557 | }; |
| 558 | |
| 559 | qupv3_se13_i2c: i2c@a94000 { |
| 560 | compatible = "qcom,i2c-geni"; |
| 561 | reg = <0xa94000 0x4000>; |
| 562 | interrupts = <GIC_SPI 358 0>; |
| 563 | #address-cells = <1>; |
| 564 | #size-cells = <0>; |
| 565 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 566 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, |
| 567 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 568 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
Sagar Dharia | 82bf858 | 2017-04-15 13:17:49 -0600 | [diff] [blame] | 569 | dmas = <&gpi_dma1 0 5 3 64 0>, |
| 570 | <&gpi_dma1 1 5 3 64 0>; |
| 571 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 572 | pinctrl-names = "default", "sleep"; |
| 573 | pinctrl-0 = <&qupv3_se13_i2c_active>; |
| 574 | pinctrl-1 = <&qupv3_se13_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 575 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 576 | status = "disabled"; |
| 577 | }; |
| 578 | |
| 579 | qupv3_se14_i2c: i2c@a98000 { |
| 580 | compatible = "qcom,i2c-geni"; |
| 581 | reg = <0xa98000 0x4000>; |
| 582 | interrupts = <GIC_SPI 359 0>; |
| 583 | #address-cells = <1>; |
| 584 | #size-cells = <0>; |
| 585 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 586 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S6_CLK>, |
| 587 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 588 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
Sagar Dharia | 82bf858 | 2017-04-15 13:17:49 -0600 | [diff] [blame] | 589 | dmas = <&gpi_dma1 0 6 3 64 0>, |
| 590 | <&gpi_dma1 1 6 3 64 0>; |
| 591 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 592 | pinctrl-names = "default", "sleep"; |
| 593 | pinctrl-0 = <&qupv3_se14_i2c_active>; |
| 594 | pinctrl-1 = <&qupv3_se14_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 595 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 596 | status = "disabled"; |
| 597 | }; |
| 598 | |
| 599 | qupv3_se15_i2c: i2c@a9c000 { |
| 600 | compatible = "qcom,i2c-geni"; |
| 601 | reg = <0xa9c000 0x4000>; |
| 602 | interrupts = <GIC_SPI 360 0>; |
| 603 | #address-cells = <1>; |
| 604 | #size-cells = <0>; |
| 605 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 606 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S7_CLK>, |
| 607 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 608 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
Sagar Dharia | 82bf858 | 2017-04-15 13:17:49 -0600 | [diff] [blame] | 609 | dmas = <&gpi_dma1 0 7 3 64 0>, |
| 610 | <&gpi_dma1 1 7 3 64 0>; |
| 611 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 612 | pinctrl-names = "default", "sleep"; |
| 613 | pinctrl-0 = <&qupv3_se15_i2c_active>; |
| 614 | pinctrl-1 = <&qupv3_se15_i2c_sleep>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 615 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 616 | status = "disabled"; |
| 617 | }; |
| 618 | |
| 619 | /* SPI */ |
| 620 | qupv3_se8_spi: spi@a80000 { |
| 621 | compatible = "qcom,spi-geni"; |
| 622 | #address-cells = <1>; |
| 623 | #size-cells = <0>; |
| 624 | reg = <0xa80000 0x4000>; |
| 625 | reg-names = "se_phys"; |
| 626 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 627 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>, |
| 628 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 629 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 630 | pinctrl-names = "default", "sleep"; |
| 631 | pinctrl-0 = <&qupv3_se8_spi_active>; |
Girish Mahadevan | 7ea9df5 | 2017-09-26 13:49:12 -0600 | [diff] [blame] | 632 | pinctrl-1 = <&qupv3_se8_spi_active>; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 633 | interrupts = <GIC_SPI 353 0>; |
| 634 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 635 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 636 | dmas = <&gpi_dma1 0 0 1 64 0>, |
| 637 | <&gpi_dma1 1 0 1 64 0>; |
| 638 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 639 | status = "disabled"; |
| 640 | }; |
| 641 | |
| 642 | qupv3_se9_spi: spi@a84000 { |
| 643 | compatible = "qcom,spi-geni"; |
| 644 | #address-cells = <1>; |
| 645 | #size-cells = <0>; |
| 646 | reg = <0xa84000 0x4000>; |
| 647 | reg-names = "se_phys"; |
| 648 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 649 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>, |
| 650 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 651 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 652 | pinctrl-names = "default", "sleep"; |
| 653 | pinctrl-0 = <&qupv3_se9_spi_active>; |
| 654 | pinctrl-1 = <&qupv3_se9_spi_sleep>; |
| 655 | interrupts = <GIC_SPI 354 0>; |
| 656 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 657 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 658 | dmas = <&gpi_dma1 0 1 1 64 0>, |
| 659 | <&gpi_dma1 1 1 1 64 0>; |
| 660 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 661 | status = "disabled"; |
| 662 | }; |
| 663 | |
| 664 | qupv3_se10_spi: spi@a88000 { |
| 665 | compatible = "qcom,spi-geni"; |
| 666 | #address-cells = <1>; |
| 667 | #size-cells = <0>; |
| 668 | reg = <0xa88000 0x4000>; |
| 669 | reg-names = "se_phys"; |
| 670 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 671 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>, |
| 672 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 673 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 674 | pinctrl-names = "default", "sleep"; |
| 675 | pinctrl-0 = <&qupv3_se10_spi_active>; |
| 676 | pinctrl-1 = <&qupv3_se10_spi_sleep>; |
| 677 | interrupts = <GIC_SPI 355 0>; |
| 678 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 679 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 680 | dmas = <&gpi_dma1 0 2 1 64 0>, |
| 681 | <&gpi_dma1 1 2 1 64 0>; |
| 682 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 683 | status = "disabled"; |
| 684 | }; |
| 685 | |
| 686 | qupv3_se11_spi: spi@a8c000 { |
| 687 | compatible = "qcom,spi-geni"; |
| 688 | #address-cells = <1>; |
| 689 | #size-cells = <0>; |
| 690 | reg = <0xa8c000 0x4000>; |
| 691 | reg-names = "se_phys"; |
| 692 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 693 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>, |
| 694 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 695 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 696 | pinctrl-names = "default", "sleep"; |
| 697 | pinctrl-0 = <&qupv3_se11_spi_active>; |
| 698 | pinctrl-1 = <&qupv3_se11_spi_sleep>; |
| 699 | interrupts = <GIC_SPI 356 0>; |
| 700 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 701 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 702 | dmas = <&gpi_dma1 0 3 1 64 0>, |
| 703 | <&gpi_dma1 1 3 1 64 0>; |
| 704 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 705 | status = "disabled"; |
| 706 | }; |
| 707 | |
| 708 | qupv3_se12_spi: spi@a90000 { |
| 709 | compatible = "qcom,spi-geni"; |
| 710 | #address-cells = <1>; |
| 711 | #size-cells = <0>; |
| 712 | reg = <0xa90000 0x4000>; |
| 713 | reg-names = "se_phys"; |
| 714 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 715 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S4_CLK>, |
| 716 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 717 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 718 | pinctrl-names = "default", "sleep"; |
| 719 | pinctrl-0 = <&qupv3_se12_spi_active>; |
| 720 | pinctrl-1 = <&qupv3_se12_spi_sleep>; |
| 721 | interrupts = <GIC_SPI 357 0>; |
| 722 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 723 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 724 | dmas = <&gpi_dma1 0 4 1 64 0>, |
| 725 | <&gpi_dma1 1 4 1 64 0>; |
| 726 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 727 | status = "disabled"; |
| 728 | }; |
| 729 | |
| 730 | qupv3_se13_spi: spi@a94000 { |
| 731 | compatible = "qcom,spi-geni"; |
| 732 | #address-cells = <1>; |
| 733 | #size-cells = <0>; |
| 734 | reg = <0xa94000 0x4000>; |
| 735 | reg-names = "se_phys"; |
| 736 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 737 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S5_CLK>, |
| 738 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 739 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 740 | pinctrl-names = "default", "sleep"; |
| 741 | pinctrl-0 = <&qupv3_se13_spi_active>; |
| 742 | pinctrl-1 = <&qupv3_se13_spi_sleep>; |
| 743 | interrupts = <GIC_SPI 358 0>; |
| 744 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 745 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 746 | dmas = <&gpi_dma1 0 5 1 64 0>, |
| 747 | <&gpi_dma1 1 5 1 64 0>; |
| 748 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 749 | status = "disabled"; |
| 750 | }; |
| 751 | |
| 752 | qupv3_se14_spi: spi@a98000 { |
| 753 | compatible = "qcom,spi-geni"; |
| 754 | #address-cells = <1>; |
| 755 | #size-cells = <0>; |
| 756 | reg = <0xa98000 0x4000>; |
| 757 | reg-names = "se_phys"; |
| 758 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 759 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S6_CLK>, |
| 760 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 761 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 762 | pinctrl-names = "default", "sleep"; |
| 763 | pinctrl-0 = <&qupv3_se14_spi_active>; |
| 764 | pinctrl-1 = <&qupv3_se14_spi_sleep>; |
| 765 | interrupts = <GIC_SPI 359 0>; |
| 766 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 767 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 768 | dmas = <&gpi_dma1 0 6 1 64 0>, |
| 769 | <&gpi_dma1 1 6 1 64 0>; |
| 770 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 771 | status = "disabled"; |
| 772 | }; |
| 773 | |
| 774 | qupv3_se15_spi: spi@a9c000 { |
| 775 | compatible = "qcom,spi-geni"; |
| 776 | #address-cells = <1>; |
| 777 | #size-cells = <0>; |
| 778 | reg = <0xa9c000 0x4000>; |
| 779 | reg-names = "se_phys"; |
| 780 | clock-names = "se-clk", "m-ahb", "s-ahb"; |
| 781 | clocks = <&clock_gcc GCC_QUPV3_WRAP1_S7_CLK>, |
| 782 | <&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, |
| 783 | <&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; |
| 784 | pinctrl-names = "default", "sleep"; |
| 785 | pinctrl-0 = <&qupv3_se15_spi_active>; |
| 786 | pinctrl-1 = <&qupv3_se15_spi_sleep>; |
| 787 | interrupts = <GIC_SPI 360 0>; |
| 788 | spi-max-frequency = <50000000>; |
Karthikeyan Ramasubramanian | 0d578b7 | 2017-04-26 10:44:02 -0600 | [diff] [blame] | 789 | qcom,wrapper-core = <&qupv3_1>; |
Girish Mahadevan | 1046ae4 | 2017-06-08 10:17:14 -0600 | [diff] [blame] | 790 | dmas = <&gpi_dma1 0 7 1 64 0>, |
| 791 | <&gpi_dma1 1 7 1 64 0>; |
| 792 | dma-names = "tx", "rx"; |
Girish Mahadevan | 2e2fbe7 | 2017-03-28 13:28:18 -0600 | [diff] [blame] | 793 | status = "disabled"; |
| 794 | }; |
| 795 | }; |