Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Based on arch/arm/include/asm/uaccess.h |
| 3 | * |
| 4 | * Copyright (C) 2012 ARM Ltd. |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License version 2 as |
| 8 | * published by the Free Software Foundation. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program. If not, see <http://www.gnu.org/licenses/>. |
| 17 | */ |
| 18 | #ifndef __ASM_UACCESS_H |
| 19 | #define __ASM_UACCESS_H |
| 20 | |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 21 | #include <asm/alternative.h> |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 22 | #include <asm/kernel-pgtable.h> |
Will Deacon | 4345a53 | 2017-12-01 17:33:48 +0000 | [diff] [blame] | 23 | #include <asm/mmu.h> |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 24 | #include <asm/sysreg.h> |
| 25 | |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 26 | #ifndef __ASSEMBLY__ |
| 27 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 28 | /* |
| 29 | * User space memory access functions |
| 30 | */ |
Andre Przywara | 87261d1 | 2016-10-19 14:40:54 +0100 | [diff] [blame] | 31 | #include <linux/bitops.h> |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 32 | #include <linux/kasan-checks.h> |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 33 | #include <linux/string.h> |
| 34 | #include <linux/thread_info.h> |
| 35 | |
James Morse | 338d4f4 | 2015-07-22 19:05:54 +0100 | [diff] [blame] | 36 | #include <asm/cpufeature.h> |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 37 | #include <asm/kernel-pgtable.h> |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 38 | #include <asm/ptrace.h> |
| 39 | #include <asm/errno.h> |
| 40 | #include <asm/memory.h> |
| 41 | #include <asm/compiler.h> |
| 42 | |
| 43 | #define VERIFY_READ 0 |
| 44 | #define VERIFY_WRITE 1 |
| 45 | |
| 46 | /* |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 47 | * The exception table consists of pairs of relative offsets: the first |
| 48 | * is the relative offset to an instruction that is allowed to fault, |
| 49 | * and the second is the relative offset at which the program should |
| 50 | * continue. No registers are modified, so it is entirely up to the |
| 51 | * continuation code to figure out what to do. |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 52 | * |
| 53 | * All the routines below use bits of fixup code that are out of line |
| 54 | * with the main instruction path. This means when everything is well, |
| 55 | * we don't even have to jump over them. Further, they do not intrude |
| 56 | * on our cache or tlb entries. |
| 57 | */ |
| 58 | |
| 59 | struct exception_table_entry |
| 60 | { |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 61 | int insn, fixup; |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 62 | }; |
| 63 | |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 64 | #define ARCH_HAS_RELATIVE_EXTABLE |
| 65 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 66 | extern int fixup_exception(struct pt_regs *regs); |
| 67 | |
| 68 | #define KERNEL_DS (-1UL) |
| 69 | #define get_ds() (KERNEL_DS) |
| 70 | |
| 71 | #define USER_DS TASK_SIZE_64 |
| 72 | #define get_fs() (current_thread_info()->addr_limit) |
| 73 | |
| 74 | static inline void set_fs(mm_segment_t fs) |
| 75 | { |
| 76 | current_thread_info()->addr_limit = fs; |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 77 | |
| 78 | /* |
| 79 | * Enable/disable UAO so that copy_to_user() etc can access |
| 80 | * kernel memory with the unprivileged instructions. |
| 81 | */ |
| 82 | if (IS_ENABLED(CONFIG_ARM64_UAO) && fs == KERNEL_DS) |
| 83 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(1), ARM64_HAS_UAO)); |
| 84 | else |
| 85 | asm(ALTERNATIVE("nop", SET_PSTATE_UAO(0), ARM64_HAS_UAO, |
| 86 | CONFIG_ARM64_UAO)); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 87 | } |
| 88 | |
Michael S. Tsirkin | 967f0e5 | 2015-01-06 15:11:13 +0200 | [diff] [blame] | 89 | #define segment_eq(a, b) ((a) == (b)) |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 90 | |
| 91 | /* |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 92 | * Test whether a block of memory is a valid user space address. |
| 93 | * Returns 1 if the range is valid, 0 otherwise. |
| 94 | * |
| 95 | * This is equivalent to the following test: |
Christopher Covington | 31b1e94 | 2014-03-19 16:29:37 +0000 | [diff] [blame] | 96 | * (u65)addr + (u65)size <= current->addr_limit |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 97 | * |
| 98 | * This needs 65-bit arithmetic. |
| 99 | */ |
| 100 | #define __range_ok(addr, size) \ |
| 101 | ({ \ |
Mark Rutland | e817a7f | 2017-05-03 16:09:35 +0100 | [diff] [blame] | 102 | unsigned long __addr = (unsigned long __force)(addr); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 103 | unsigned long flag, roksum; \ |
| 104 | __chk_user_ptr(addr); \ |
Christopher Covington | 31b1e94 | 2014-03-19 16:29:37 +0000 | [diff] [blame] | 105 | asm("adds %1, %1, %3; ccmp %1, %4, #2, cc; cset %0, ls" \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 106 | : "=&r" (flag), "=&r" (roksum) \ |
Mark Rutland | e817a7f | 2017-05-03 16:09:35 +0100 | [diff] [blame] | 107 | : "1" (__addr), "Ir" (size), \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 108 | "r" (current_thread_info()->addr_limit) \ |
| 109 | : "cc"); \ |
| 110 | flag; \ |
| 111 | }) |
| 112 | |
Andre Przywara | 87261d1 | 2016-10-19 14:40:54 +0100 | [diff] [blame] | 113 | /* |
Kristina Martsenko | 1d61ccb | 2017-06-06 20:14:09 +0100 | [diff] [blame] | 114 | * When dealing with data aborts, watchpoints, or instruction traps we may end |
| 115 | * up with a tagged userland pointer. Clear the tag to get a sane pointer to |
| 116 | * pass on to access_ok(), for instance. |
Andre Przywara | 87261d1 | 2016-10-19 14:40:54 +0100 | [diff] [blame] | 117 | */ |
| 118 | #define untagged_addr(addr) sign_extend64(addr, 55) |
| 119 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 120 | #define access_ok(type, addr, size) __range_ok(addr, size) |
Will Deacon | 12a0ef7 | 2013-11-06 17:20:22 +0000 | [diff] [blame] | 121 | #define user_addr_max get_fs |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 122 | |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 123 | #define _ASM_EXTABLE(from, to) \ |
| 124 | " .pushsection __ex_table, \"a\"\n" \ |
| 125 | " .align 3\n" \ |
| 126 | " .long (" #from " - .), (" #to " - .)\n" \ |
| 127 | " .popsection\n" |
| 128 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 129 | /* |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 130 | * User access enabling/disabling. |
| 131 | */ |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 132 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 133 | static inline void __uaccess_ttbr0_disable(void) |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 134 | { |
| 135 | unsigned long ttbr; |
| 136 | |
Will Deacon | f7aa82e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 137 | ttbr = read_sysreg(ttbr1_el1); |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 138 | /* reserved_ttbr0 placed at the end of swapper_pg_dir */ |
Will Deacon | f7aa82e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 139 | write_sysreg(ttbr + SWAPPER_DIR_SIZE, ttbr0_el1); |
| 140 | isb(); |
| 141 | /* Set reserved ASID */ |
Will Deacon | 4345a53 | 2017-12-01 17:33:48 +0000 | [diff] [blame] | 142 | ttbr &= ~TTBR_ASID_MASK; |
Will Deacon | f7aa82e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 143 | write_sysreg(ttbr, ttbr1_el1); |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 144 | isb(); |
| 145 | } |
| 146 | |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 147 | static inline void __uaccess_ttbr0_enable(void) |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 148 | { |
Will Deacon | f7aa82e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 149 | unsigned long flags, ttbr0, ttbr1; |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 150 | |
| 151 | /* |
| 152 | * Disable interrupts to avoid preemption between reading the 'ttbr0' |
| 153 | * variable and the MSR. A context switch could trigger an ASID |
| 154 | * roll-over and an update of 'ttbr0'. |
| 155 | */ |
| 156 | local_irq_save(flags); |
Will Deacon | f7aa82e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 157 | ttbr0 = current_thread_info()->ttbr0; |
| 158 | |
| 159 | /* Restore active ASID */ |
| 160 | ttbr1 = read_sysreg(ttbr1_el1); |
Will Deacon | 4345a53 | 2017-12-01 17:33:48 +0000 | [diff] [blame] | 161 | ttbr1 |= ttbr0 & TTBR_ASID_MASK; |
Will Deacon | f7aa82e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 162 | write_sysreg(ttbr1, ttbr1_el1); |
| 163 | isb(); |
| 164 | |
| 165 | /* Restore user page table */ |
| 166 | write_sysreg(ttbr0, ttbr0_el1); |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 167 | isb(); |
| 168 | local_irq_restore(flags); |
| 169 | } |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 170 | |
| 171 | static inline bool uaccess_ttbr0_disable(void) |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 172 | { |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 173 | if (!system_uses_ttbr0_pan()) |
| 174 | return false; |
| 175 | __uaccess_ttbr0_disable(); |
| 176 | return true; |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 177 | } |
| 178 | |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 179 | static inline bool uaccess_ttbr0_enable(void) |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 180 | { |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 181 | if (!system_uses_ttbr0_pan()) |
| 182 | return false; |
| 183 | __uaccess_ttbr0_enable(); |
| 184 | return true; |
| 185 | } |
| 186 | #else |
| 187 | static inline bool uaccess_ttbr0_disable(void) |
| 188 | { |
| 189 | return false; |
| 190 | } |
| 191 | |
| 192 | static inline bool uaccess_ttbr0_enable(void) |
| 193 | { |
| 194 | return false; |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 195 | } |
| 196 | #endif |
| 197 | |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 198 | #define __uaccess_disable(alt) \ |
| 199 | do { \ |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 200 | if (!uaccess_ttbr0_disable()) \ |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 201 | asm(ALTERNATIVE("nop", SET_PSTATE_PAN(1), alt, \ |
| 202 | CONFIG_ARM64_PAN)); \ |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 203 | } while (0) |
| 204 | |
| 205 | #define __uaccess_enable(alt) \ |
| 206 | do { \ |
Marc Zyngier | 093284e | 2016-12-12 13:50:26 +0000 | [diff] [blame] | 207 | if (!uaccess_ttbr0_enable()) \ |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 208 | asm(ALTERNATIVE("nop", SET_PSTATE_PAN(0), alt, \ |
| 209 | CONFIG_ARM64_PAN)); \ |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 210 | } while (0) |
| 211 | |
| 212 | static inline void uaccess_disable(void) |
| 213 | { |
| 214 | __uaccess_disable(ARM64_HAS_PAN); |
| 215 | } |
| 216 | |
| 217 | static inline void uaccess_enable(void) |
| 218 | { |
| 219 | __uaccess_enable(ARM64_HAS_PAN); |
| 220 | } |
| 221 | |
| 222 | /* |
| 223 | * These functions are no-ops when UAO is present. |
| 224 | */ |
| 225 | static inline void uaccess_disable_not_uao(void) |
| 226 | { |
| 227 | __uaccess_disable(ARM64_ALT_PAN_NOT_UAO); |
| 228 | } |
| 229 | |
| 230 | static inline void uaccess_enable_not_uao(void) |
| 231 | { |
| 232 | __uaccess_enable(ARM64_ALT_PAN_NOT_UAO); |
| 233 | } |
| 234 | |
| 235 | /* |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 236 | * The "__xxx" versions of the user access functions do not verify the address |
| 237 | * space - it must have been done previously with a separate "access_ok()" |
| 238 | * call. |
| 239 | * |
| 240 | * The "__xxx_error" versions set the third argument to -EFAULT if an error |
| 241 | * occurs, and leave it unchanged on success. |
| 242 | */ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 243 | #define __get_user_asm(instr, alt_instr, reg, x, addr, err, feature) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 244 | asm volatile( \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 245 | "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \ |
| 246 | alt_instr " " reg "1, [%2]\n", feature) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 247 | "2:\n" \ |
| 248 | " .section .fixup, \"ax\"\n" \ |
| 249 | " .align 2\n" \ |
| 250 | "3: mov %w0, %3\n" \ |
| 251 | " mov %1, #0\n" \ |
| 252 | " b 2b\n" \ |
| 253 | " .previous\n" \ |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 254 | _ASM_EXTABLE(1b, 3b) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 255 | : "+r" (err), "=&r" (x) \ |
| 256 | : "r" (addr), "i" (-EFAULT)) |
| 257 | |
| 258 | #define __get_user_err(x, ptr, err) \ |
| 259 | do { \ |
| 260 | unsigned long __gu_val; \ |
| 261 | __chk_user_ptr(ptr); \ |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 262 | uaccess_enable_not_uao(); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 263 | switch (sizeof(*(ptr))) { \ |
| 264 | case 1: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 265 | __get_user_asm("ldrb", "ldtrb", "%w", __gu_val, (ptr), \ |
| 266 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 267 | break; \ |
| 268 | case 2: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 269 | __get_user_asm("ldrh", "ldtrh", "%w", __gu_val, (ptr), \ |
| 270 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 271 | break; \ |
| 272 | case 4: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 273 | __get_user_asm("ldr", "ldtr", "%w", __gu_val, (ptr), \ |
| 274 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 275 | break; \ |
| 276 | case 8: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 277 | __get_user_asm("ldr", "ldtr", "%", __gu_val, (ptr), \ |
| 278 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 279 | break; \ |
| 280 | default: \ |
| 281 | BUILD_BUG(); \ |
| 282 | } \ |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 283 | uaccess_disable_not_uao(); \ |
Michael S. Tsirkin | 58fff51 | 2014-12-12 01:56:04 +0200 | [diff] [blame] | 284 | (x) = (__force __typeof__(*(ptr)))__gu_val; \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 285 | } while (0) |
| 286 | |
| 287 | #define __get_user(x, ptr) \ |
| 288 | ({ \ |
| 289 | int __gu_err = 0; \ |
| 290 | __get_user_err((x), (ptr), __gu_err); \ |
| 291 | __gu_err; \ |
| 292 | }) |
| 293 | |
| 294 | #define __get_user_error(x, ptr, err) \ |
| 295 | ({ \ |
| 296 | __get_user_err((x), (ptr), (err)); \ |
| 297 | (void)0; \ |
| 298 | }) |
| 299 | |
| 300 | #define __get_user_unaligned __get_user |
| 301 | |
| 302 | #define get_user(x, ptr) \ |
| 303 | ({ \ |
AKASHI Takahiro | 1f65c13 | 2013-09-24 10:00:50 +0100 | [diff] [blame] | 304 | __typeof__(*(ptr)) __user *__p = (ptr); \ |
Michael S. Tsirkin | 56d2ef7 | 2013-05-26 17:30:42 +0300 | [diff] [blame] | 305 | might_fault(); \ |
AKASHI Takahiro | 1f65c13 | 2013-09-24 10:00:50 +0100 | [diff] [blame] | 306 | access_ok(VERIFY_READ, __p, sizeof(*__p)) ? \ |
| 307 | __get_user((x), __p) : \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 308 | ((x) = 0, -EFAULT); \ |
| 309 | }) |
| 310 | |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 311 | #define __put_user_asm(instr, alt_instr, reg, x, addr, err, feature) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 312 | asm volatile( \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 313 | "1:"ALTERNATIVE(instr " " reg "1, [%2]\n", \ |
| 314 | alt_instr " " reg "1, [%2]\n", feature) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 315 | "2:\n" \ |
| 316 | " .section .fixup,\"ax\"\n" \ |
| 317 | " .align 2\n" \ |
| 318 | "3: mov %w0, %3\n" \ |
| 319 | " b 2b\n" \ |
| 320 | " .previous\n" \ |
Ard Biesheuvel | 6c94f27 | 2016-01-01 15:02:12 +0100 | [diff] [blame] | 321 | _ASM_EXTABLE(1b, 3b) \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 322 | : "+r" (err) \ |
| 323 | : "r" (x), "r" (addr), "i" (-EFAULT)) |
| 324 | |
| 325 | #define __put_user_err(x, ptr, err) \ |
| 326 | do { \ |
| 327 | __typeof__(*(ptr)) __pu_val = (x); \ |
| 328 | __chk_user_ptr(ptr); \ |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 329 | uaccess_enable_not_uao(); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 330 | switch (sizeof(*(ptr))) { \ |
| 331 | case 1: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 332 | __put_user_asm("strb", "sttrb", "%w", __pu_val, (ptr), \ |
| 333 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 334 | break; \ |
| 335 | case 2: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 336 | __put_user_asm("strh", "sttrh", "%w", __pu_val, (ptr), \ |
| 337 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 338 | break; \ |
| 339 | case 4: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 340 | __put_user_asm("str", "sttr", "%w", __pu_val, (ptr), \ |
| 341 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 342 | break; \ |
| 343 | case 8: \ |
James Morse | 57f4959 | 2016-02-05 14:58:48 +0000 | [diff] [blame] | 344 | __put_user_asm("str", "sttr", "%", __pu_val, (ptr), \ |
| 345 | (err), ARM64_HAS_UAO); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 346 | break; \ |
| 347 | default: \ |
| 348 | BUILD_BUG(); \ |
| 349 | } \ |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 350 | uaccess_disable_not_uao(); \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 351 | } while (0) |
| 352 | |
| 353 | #define __put_user(x, ptr) \ |
| 354 | ({ \ |
| 355 | int __pu_err = 0; \ |
| 356 | __put_user_err((x), (ptr), __pu_err); \ |
| 357 | __pu_err; \ |
| 358 | }) |
| 359 | |
| 360 | #define __put_user_error(x, ptr, err) \ |
| 361 | ({ \ |
| 362 | __put_user_err((x), (ptr), (err)); \ |
| 363 | (void)0; \ |
| 364 | }) |
| 365 | |
| 366 | #define __put_user_unaligned __put_user |
| 367 | |
| 368 | #define put_user(x, ptr) \ |
| 369 | ({ \ |
AKASHI Takahiro | 1f65c13 | 2013-09-24 10:00:50 +0100 | [diff] [blame] | 370 | __typeof__(*(ptr)) __user *__p = (ptr); \ |
Michael S. Tsirkin | 56d2ef7 | 2013-05-26 17:30:42 +0300 | [diff] [blame] | 371 | might_fault(); \ |
AKASHI Takahiro | 1f65c13 | 2013-09-24 10:00:50 +0100 | [diff] [blame] | 372 | access_ok(VERIFY_WRITE, __p, sizeof(*__p)) ? \ |
| 373 | __put_user((x), __p) : \ |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 374 | -EFAULT; \ |
| 375 | }) |
| 376 | |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 377 | extern unsigned long __must_check __arch_copy_from_user(void *to, const void __user *from, unsigned long n); |
| 378 | extern unsigned long __must_check __arch_copy_to_user(void __user *to, const void *from, unsigned long n); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 379 | extern unsigned long __must_check __copy_in_user(void __user *to, const void __user *from, unsigned long n); |
| 380 | extern unsigned long __must_check __clear_user(void __user *addr, unsigned long n); |
| 381 | |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 382 | static inline unsigned long __must_check __copy_from_user(void *to, const void __user *from, unsigned long n) |
| 383 | { |
| 384 | kasan_check_write(to, n); |
Kees Cook | faf5b63 | 2016-06-23 15:59:42 -0700 | [diff] [blame] | 385 | check_object_size(to, n, false); |
| 386 | return __arch_copy_from_user(to, from, n); |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 387 | } |
| 388 | |
| 389 | static inline unsigned long __must_check __copy_to_user(void __user *to, const void *from, unsigned long n) |
| 390 | { |
| 391 | kasan_check_read(from, n); |
Kees Cook | faf5b63 | 2016-06-23 15:59:42 -0700 | [diff] [blame] | 392 | check_object_size(from, n, true); |
| 393 | return __arch_copy_to_user(to, from, n); |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 394 | } |
| 395 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 396 | static inline unsigned long __must_check copy_from_user(void *to, const void __user *from, unsigned long n) |
| 397 | { |
Al Viro | 4855bd2 | 2016-09-10 16:50:00 -0400 | [diff] [blame] | 398 | unsigned long res = n; |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 399 | kasan_check_write(to, n); |
Mark Rutland | d0a0057 | 2017-02-07 12:33:55 +0000 | [diff] [blame] | 400 | check_object_size(to, n, false); |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 401 | |
Kees Cook | faf5b63 | 2016-06-23 15:59:42 -0700 | [diff] [blame] | 402 | if (access_ok(VERIFY_READ, from, n)) { |
Al Viro | 4855bd2 | 2016-09-10 16:50:00 -0400 | [diff] [blame] | 403 | res = __arch_copy_from_user(to, from, n); |
| 404 | } |
| 405 | if (unlikely(res)) |
| 406 | memset(to + (n - res), 0, res); |
| 407 | return res; |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 408 | } |
| 409 | |
| 410 | static inline unsigned long __must_check copy_to_user(void __user *to, const void *from, unsigned long n) |
| 411 | { |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 412 | kasan_check_read(from, n); |
Mark Rutland | d0a0057 | 2017-02-07 12:33:55 +0000 | [diff] [blame] | 413 | check_object_size(from, n, true); |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 414 | |
Kees Cook | faf5b63 | 2016-06-23 15:59:42 -0700 | [diff] [blame] | 415 | if (access_ok(VERIFY_WRITE, to, n)) { |
Yang Shi | bffe1baff | 2016-06-08 14:40:56 -0700 | [diff] [blame] | 416 | n = __arch_copy_to_user(to, from, n); |
Kees Cook | faf5b63 | 2016-06-23 15:59:42 -0700 | [diff] [blame] | 417 | } |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 418 | return n; |
| 419 | } |
| 420 | |
| 421 | static inline unsigned long __must_check copy_in_user(void __user *to, const void __user *from, unsigned long n) |
| 422 | { |
| 423 | if (access_ok(VERIFY_READ, from, n) && access_ok(VERIFY_WRITE, to, n)) |
| 424 | n = __copy_in_user(to, from, n); |
| 425 | return n; |
| 426 | } |
| 427 | |
| 428 | #define __copy_to_user_inatomic __copy_to_user |
| 429 | #define __copy_from_user_inatomic __copy_from_user |
| 430 | |
| 431 | static inline unsigned long __must_check clear_user(void __user *to, unsigned long n) |
| 432 | { |
| 433 | if (access_ok(VERIFY_WRITE, to, n)) |
| 434 | n = __clear_user(to, n); |
| 435 | return n; |
| 436 | } |
| 437 | |
Will Deacon | 12a0ef7 | 2013-11-06 17:20:22 +0000 | [diff] [blame] | 438 | extern long strncpy_from_user(char *dest, const char __user *src, long count); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 439 | |
Will Deacon | 12a0ef7 | 2013-11-06 17:20:22 +0000 | [diff] [blame] | 440 | extern __must_check long strlen_user(const char __user *str); |
| 441 | extern __must_check long strnlen_user(const char __user *str, long n); |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 442 | |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 443 | #else /* __ASSEMBLY__ */ |
| 444 | |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 445 | #include <asm/assembler.h> |
| 446 | |
| 447 | /* |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 448 | * User access enabling/disabling macros. |
| 449 | */ |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 450 | #ifdef CONFIG_ARM64_SW_TTBR0_PAN |
| 451 | .macro __uaccess_ttbr0_disable, tmp1 |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 452 | mrs \tmp1, ttbr1_el1 // swapper_pg_dir |
| 453 | add \tmp1, \tmp1, #SWAPPER_DIR_SIZE // reserved_ttbr0 at the end of swapper_pg_dir |
| 454 | msr ttbr0_el1, \tmp1 // set reserved TTBR0_EL1 |
| 455 | isb |
Will Deacon | f7aa82e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 456 | sub \tmp1, \tmp1, #SWAPPER_DIR_SIZE |
Will Deacon | 4345a53 | 2017-12-01 17:33:48 +0000 | [diff] [blame] | 457 | bic \tmp1, \tmp1, #TTBR_ASID_MASK |
Will Deacon | f7aa82e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 458 | msr ttbr1_el1, \tmp1 // set reserved ASID |
| 459 | isb |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 460 | .endm |
| 461 | |
Will Deacon | f7aa82e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 462 | .macro __uaccess_ttbr0_enable, tmp1, tmp2 |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 463 | get_thread_info \tmp1 |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 464 | ldr \tmp1, [\tmp1, #TSK_TI_TTBR0] // load saved TTBR0_EL1 |
Will Deacon | f7aa82e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 465 | mrs \tmp2, ttbr1_el1 |
| 466 | extr \tmp2, \tmp2, \tmp1, #48 |
| 467 | ror \tmp2, \tmp2, #16 |
| 468 | msr ttbr1_el1, \tmp2 // set the active ASID |
| 469 | isb |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 470 | msr ttbr0_el1, \tmp1 // set the non-PAN TTBR0_EL1 |
| 471 | isb |
| 472 | .endm |
| 473 | |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 474 | .macro uaccess_ttbr0_disable, tmp1 |
| 475 | alternative_if_not ARM64_HAS_PAN |
| 476 | __uaccess_ttbr0_disable \tmp1 |
| 477 | alternative_else_nop_endif |
| 478 | .endm |
| 479 | |
Will Deacon | f7aa82e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 480 | .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 481 | alternative_if_not ARM64_HAS_PAN |
Will Deacon | f7aa82e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 482 | save_and_disable_irq \tmp3 // avoid preemption |
| 483 | __uaccess_ttbr0_enable \tmp1, \tmp2 |
| 484 | restore_irq \tmp3 |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 485 | alternative_else_nop_endif |
| 486 | .endm |
| 487 | #else |
| 488 | .macro uaccess_ttbr0_disable, tmp1 |
| 489 | .endm |
| 490 | |
Will Deacon | f7aa82e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 491 | .macro uaccess_ttbr0_enable, tmp1, tmp2, tmp3 |
Catalin Marinas | 005bf1a | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 492 | .endm |
| 493 | #endif |
| 494 | |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 495 | /* |
| 496 | * These macros are no-ops when UAO is present. |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 497 | */ |
| 498 | .macro uaccess_disable_not_uao, tmp1 |
Catalin Marinas | e4cbde7 | 2016-07-01 16:53:00 +0100 | [diff] [blame] | 499 | uaccess_ttbr0_disable \tmp1 |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 500 | alternative_if ARM64_ALT_PAN_NOT_UAO |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 501 | SET_PSTATE_PAN(1) |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 502 | alternative_else_nop_endif |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 503 | .endm |
| 504 | |
Will Deacon | f7aa82e | 2017-08-10 13:58:16 +0100 | [diff] [blame] | 505 | .macro uaccess_enable_not_uao, tmp1, tmp2, tmp3 |
| 506 | uaccess_ttbr0_enable \tmp1, \tmp2, \tmp3 |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 507 | alternative_if ARM64_ALT_PAN_NOT_UAO |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 508 | SET_PSTATE_PAN(0) |
Catalin Marinas | 2962f1d | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 509 | alternative_else_nop_endif |
Catalin Marinas | 7c93e72 | 2016-07-01 14:58:21 +0100 | [diff] [blame] | 510 | .endm |
| 511 | |
| 512 | #endif /* __ASSEMBLY__ */ |
| 513 | |
Catalin Marinas | 0aea86a | 2012-03-05 11:49:32 +0000 | [diff] [blame] | 514 | #endif /* __ASM_UACCESS_H */ |