Sachin Bhayare | cf8460a | 2018-01-03 18:34:30 +0530 | [diff] [blame] | 1 | /* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | |
| 14 | #define pr_fmt(fmt) "%s: " fmt, __func__ |
| 15 | |
| 16 | #include <linux/kernel.h> |
| 17 | #include <linux/err.h> |
| 18 | #include <linux/string.h> |
| 19 | #include <linux/clk/msm-clock-generic.h> |
| 20 | #include <linux/of_address.h> |
| 21 | #include <linux/dma-mapping.h> |
| 22 | #include <linux/vmalloc.h> |
| 23 | #include <linux/memblock.h> |
| 24 | |
| 25 | #include "mdss-pll.h" |
| 26 | |
| 27 | int mdss_pll_util_resource_init(struct platform_device *pdev, |
| 28 | struct mdss_pll_resources *pll_res) |
| 29 | { |
| 30 | int rc = 0; |
| 31 | struct dss_module_power *mp = &pll_res->mp; |
| 32 | |
| 33 | rc = msm_dss_config_vreg(&pdev->dev, |
| 34 | mp->vreg_config, mp->num_vreg, 1); |
| 35 | if (rc) { |
| 36 | pr_err("Vreg config failed rc=%d\n", rc); |
| 37 | goto vreg_err; |
| 38 | } |
| 39 | |
| 40 | rc = msm_dss_get_clk(&pdev->dev, mp->clk_config, mp->num_clk); |
| 41 | if (rc) { |
| 42 | pr_err("Clock get failed rc=%d\n", rc); |
| 43 | goto clk_err; |
| 44 | } |
| 45 | |
| 46 | return rc; |
| 47 | |
| 48 | clk_err: |
| 49 | msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0); |
| 50 | vreg_err: |
| 51 | return rc; |
| 52 | } |
| 53 | |
| 54 | /** |
| 55 | * mdss_pll_get_mp_by_reg_name() -- Find power module by regulator name |
| 56 | *@pll_res: Pointer to the PLL resource |
| 57 | *@name: Regulator name as specified in the pll dtsi |
| 58 | * |
| 59 | * This is a helper function to retrieve the regulator information |
| 60 | * for each pll resource. |
| 61 | */ |
| 62 | struct dss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res |
| 63 | , char *name) |
| 64 | { |
| 65 | |
| 66 | struct dss_vreg *regulator = NULL; |
| 67 | int i; |
| 68 | |
| 69 | if ((pll_res == NULL) || (pll_res->mp.vreg_config == NULL)) { |
| 70 | pr_err("%s Invalid PLL resource\n", __func__); |
| 71 | goto error; |
| 72 | } |
| 73 | |
| 74 | regulator = pll_res->mp.vreg_config; |
| 75 | |
| 76 | for (i = 0; i < pll_res->mp.num_vreg; i++) { |
| 77 | if (!strcmp(name, regulator->vreg_name)) { |
| 78 | pr_debug("Found regulator match for %s\n", name); |
| 79 | break; |
| 80 | } |
| 81 | regulator++; |
| 82 | } |
| 83 | |
| 84 | error: |
| 85 | return regulator; |
| 86 | } |
| 87 | |
| 88 | void mdss_pll_util_resource_deinit(struct platform_device *pdev, |
| 89 | struct mdss_pll_resources *pll_res) |
| 90 | { |
| 91 | struct dss_module_power *mp = &pll_res->mp; |
| 92 | |
| 93 | msm_dss_put_clk(mp->clk_config, mp->num_clk); |
| 94 | |
| 95 | msm_dss_config_vreg(&pdev->dev, mp->vreg_config, mp->num_vreg, 0); |
| 96 | } |
| 97 | |
| 98 | void mdss_pll_util_resource_release(struct platform_device *pdev, |
| 99 | struct mdss_pll_resources *pll_res) |
| 100 | { |
| 101 | struct dss_module_power *mp = &pll_res->mp; |
| 102 | |
| 103 | devm_kfree(&pdev->dev, mp->clk_config); |
| 104 | devm_kfree(&pdev->dev, mp->vreg_config); |
| 105 | mp->num_vreg = 0; |
| 106 | mp->num_clk = 0; |
| 107 | } |
| 108 | |
| 109 | int mdss_pll_util_resource_enable(struct mdss_pll_resources *pll_res, |
| 110 | bool enable) |
| 111 | { |
| 112 | int rc = 0; |
| 113 | struct dss_module_power *mp = &pll_res->mp; |
| 114 | |
| 115 | if (enable) { |
| 116 | rc = msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable); |
| 117 | if (rc) { |
| 118 | pr_err("Failed to enable vregs rc=%d\n", rc); |
| 119 | goto vreg_err; |
| 120 | } |
| 121 | |
| 122 | rc = msm_dss_clk_set_rate(mp->clk_config, mp->num_clk); |
| 123 | if (rc) { |
| 124 | pr_err("Failed to set clock rate rc=%d\n", rc); |
| 125 | goto clk_err; |
| 126 | } |
| 127 | |
| 128 | rc = msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable); |
| 129 | if (rc) { |
| 130 | pr_err("clock enable failed rc:%d\n", rc); |
| 131 | goto clk_err; |
| 132 | } |
| 133 | } else { |
| 134 | msm_dss_enable_clk(mp->clk_config, mp->num_clk, enable); |
| 135 | |
| 136 | msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, enable); |
| 137 | } |
| 138 | |
| 139 | return rc; |
| 140 | |
| 141 | clk_err: |
| 142 | msm_dss_enable_vreg(mp->vreg_config, mp->num_vreg, 0); |
| 143 | vreg_err: |
| 144 | return rc; |
| 145 | } |
| 146 | |
| 147 | static int mdss_pll_util_parse_dt_supply(struct platform_device *pdev, |
| 148 | struct mdss_pll_resources *pll_res) |
| 149 | { |
| 150 | int i = 0, rc = 0; |
| 151 | u32 tmp = 0; |
| 152 | struct device_node *of_node = NULL, *supply_root_node = NULL; |
| 153 | struct device_node *supply_node = NULL; |
| 154 | struct dss_module_power *mp = &pll_res->mp; |
| 155 | |
| 156 | of_node = pdev->dev.of_node; |
| 157 | |
| 158 | mp->num_vreg = 0; |
| 159 | supply_root_node = of_get_child_by_name(of_node, |
| 160 | "qcom,platform-supply-entries"); |
| 161 | if (!supply_root_node) { |
| 162 | pr_err("no supply entry present\n"); |
| 163 | return rc; |
| 164 | } |
| 165 | |
| 166 | for_each_child_of_node(supply_root_node, supply_node) { |
| 167 | mp->num_vreg++; |
| 168 | } |
| 169 | |
| 170 | if (mp->num_vreg == 0) { |
| 171 | pr_debug("no vreg\n"); |
| 172 | return rc; |
| 173 | } |
| 174 | pr_debug("vreg found. count=%d\n", mp->num_vreg); |
| 175 | |
| 176 | mp->vreg_config = devm_kzalloc(&pdev->dev, sizeof(struct dss_vreg) * |
| 177 | mp->num_vreg, GFP_KERNEL); |
| 178 | if (!mp->vreg_config) { |
| 179 | rc = -ENOMEM; |
| 180 | return rc; |
| 181 | } |
| 182 | |
| 183 | for_each_child_of_node(supply_root_node, supply_node) { |
| 184 | |
| 185 | const char *st = NULL; |
| 186 | |
| 187 | rc = of_property_read_string(supply_node, |
| 188 | "qcom,supply-name", &st); |
| 189 | if (rc) { |
| 190 | pr_err(":error reading name. rc=%d\n", rc); |
| 191 | goto error; |
| 192 | } |
| 193 | |
| 194 | strlcpy(mp->vreg_config[i].vreg_name, st, |
| 195 | sizeof(mp->vreg_config[i].vreg_name)); |
| 196 | |
| 197 | rc = of_property_read_u32(supply_node, |
| 198 | "qcom,supply-min-voltage", &tmp); |
| 199 | if (rc) { |
| 200 | pr_err(": error reading min volt. rc=%d\n", rc); |
| 201 | goto error; |
| 202 | } |
| 203 | mp->vreg_config[i].min_voltage = tmp; |
| 204 | |
| 205 | rc = of_property_read_u32(supply_node, |
| 206 | "qcom,supply-max-voltage", &tmp); |
| 207 | if (rc) { |
| 208 | pr_err(": error reading max volt. rc=%d\n", rc); |
| 209 | goto error; |
| 210 | } |
| 211 | mp->vreg_config[i].max_voltage = tmp; |
| 212 | |
| 213 | rc = of_property_read_u32(supply_node, |
| 214 | "qcom,supply-enable-load", &tmp); |
| 215 | if (rc) { |
| 216 | pr_err(": error reading enable load. rc=%d\n", rc); |
| 217 | goto error; |
| 218 | } |
| 219 | mp->vreg_config[i].load[DSS_REG_MODE_ENABLE] = tmp; |
| 220 | |
| 221 | rc = of_property_read_u32(supply_node, |
| 222 | "qcom,supply-disable-load", &tmp); |
| 223 | if (rc) { |
| 224 | pr_err(": error reading disable load. rc=%d\n", rc); |
| 225 | goto error; |
| 226 | } |
| 227 | mp->vreg_config[i].load[DSS_REG_MODE_DISABLE] = tmp; |
| 228 | |
| 229 | rc = of_property_read_u32(supply_node, |
| 230 | "qcom,supply-ulp-load", &tmp); |
| 231 | if (rc) |
| 232 | pr_warn(": error reading ulp load. rc=%d\n", rc); |
| 233 | |
| 234 | mp->vreg_config[i].load[DSS_REG_MODE_ULP] = (!rc ? tmp : |
| 235 | mp->vreg_config[i].load[DSS_REG_MODE_ENABLE]); |
| 236 | |
| 237 | rc = of_property_read_u32(supply_node, |
| 238 | "qcom,supply-pre-on-sleep", &tmp); |
| 239 | if (rc) |
| 240 | pr_debug("error reading supply pre sleep value. rc=%d\n", |
| 241 | rc); |
| 242 | |
| 243 | mp->vreg_config[i].pre_on_sleep = (!rc ? tmp : 0); |
| 244 | |
| 245 | rc = of_property_read_u32(supply_node, |
| 246 | "qcom,supply-pre-off-sleep", &tmp); |
| 247 | if (rc) |
| 248 | pr_debug("error reading supply pre sleep value. rc=%d\n", |
| 249 | rc); |
| 250 | |
| 251 | mp->vreg_config[i].pre_off_sleep = (!rc ? tmp : 0); |
| 252 | |
| 253 | rc = of_property_read_u32(supply_node, |
| 254 | "qcom,supply-post-on-sleep", &tmp); |
| 255 | if (rc) |
| 256 | pr_debug("error reading supply post sleep value. rc=%d\n", |
| 257 | rc); |
| 258 | |
| 259 | mp->vreg_config[i].post_on_sleep = (!rc ? tmp : 0); |
| 260 | |
| 261 | rc = of_property_read_u32(supply_node, |
| 262 | "qcom,supply-post-off-sleep", &tmp); |
| 263 | if (rc) |
| 264 | pr_debug("error reading supply post sleep value. rc=%d\n", |
| 265 | rc); |
| 266 | |
| 267 | mp->vreg_config[i].post_off_sleep = (!rc ? tmp : 0); |
| 268 | |
| 269 | pr_debug("%s min=%d, max=%d, enable=%d, disable=%d, ulp=%d, preonsleep=%d, postonsleep=%d, preoffsleep=%d, postoffsleep=%d\n", |
| 270 | mp->vreg_config[i].vreg_name, |
| 271 | mp->vreg_config[i].min_voltage, |
| 272 | mp->vreg_config[i].max_voltage, |
| 273 | mp->vreg_config[i].load[DSS_REG_MODE_ENABLE], |
| 274 | mp->vreg_config[i].load[DSS_REG_MODE_DISABLE], |
| 275 | mp->vreg_config[i].load[DSS_REG_MODE_ULP], |
| 276 | mp->vreg_config[i].pre_on_sleep, |
| 277 | mp->vreg_config[i].post_on_sleep, |
| 278 | mp->vreg_config[i].pre_off_sleep, |
| 279 | mp->vreg_config[i].post_off_sleep); |
| 280 | ++i; |
| 281 | |
| 282 | rc = 0; |
| 283 | } |
| 284 | |
| 285 | return rc; |
| 286 | |
| 287 | error: |
| 288 | if (mp->vreg_config) { |
| 289 | devm_kfree(&pdev->dev, mp->vreg_config); |
| 290 | mp->vreg_config = NULL; |
| 291 | mp->num_vreg = 0; |
| 292 | } |
| 293 | |
| 294 | return rc; |
| 295 | } |
| 296 | |
| 297 | static int mdss_pll_util_parse_dt_clock(struct platform_device *pdev, |
| 298 | struct mdss_pll_resources *pll_res) |
| 299 | { |
| 300 | u32 i = 0, rc = 0; |
| 301 | struct dss_module_power *mp = &pll_res->mp; |
| 302 | const char *clock_name; |
| 303 | u32 clock_rate; |
| 304 | |
| 305 | mp->num_clk = of_property_count_strings(pdev->dev.of_node, |
| 306 | "clock-names"); |
| 307 | if (mp->num_clk <= 0) { |
| 308 | pr_err("clocks are not defined\n"); |
| 309 | goto clk_err; |
| 310 | } |
| 311 | |
| 312 | mp->clk_config = devm_kzalloc(&pdev->dev, |
| 313 | sizeof(struct dss_clk) * mp->num_clk, GFP_KERNEL); |
| 314 | if (!mp->clk_config) { |
| 315 | rc = -ENOMEM; |
| 316 | mp->num_clk = 0; |
| 317 | goto clk_err; |
| 318 | } |
| 319 | |
| 320 | for (i = 0; i < mp->num_clk; i++) { |
| 321 | of_property_read_string_index(pdev->dev.of_node, "clock-names", |
| 322 | i, &clock_name); |
| 323 | strlcpy(mp->clk_config[i].clk_name, clock_name, |
| 324 | sizeof(mp->clk_config[i].clk_name)); |
| 325 | |
| 326 | of_property_read_u32_index(pdev->dev.of_node, "clock-rate", |
| 327 | i, &clock_rate); |
| 328 | mp->clk_config[i].rate = clock_rate; |
| 329 | |
| 330 | if (!clock_rate) |
| 331 | mp->clk_config[i].type = DSS_CLK_AHB; |
| 332 | else |
| 333 | mp->clk_config[i].type = DSS_CLK_PCLK; |
| 334 | } |
| 335 | |
| 336 | clk_err: |
| 337 | return rc; |
| 338 | } |
| 339 | |
| 340 | static void mdss_pll_free_bootmem(u32 mem_addr, u32 size) |
| 341 | { |
| 342 | unsigned long pfn_start, pfn_end, pfn_idx; |
| 343 | |
| 344 | pfn_start = mem_addr >> PAGE_SHIFT; |
| 345 | pfn_end = (mem_addr + size) >> PAGE_SHIFT; |
| 346 | for (pfn_idx = pfn_start; pfn_idx < pfn_end; pfn_idx++) |
| 347 | free_reserved_page(pfn_to_page(pfn_idx)); |
| 348 | } |
| 349 | |
| 350 | static int mdss_pll_util_parse_dt_dfps(struct platform_device *pdev, |
| 351 | struct mdss_pll_resources *pll_res) |
| 352 | { |
| 353 | int rc = 0; |
| 354 | struct device_node *pnode; |
| 355 | const u32 *addr; |
| 356 | struct vm_struct *area; |
| 357 | u64 size; |
| 358 | u32 offsets[2]; |
| 359 | unsigned long virt_add; |
| 360 | |
| 361 | pnode = of_parse_phandle(pdev->dev.of_node, "memory-region", 0); |
| 362 | if (IS_ERR_OR_NULL(pnode)) { |
| 363 | rc = PTR_ERR(pnode); |
| 364 | goto pnode_err; |
| 365 | } |
| 366 | |
| 367 | addr = of_get_address(pnode, 0, &size, NULL); |
| 368 | if (!addr) { |
| 369 | pr_err("failed to parse the dfps memory address\n"); |
| 370 | rc = -EINVAL; |
| 371 | goto pnode_err; |
| 372 | } |
| 373 | /* maintain compatibility for 32/64 bit */ |
| 374 | offsets[0] = (u32) of_read_ulong(addr, 2); |
| 375 | offsets[1] = (u32) size; |
| 376 | |
| 377 | area = get_vm_area(offsets[1], VM_IOREMAP); |
| 378 | if (!area) { |
| 379 | rc = -ENOMEM; |
| 380 | goto dfps_mem_err; |
| 381 | } |
| 382 | |
| 383 | virt_add = (unsigned long)area->addr; |
| 384 | rc = ioremap_page_range(virt_add, (virt_add + offsets[1]), |
| 385 | offsets[0], PAGE_KERNEL); |
| 386 | if (rc) { |
| 387 | rc = -ENOMEM; |
| 388 | goto ioremap_err; |
| 389 | } |
| 390 | |
| 391 | pll_res->dfps = kzalloc(sizeof(struct dfps_info), GFP_KERNEL); |
| 392 | if (IS_ERR_OR_NULL(pll_res->dfps)) { |
| 393 | rc = PTR_ERR(pll_res->dfps); |
| 394 | pr_err("couldn't allocate dfps kernel memory\n"); |
| 395 | goto addr_err; |
| 396 | } |
| 397 | |
| 398 | /* memcopy complete dfps structure from kernel virtual memory */ |
| 399 | memcpy_fromio(pll_res->dfps, area->addr, sizeof(struct dfps_info)); |
| 400 | |
| 401 | addr_err: |
| 402 | if (virt_add) |
| 403 | unmap_kernel_range(virt_add, (unsigned long) size); |
| 404 | ioremap_err: |
| 405 | if (area) |
| 406 | vfree(area->addr); |
| 407 | dfps_mem_err: |
| 408 | /* free the dfps memory here */ |
| 409 | memblock_free(offsets[0], offsets[1]); |
| 410 | mdss_pll_free_bootmem(offsets[0], offsets[1]); |
| 411 | pnode_err: |
| 412 | if (pnode) |
| 413 | of_node_put(pnode); |
| 414 | |
| 415 | dma_release_declared_memory(&pdev->dev); |
| 416 | return rc; |
| 417 | } |
| 418 | |
| 419 | int mdss_pll_util_resource_parse(struct platform_device *pdev, |
| 420 | struct mdss_pll_resources *pll_res) |
| 421 | { |
| 422 | int rc = 0; |
| 423 | struct dss_module_power *mp = &pll_res->mp; |
| 424 | |
| 425 | rc = mdss_pll_util_parse_dt_supply(pdev, pll_res); |
| 426 | if (rc) { |
| 427 | pr_err("vreg parsing failed rc=%d\n", rc); |
| 428 | goto end; |
| 429 | } |
| 430 | |
| 431 | rc = mdss_pll_util_parse_dt_clock(pdev, pll_res); |
| 432 | if (rc) { |
| 433 | pr_err("clock name parsing failed rc=%d", rc); |
| 434 | goto clk_err; |
| 435 | } |
| 436 | |
| 437 | if (mdss_pll_util_parse_dt_dfps(pdev, pll_res)) |
| 438 | pr_err("dfps not enabled!\n"); |
| 439 | |
| 440 | return rc; |
| 441 | |
| 442 | clk_err: |
| 443 | devm_kfree(&pdev->dev, mp->vreg_config); |
| 444 | mp->num_vreg = 0; |
| 445 | end: |
| 446 | return rc; |
| 447 | } |