Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 1 | /* Copyright (c) 2012-2017, The Linux Foundation. All rights reserved. |
| 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | #ifndef __KGSL_IOMMU_H |
| 14 | #define __KGSL_IOMMU_H |
| 15 | |
| 16 | #ifdef CONFIG_QCOM_IOMMU |
| 17 | #include <linux/qcom_iommu.h> |
| 18 | #endif |
| 19 | #include <linux/of.h> |
| 20 | #include "kgsl.h" |
| 21 | |
| 22 | /* |
| 23 | * These defines control the address range for allocations that |
| 24 | * are mapped into all pagetables. |
| 25 | */ |
Harshdeep Dhatt | 2a3e7f5 | 2017-06-01 13:02:06 -0600 | [diff] [blame] | 26 | #define KGSL_IOMMU_GLOBAL_MEM_SIZE (20 * SZ_1M) |
Deepak Kumar | 756d6a9 | 2017-11-28 16:58:29 +0530 | [diff] [blame] | 27 | #define KGSL_IOMMU_GLOBAL_MEM_BASE32 0xf8000000 |
| 28 | #define KGSL_IOMMU_GLOBAL_MEM_BASE64 TASK_SIZE_32 |
| 29 | |
| 30 | #define KGSL_IOMMU_GLOBAL_MEM_BASE(__mmu) \ |
| 31 | (MMU_FEATURE(__mmu, KGSL_MMU_64BIT) ? \ |
| 32 | KGSL_IOMMU_GLOBAL_MEM_BASE64 : KGSL_IOMMU_GLOBAL_MEM_BASE32) |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 33 | |
| 34 | #define KGSL_IOMMU_SECURE_SIZE SZ_256M |
Deepak Kumar | 756d6a9 | 2017-11-28 16:58:29 +0530 | [diff] [blame] | 35 | #define KGSL_IOMMU_SECURE_END(_mmu) KGSL_IOMMU_GLOBAL_MEM_BASE(_mmu) |
| 36 | #define KGSL_IOMMU_SECURE_BASE(_mmu) \ |
| 37 | (KGSL_IOMMU_GLOBAL_MEM_BASE(_mmu) - KGSL_IOMMU_SECURE_SIZE) |
Shrenuj Bansal | a419c79 | 2016-10-20 14:05:11 -0700 | [diff] [blame] | 38 | |
| 39 | #define KGSL_IOMMU_SVM_BASE32 0x300000 |
| 40 | #define KGSL_IOMMU_SVM_END32 (0xC0000000 - SZ_16M) |
| 41 | |
| 42 | #define KGSL_IOMMU_VA_BASE64 0x500000000ULL |
| 43 | #define KGSL_IOMMU_VA_END64 0x600000000ULL |
| 44 | /* |
| 45 | * Note: currently we only support 36 bit addresses, |
| 46 | * but the CPU supports 39. Eventually this range |
| 47 | * should change to high part of the 39 bit address |
| 48 | * space just like the CPU. |
| 49 | */ |
| 50 | #define KGSL_IOMMU_SVM_BASE64 0x700000000ULL |
| 51 | #define KGSL_IOMMU_SVM_END64 0x800000000ULL |
| 52 | |
| 53 | /* TLBSTATUS register fields */ |
| 54 | #define KGSL_IOMMU_CTX_TLBSTATUS_SACTIVE BIT(0) |
| 55 | |
| 56 | /* IMPLDEF_MICRO_MMU_CTRL register fields */ |
| 57 | #define KGSL_IOMMU_IMPLDEF_MICRO_MMU_CTRL_HALT 0x00000004 |
| 58 | #define KGSL_IOMMU_IMPLDEF_MICRO_MMU_CTRL_IDLE 0x00000008 |
| 59 | |
| 60 | /* SCTLR fields */ |
| 61 | #define KGSL_IOMMU_SCTLR_HUPCF_SHIFT 8 |
| 62 | #define KGSL_IOMMU_SCTLR_CFCFG_SHIFT 7 |
| 63 | #define KGSL_IOMMU_SCTLR_CFIE_SHIFT 6 |
| 64 | |
| 65 | enum kgsl_iommu_reg_map { |
| 66 | KGSL_IOMMU_CTX_SCTLR = 0, |
| 67 | KGSL_IOMMU_CTX_TTBR0, |
| 68 | KGSL_IOMMU_CTX_CONTEXTIDR, |
| 69 | KGSL_IOMMU_CTX_FSR, |
| 70 | KGSL_IOMMU_CTX_FAR, |
| 71 | KGSL_IOMMU_CTX_TLBIALL, |
| 72 | KGSL_IOMMU_CTX_RESUME, |
| 73 | KGSL_IOMMU_CTX_FSYNR0, |
| 74 | KGSL_IOMMU_CTX_FSYNR1, |
| 75 | KGSL_IOMMU_CTX_TLBSYNC, |
| 76 | KGSL_IOMMU_CTX_TLBSTATUS, |
| 77 | KGSL_IOMMU_REG_MAX |
| 78 | }; |
| 79 | |
| 80 | /* Max number of iommu clks per IOMMU unit */ |
| 81 | #define KGSL_IOMMU_MAX_CLKS 5 |
| 82 | |
| 83 | enum kgsl_iommu_context_id { |
| 84 | KGSL_IOMMU_CONTEXT_USER = 0, |
| 85 | KGSL_IOMMU_CONTEXT_SECURE = 1, |
| 86 | KGSL_IOMMU_CONTEXT_MAX, |
| 87 | }; |
| 88 | |
| 89 | /* offset at which a nop command is placed in setstate */ |
| 90 | #define KGSL_IOMMU_SETSTATE_NOP_OFFSET 1024 |
| 91 | |
| 92 | /* |
| 93 | * struct kgsl_iommu_context - Structure holding data about an iommu context |
| 94 | * bank |
| 95 | * @dev: pointer to the iommu context's device |
| 96 | * @name: context name |
| 97 | * @id: The id of the context, used for deciding how it is used. |
| 98 | * @cb_num: The hardware context bank number, used for calculating register |
| 99 | * offsets. |
| 100 | * @kgsldev: The kgsl device that uses this context. |
| 101 | * @fault: Flag when set indicates that this iommu device has caused a page |
| 102 | * fault |
| 103 | * @gpu_offset: Offset of this context bank in the GPU register space |
| 104 | * @default_pt: The default pagetable for this context, |
| 105 | * it may be changed by self programming. |
| 106 | */ |
| 107 | struct kgsl_iommu_context { |
| 108 | struct device *dev; |
| 109 | const char *name; |
| 110 | enum kgsl_iommu_context_id id; |
| 111 | unsigned int cb_num; |
| 112 | struct kgsl_device *kgsldev; |
| 113 | int fault; |
| 114 | void __iomem *regbase; |
| 115 | unsigned int gpu_offset; |
| 116 | struct kgsl_pagetable *default_pt; |
| 117 | }; |
| 118 | |
| 119 | /* |
| 120 | * struct kgsl_iommu - Structure holding iommu data for kgsl driver |
| 121 | * @ctx: Array of kgsl_iommu_context structs |
| 122 | * @regbase: Virtual address of the IOMMU register base |
| 123 | * @regstart: Physical address of the iommu registers |
| 124 | * @regsize: Length of the iommu register region. |
| 125 | * @setstate: Scratch GPU memory for IOMMU operations |
| 126 | * @clk_enable_count: The ref count of clock enable calls |
| 127 | * @clks: Array of pointers to IOMMU clocks |
| 128 | * @micro_mmu_ctrl: GPU register offset of this glob al register |
| 129 | * @smmu_info: smmu info used in a5xx preemption |
| 130 | * @protect: register protection settings for the iommu. |
| 131 | * @pagefault_suppression_count: Total number of pagefaults |
| 132 | * suppressed since boot. |
| 133 | */ |
| 134 | struct kgsl_iommu { |
| 135 | struct kgsl_iommu_context ctx[KGSL_IOMMU_CONTEXT_MAX]; |
| 136 | void __iomem *regbase; |
| 137 | unsigned long regstart; |
| 138 | unsigned int regsize; |
| 139 | struct kgsl_memdesc setstate; |
| 140 | atomic_t clk_enable_count; |
| 141 | struct clk *clks[KGSL_IOMMU_MAX_CLKS]; |
| 142 | unsigned int micro_mmu_ctrl; |
| 143 | struct kgsl_memdesc smmu_info; |
| 144 | unsigned int version; |
| 145 | struct kgsl_protected_registers protect; |
| 146 | u32 pagefault_suppression_count; |
| 147 | }; |
| 148 | |
| 149 | /* |
| 150 | * struct kgsl_iommu_pt - Iommu pagetable structure private to kgsl driver |
| 151 | * @domain: Pointer to the iommu domain that contains the iommu pagetable |
| 152 | * @ttbr0: register value to set when using this pagetable |
| 153 | * @contextidr: register value to set when using this pagetable |
| 154 | * @attached: is the pagetable attached? |
| 155 | * @rbtree: all buffers mapped into the pagetable, indexed by gpuaddr |
| 156 | * @va_start: Start of virtual range used in this pagetable. |
| 157 | * @va_end: End of virtual range. |
| 158 | * @svm_start: Start of shared virtual memory range. Addresses in this |
| 159 | * range are also valid in the process's CPU address space. |
| 160 | * @svm_end: End of the shared virtual memory range. |
| 161 | * @svm_start: 32 bit compatible range, for old clients who lack bits |
| 162 | * @svm_end: end of 32 bit compatible range |
| 163 | */ |
| 164 | struct kgsl_iommu_pt { |
| 165 | struct iommu_domain *domain; |
| 166 | u64 ttbr0; |
| 167 | u32 contextidr; |
| 168 | bool attached; |
| 169 | |
| 170 | struct rb_root rbtree; |
| 171 | |
| 172 | uint64_t va_start; |
| 173 | uint64_t va_end; |
| 174 | uint64_t svm_start; |
| 175 | uint64_t svm_end; |
| 176 | uint64_t compat_va_start; |
| 177 | uint64_t compat_va_end; |
| 178 | }; |
| 179 | |
| 180 | /* |
| 181 | * offset of context bank 0 from the start of the SMMU register space. |
| 182 | */ |
| 183 | #define KGSL_IOMMU_CB0_OFFSET 0x8000 |
| 184 | /* size of each context bank's register space */ |
| 185 | #define KGSL_IOMMU_CB_SHIFT 12 |
| 186 | |
| 187 | /* Macros to read/write IOMMU registers */ |
| 188 | extern const unsigned int kgsl_iommu_reg_list[KGSL_IOMMU_REG_MAX]; |
| 189 | |
| 190 | /* |
| 191 | * Don't use this function directly. Use the macros below to read/write |
| 192 | * IOMMU registers. |
| 193 | */ |
| 194 | static inline void __iomem * |
| 195 | kgsl_iommu_reg(struct kgsl_iommu_context *ctx, enum kgsl_iommu_reg_map reg) |
| 196 | { |
| 197 | return ctx->regbase + kgsl_iommu_reg_list[reg]; |
| 198 | } |
| 199 | |
| 200 | #define KGSL_IOMMU_SET_CTX_REG_Q(_ctx, REG, val) \ |
| 201 | writeq_relaxed((val), \ |
| 202 | kgsl_iommu_reg((_ctx), KGSL_IOMMU_CTX_##REG)) |
| 203 | |
| 204 | #define KGSL_IOMMU_GET_CTX_REG_Q(_ctx, REG) \ |
| 205 | readq_relaxed(kgsl_iommu_reg((_ctx), KGSL_IOMMU_CTX_##REG)) |
| 206 | |
| 207 | #define KGSL_IOMMU_SET_CTX_REG(_ctx, REG, val) \ |
| 208 | writel_relaxed((val), \ |
| 209 | kgsl_iommu_reg((_ctx), KGSL_IOMMU_CTX_##REG)) |
| 210 | |
| 211 | #define KGSL_IOMMU_GET_CTX_REG(_ctx, REG) \ |
| 212 | readl_relaxed(kgsl_iommu_reg((_ctx), KGSL_IOMMU_CTX_##REG)) |
| 213 | |
| 214 | |
| 215 | #endif |