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gerrit-public.fairphone.software / kernel / msm-4.9 / 070ea8e1f5c7003aa463fdc511b9f898544a2a39 / . / drivers / platform / msm / ep_pcie / ep_pcie_com.h
blob: c02aabf07105e8b4a4fb21c8bb3ac900dec1fa56 [file] [log] [blame]
Yan He50222ad2017-11-17 18:22:17 -0800[diff] [blame]1/* Copyright (c) 2015-2017, The Linux Foundation. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#ifndef __EP_PCIE_COM_H
14#define __EP_PCIE_COM_H
15
16#include <linux/io.h>
17#include <linux/clk.h>
18#include <linux/compiler.h>
19#include <linux/ipc_logging.h>
20#include <linux/platform_device.h>
21#include <linux/regulator/consumer.h>
22#include <linux/types.h>
23#include <linux/uaccess.h>
24#include <linux/delay.h>
25#include <linux/msm_ep_pcie.h>
26
27#define PCIE20_PARF_SYS_CTRL 0x00
28#define PCIE20_PARF_DB_CTRL 0x10
29#define PCIE20_PARF_PM_CTRL 0x20
30#define PCIE20_PARF_PM_STTS 0x24
31#define PCIE20_PARF_PHY_CTRL 0x40
32#define PCIE20_PARF_PHY_REFCLK 0x4C
33#define PCIE20_PARF_CONFIG_BITS 0x50
34#define PCIE20_PARF_TEST_BUS 0xE4
35#define PCIE20_PARF_MHI_BASE_ADDR_LOWER 0x178
36#define PCIE20_PARF_MHI_BASE_ADDR_UPPER 0x17c
37#define PCIE20_PARF_MSI_GEN 0x188
38#define PCIE20_PARF_DEBUG_INT_EN 0x190
39#define PCIE20_PARF_MHI_IPA_DBS 0x198
40#define PCIE20_PARF_MHI_IPA_CDB_TARGET_LOWER 0x19C
41#define PCIE20_PARF_MHI_IPA_EDB_TARGET_LOWER 0x1A0
42#define PCIE20_PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1A4
43#define PCIE20_PARF_AXI_MSTR_WR_ADDR_HALT 0x1A8
44#define PCIE20_PARF_Q2A_FLUSH 0x1AC
45#define PCIE20_PARF_LTSSM 0x1B0
46#define PCIE20_PARF_CFG_BITS 0x210
47#define PCIE20_PARF_LTR_MSI_EXIT_L1SS 0x214
48#define PCIE20_PARF_INT_ALL_STATUS 0x224
49#define PCIE20_PARF_INT_ALL_CLEAR 0x228
50#define PCIE20_PARF_INT_ALL_MASK 0x22C
51#define PCIE20_PARF_SLV_ADDR_MSB_CTRL 0x2C0
52#define PCIE20_PARF_DBI_BASE_ADDR 0x350
53#define PCIE20_PARF_DBI_BASE_ADDR_HI 0x354
54#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE 0x358
55#define PCIE20_PARF_SLV_ADDR_SPACE_SIZE_HI 0x35C
56#define PCIE20_PARF_DEVICE_TYPE 0x1000
57
58#define PCIE20_ELBI_VERSION 0x00
59#define PCIE20_ELBI_SYS_CTRL 0x04
60#define PCIE20_ELBI_SYS_STTS 0x08
61#define PCIE20_ELBI_CS2_ENABLE 0xA4
62
63#define PCIE20_DEVICE_ID_VENDOR_ID 0x00
64#define PCIE20_COMMAND_STATUS 0x04
65#define PCIE20_CLASS_CODE_REVISION_ID 0x08
66#define PCIE20_BIST_HDR_TYPE 0x0C
67#define PCIE20_BAR0 0x10
68#define PCIE20_SUBSYSTEM 0x2c
69#define PCIE20_CAP_ID_NXT_PTR 0x40
70#define PCIE20_CON_STATUS 0x44
71#define PCIE20_MSI_CAP_ID_NEXT_CTRL 0x50
72#define PCIE20_MSI_LOWER 0x54
73#define PCIE20_MSI_UPPER 0x58
74#define PCIE20_MSI_DATA 0x5C
75#define PCIE20_MSI_MASK 0x60
76#define PCIE20_DEVICE_CAPABILITIES 0x74
77#define PCIE20_MASK_EP_L1_ACCPT_LATENCY 0xE00
78#define PCIE20_MASK_EP_L0S_ACCPT_LATENCY 0x1C0
79#define PCIE20_LINK_CAPABILITIES 0x7C
80#define PCIE20_MASK_CLOCK_POWER_MAN 0x40000
81#define PCIE20_MASK_L1_EXIT_LATENCY 0x38000
82#define PCIE20_MASK_L0S_EXIT_LATENCY 0x7000
83#define PCIE20_CAP_LINKCTRLSTATUS 0x80
84#define PCIE20_DEVICE_CONTROL2_STATUS2 0x98
85#define PCIE20_LINK_CONTROL2_LINK_STATUS2 0xA0
86#define PCIE20_L1SUB_CAPABILITY 0x154
87#define PCIE20_L1SUB_CONTROL1 0x158
88#define PCIE20_ACK_F_ASPM_CTRL_REG 0x70C
89#define PCIE20_MASK_ACK_N_FTS 0xff00
90#define PCIE20_MISC_CONTROL_1 0x8BC
91
92#define PCIE20_PLR_IATU_VIEWPORT 0x900
93#define PCIE20_PLR_IATU_CTRL1 0x904
94#define PCIE20_PLR_IATU_CTRL2 0x908
95#define PCIE20_PLR_IATU_LBAR 0x90C
96#define PCIE20_PLR_IATU_UBAR 0x910
97#define PCIE20_PLR_IATU_LAR 0x914
98#define PCIE20_PLR_IATU_LTAR 0x918
99#define PCIE20_PLR_IATU_UTAR 0x91c
100
101#define PCIE20_MHICFG 0x110
102#define PCIE20_BHI_EXECENV 0x228
103
104#define PCIE20_AUX_CLK_FREQ_REG 0xB40
105
106#define PERST_TIMEOUT_US_MIN 1000
107#define PERST_TIMEOUT_US_MAX 1000
108#define PERST_CHECK_MAX_COUNT 30000
109#define LINK_UP_TIMEOUT_US_MIN 1000
110#define LINK_UP_TIMEOUT_US_MAX 1000
111#define LINK_UP_CHECK_MAX_COUNT 30000
112#define BME_TIMEOUT_US_MIN 1000
113#define BME_TIMEOUT_US_MAX 1000
114#define BME_CHECK_MAX_COUNT 30000
115#define PHY_STABILIZATION_DELAY_US_MIN 1000
116#define PHY_STABILIZATION_DELAY_US_MAX 1000
117#define REFCLK_STABILIZATION_DELAY_US_MIN 1000
118#define REFCLK_STABILIZATION_DELAY_US_MAX 1000
119#define PHY_READY_TIMEOUT_COUNT 30000
120#define MSI_EXIT_L1SS_WAIT 10
121#define MSI_EXIT_L1SS_WAIT_MAX_COUNT 100
122#define XMLH_LINK_UP 0x400
123#define PARF_XMLH_LINK_UP 0x40000000
124
125#define MAX_PROP_SIZE 32
126#define MAX_MSG_LEN 80
127#define MAX_NAME_LEN 80
128#define MAX_IATU_ENTRY_NUM 2
129
130#define EP_PCIE_LOG_PAGES 50
131#define EP_PCIE_MAX_VREG 2
132#define EP_PCIE_MAX_CLK 5
133#define EP_PCIE_MAX_PIPE_CLK 1
134#define EP_PCIE_MAX_RESET 2
135
136#define EP_PCIE_ERROR -30655
137#define EP_PCIE_LINK_DOWN 0xFFFFFFFF
138
139#define EP_PCIE_OATU_INDEX_MSI 1
140#define EP_PCIE_OATU_INDEX_CTRL 2
141#define EP_PCIE_OATU_INDEX_DATA 3
142
143#define EP_PCIE_OATU_UPPER 0x100
144
145#define EP_PCIE_GEN_DBG(x...) do { \
146 if (ep_pcie_get_debug_mask()) \
147 pr_alert(x); \
148 else \
149 pr_debug(x); \
150 } while (0)
151
152#define EP_PCIE_DBG(dev, fmt, arg...) do { \
153 if ((dev)->ipc_log_ful) \
154 ipc_log_string((dev)->ipc_log_ful, "%s: " fmt, __func__, arg); \
155 if (ep_pcie_get_debug_mask()) \
156 pr_alert("%s: " fmt, __func__, arg); \
157 } while (0)
158
159#define EP_PCIE_DBG2(dev, fmt, arg...) do { \
160 if ((dev)->ipc_log_sel) \
161 ipc_log_string((dev)->ipc_log_sel, \
162 "DBG1:%s: " fmt, __func__, arg); \
163 if ((dev)->ipc_log_ful) \
164 ipc_log_string((dev)->ipc_log_ful, \
165 "DBG2:%s: " fmt, __func__, arg); \
166 if (ep_pcie_get_debug_mask()) \
167 pr_alert("%s: " fmt, __func__, arg); \
168 } while (0)
169
170#define EP_PCIE_DBG_FS(fmt, arg...) pr_alert("%s: " fmt, __func__, arg)
171
172#define EP_PCIE_DUMP(dev, fmt, arg...) do { \
173 if ((dev)->ipc_log_dump) \
174 ipc_log_string((dev)->ipc_log_dump, \
175 "DUMP:%s: " fmt, __func__, arg); \
176 if (ep_pcie_get_debug_mask()) \
177 pr_alert("%s: " fmt, __func__, arg); \
178 } while (0)
179
180#define EP_PCIE_INFO(dev, fmt, arg...) do { \
181 if ((dev)->ipc_log_sel) \
182 ipc_log_string((dev)->ipc_log_sel, \
183 "INFO:%s: " fmt, __func__, arg); \
184 if ((dev)->ipc_log_ful) \
185 ipc_log_string((dev)->ipc_log_ful, "%s: " fmt, __func__, arg); \
186 pr_info("%s: " fmt, __func__, arg); \
187 } while (0)
188
189#define EP_PCIE_ERR(dev, fmt, arg...) do { \
190 if ((dev)->ipc_log_sel) \
191 ipc_log_string((dev)->ipc_log_sel, \
192 "ERR:%s: " fmt, __func__, arg); \
193 if ((dev)->ipc_log_ful) \
194 ipc_log_string((dev)->ipc_log_ful, "%s: " fmt, __func__, arg); \
195 pr_err("%s: " fmt, __func__, arg); \
196 } while (0)
197
198enum ep_pcie_res {
199 EP_PCIE_RES_PARF,
200 EP_PCIE_RES_PHY,
201 EP_PCIE_RES_MMIO,
202 EP_PCIE_RES_MSI,
203 EP_PCIE_RES_DM_CORE,
204 EP_PCIE_RES_ELBI,
205 EP_PCIE_MAX_RES,
206};
207
208enum ep_pcie_irq {
209 EP_PCIE_INT_PM_TURNOFF,
210 EP_PCIE_INT_DSTATE_CHANGE,
211 EP_PCIE_INT_L1SUB_TIMEOUT,
212 EP_PCIE_INT_LINK_UP,
213 EP_PCIE_INT_LINK_DOWN,
214 EP_PCIE_INT_BRIDGE_FLUSH_N,
215 EP_PCIE_INT_BME,
216 EP_PCIE_INT_GLOBAL,
217 EP_PCIE_MAX_IRQ,
218};
219
220enum ep_pcie_gpio {
221 EP_PCIE_GPIO_PERST,
222 EP_PCIE_GPIO_WAKE,
223 EP_PCIE_GPIO_CLKREQ,
224 EP_PCIE_GPIO_MDM2AP,
225 EP_PCIE_MAX_GPIO,
226};
227
228struct ep_pcie_gpio_info_t {
229 char *name;
230 u32 num;
231 bool out;
232 u32 on;
233 u32 init;
234};
235
236struct ep_pcie_vreg_info_t {
237 struct regulator *hdl;
238 char *name;
239 u32 max_v;
240 u32 min_v;
241 u32 opt_mode;
242 bool required;
243};
244
245struct ep_pcie_clk_info_t {
246 struct clk *hdl;
247 char *name;
248 u32 freq;
249 bool required;
250};
251
252struct ep_pcie_reset_info_t {
253 struct reset_control *hdl;
254 char *name;
255 bool required;
256};
257
258struct ep_pcie_res_info_t {
259 char *name;
260 struct resource *resource;
261 void __iomem *base;
262};
263
264struct ep_pcie_irq_info_t {
265 char *name;
266 u32 num;
267};
268
269/* phy info structure */
270struct ep_pcie_phy_info_t {
271 u32 offset;
272 u32 val;
273 u32 delay;
274 u32 direction;
275};
276
277/* pcie endpoint device structure */
278struct ep_pcie_dev_t {
279 struct platform_device *pdev;
280 struct regulator *gdsc;
281 struct ep_pcie_vreg_info_t vreg[EP_PCIE_MAX_VREG];
282 struct ep_pcie_gpio_info_t gpio[EP_PCIE_MAX_GPIO];
283 struct ep_pcie_clk_info_t clk[EP_PCIE_MAX_CLK];
284 struct ep_pcie_clk_info_t pipeclk[EP_PCIE_MAX_PIPE_CLK];
285 struct ep_pcie_reset_info_t reset[EP_PCIE_MAX_RESET];
286 struct ep_pcie_irq_info_t irq[EP_PCIE_MAX_IRQ];
287 struct ep_pcie_res_info_t res[EP_PCIE_MAX_RES];
288
289 void __iomem *parf;
290 void __iomem *phy;
291 void __iomem *mmio;
292 void __iomem *msi;
293 void __iomem *dm_core;
294 void __iomem *elbi;
295
296 struct msm_bus_scale_pdata *bus_scale_table;
297 u32 bus_client;
298 u32 link_speed;
299 bool active_config;
300 bool aggregated_irq;
301 bool mhi_a7_irq;
302 u32 dbi_base_reg;
303 u32 slv_space_reg;
304 u32 phy_status_reg;
305 u32 phy_init_len;
306 struct ep_pcie_phy_info_t *phy_init;
307 bool perst_enum;
308
309 u32 rev;
310 u32 phy_rev;
311 void *ipc_log_sel;
312 void *ipc_log_ful;
313 void *ipc_log_dump;
314 struct mutex setup_mtx;
315 struct mutex ext_mtx;
316 spinlock_t ext_lock;
317 unsigned long ext_save_flags;
318
319 spinlock_t isr_lock;
320 unsigned long isr_save_flags;
321 ulong linkdown_counter;
322 ulong linkup_counter;
323 ulong bme_counter;
324 ulong pm_to_counter;
325 ulong d0_counter;
326 ulong d3_counter;
327 ulong perst_ast_counter;
328 ulong perst_deast_counter;
329 ulong wake_counter;
330 ulong msi_counter;
331 ulong global_irq_counter;
332
333 bool dump_conf;
334
335 bool enumerated;
336 enum ep_pcie_link_status link_status;
337 bool perst_deast;
338 bool power_on;
339 bool suspending;
340 bool l23_ready;
341 bool l1ss_enabled;
342 struct ep_pcie_msi_config msi_cfg;
Yan He08169892017-10-27 17:40:24 -0700[diff] [blame]343 bool no_notify;
344 bool client_ready;
Yan He50222ad2017-11-17 18:22:17 -0800[diff] [blame]345
346 struct ep_pcie_register_event *event_reg;
347 struct work_struct handle_perst_work;
348 struct work_struct handle_bme_work;
Yan He08169892017-10-27 17:40:24 -0700[diff] [blame]349 struct work_struct handle_d3cold_work;
Yan He50222ad2017-11-17 18:22:17 -0800[diff] [blame]350};
351
352extern struct ep_pcie_dev_t ep_pcie_dev;
353extern struct ep_pcie_hw hw_drv;
354
355static inline void ep_pcie_write_mask(void __iomem *addr,
356 u32 clear_mask, u32 set_mask)
357{
358 u32 val;
359
360 val = (readl_relaxed(addr) & ~clear_mask) | set_mask;
361 writel_relaxed(val, addr);
362 /* ensure register write goes through before next regiser operation */
363 wmb();
364}
365
366static inline void ep_pcie_write_reg(void __iomem *base, u32 offset, u32 value)
367{
368 writel_relaxed(value, base + offset);
369 /* ensure register write goes through before next regiser operation */
370 wmb();
371}
372
373static inline void ep_pcie_write_reg_field(void __iomem *base, u32 offset,
374 const u32 mask, u32 val)
375{
376 u32 shift = find_first_bit((void *)&mask, 32);
377 u32 tmp = readl_relaxed(base + offset);
378
379 tmp &= ~mask; /* clear written bits */
380 val = tmp | (val << shift);
381 writel_relaxed(val, base + offset);
382 /* ensure register write goes through before next regiser operation */
383 wmb();
384}
385
386extern int ep_pcie_core_register_event(struct ep_pcie_register_event *reg);
387extern int ep_pcie_get_debug_mask(void);
388extern void ep_pcie_phy_init(struct ep_pcie_dev_t *dev);
389extern bool ep_pcie_phy_is_ready(struct ep_pcie_dev_t *dev);
390extern void ep_pcie_reg_dump(struct ep_pcie_dev_t *dev, u32 sel, bool linkdown);
391extern void ep_pcie_debugfs_init(struct ep_pcie_dev_t *ep_dev);
392extern void ep_pcie_debugfs_exit(void);
393
394#endif